CN210129215U - Dual-redundancy electromechanical management computer architecture - Google Patents
Dual-redundancy electromechanical management computer architecture Download PDFInfo
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Abstract
The application belongs to the technical field of structural design of airborne computer equipment, and particularly relates to a dual-redundancy electromechanical management computer architecture which comprises a first processor, a second processor and a health monitoring processor, wherein the first processor, the second processor and the health monitoring processor are respectively connected with an external bus; the logic processing module of the health monitoring processor is respectively in hard-wire connection with the logic processing modules of the first processor and the second processor; the central processing modules of the first processor and the second processor are respectively connected with the central processing module bus of the health monitoring processor; the central processing module of the health monitoring processor is in hard-wire connection with the logic processing module. The dual-redundancy electromechanical management computer architecture can monitor and correspondingly control the health states of the first processor and the second processor through reasonable architecture layout, and avoids error control caused by selecting invalid data.
Description
Technical Field
The application belongs to the technical field of structural design of airborne computer equipment, and particularly relates to a dual-redundancy electromechanical management computer architecture.
Background
In the internal architecture of the existing dual-redundancy computer, two processors (modules) are arranged, which can process data and output control instructions simultaneously, and a data receiving device can select a data source by itself. A disadvantage of this mode is that it comprises two processors that are functionally identical, and that when one of the processors fails, it will still continue to transmit data, eventually resulting in the receiving device not being able to select valid data.
Although there are health processors (modules) capable of determining and processing the health status of a single target (processor), especially for dual-redundancy computers, the corresponding architecture form of two processors and a health processing device is not described (i.e. the electrical connection relationship between the components after the health processing device is added is not described).
SUMMERY OF THE UTILITY MODEL
In order to solve at least one of the above technical problems, the present application provides a dual-redundancy electromechanical management computer architecture.
The application discloses dual-redundancy electromechanical management computer architecture, including first treater, second treater and health monitoring processor, first treater, second treater and health monitoring processor are inside all to include bus module, logic processing module and central processing module, wherein
In the first processor, the second processor and the health monitoring processor, the central processing module is connected with the bus module through an internal bus to realize the receiving and sending of external data;
the logic processing modules of the first processor and the second processor are respectively connected with the bus modules thereof through hard wires, wherein the logic processing modules are used for sending corresponding level signals to the bus modules according to the received level signals;
the logic processing module of the health monitoring processor is respectively connected with the logic processing modules of the first processor and the second processor through hard wires and sends a horizontal signal;
the central processing modules of the first processor and the second processor are respectively connected with the central processing module of the health monitoring processor through an inter-module bus and send heartbeat signals;
the central processing module of the health monitoring processor is connected with the logic processing module thereof through a hard wire and sends a level signal, and the level signal is obtained by processing the received heartbeat signal by the central processing module;
and the bus modules of the first processor, the second processor and the health monitoring processor are respectively connected with an external bus.
According to at least one embodiment of the present application, the bus module includes at least one of an aviation 1553B bus module, a 1394B bus module, an AFDX bus module, and an FC bus module.
According to at least one embodiment of the present application, the logic processing module comprises a programmable logic controller CLPD or FPGA.
According to at least one embodiment of the present application, the inter-module bus includes at least one of an ARINC429 bus, a 422 bus, and a 485 bus.
According to at least one embodiment of the present application, the internal bus includes a PCI bus, I2At least one of a T-bus and a CAN-bus.
The application has at least the following beneficial technical effects:
according to the dual-redundancy electromechanical management computer architecture, due to the reasonable architecture layout among the first processor, the second processor and the health monitoring processor, the health monitoring processor can monitor and correspondingly control the health states of the first processor and the second processor, redundancy management and switching of data are achieved, processing burden of receiving equipment is effectively relieved, the situation that the health states cannot be reported or are reported mistakenly after a processing module fails (or an output line of the processing module is disconnected) is avoided, and the receiving equipment selects invalid data to cause error control.
Drawings
FIG. 1 is a schematic diagram of a dual-redundancy electromechanical management computer architecture of the present application.
Detailed Description
In order to make the implementation objects, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described in more detail below with reference to the drawings in the embodiments of the present application. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The described embodiments are a subset of the embodiments in the present application and not all embodiments in the present application. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
The dual-redundancy electromechanical management computer architecture of the present application is described in further detail below with reference to fig. 1.
The application discloses a dual-redundancy electromechanical management computer architecture, which comprises a first processor 1, a second processor 2 and a health monitoring processor 3; the first processor 1, the second processor 2 and the health monitoring processor 3 are designed similarly, and each of them may include a bus module 41, a logic processing module 42, a central processing module 43, a power supply (not shown in the figure) and other devices.
Specifically, the central processing module 43 of the first processor 1 is connected to the bus module 41 through the internal bus 5, so as to receive and transmit external data from and to the first processor 1. The central processing module 43 of the second processor 2 is connected with the bus module 41 through the internal bus 5, so as to realize the receiving and sending of the external data by the second processor 2. The central processing module 43 of the health monitoring processor 3 is connected with the bus module 41 through the internal bus 5, so that the health monitoring processor 3 receives and transmits external data.
Further, in the first processor 1, its logic processing module 42 is connected with its bus module 41 through the hard wire 6, and the logic processing module 42 is configured to send a corresponding level signal to the bus module 41 according to the received level signal. Similarly, in the second processor 2, its logic processing module 42 is connected to its bus module 41 via the hard wire 6, and the logic processing module 42 is configured to send a corresponding level signal to the bus module 41 according to the received level signal.
The level signal may be a high level and a low level, and respectively represent different control commands, in this embodiment, the high level preferably represents that the control bus module 41 stops.
Further, the logic processing module 42 of the health monitoring processor 3 is connected to the logic processing modules 42 of the first processor 1 and the second processor 2 through the hard wire 6, respectively, and transmits the level signal. In addition, the central processing module 43 of the health monitoring processor 3 is connected to its logic processing module 42 through the hard wire 6, and transmits level signals corresponding to the first processor 1 and the second processor 2.
Further, the central processing modules 43 of the first processor 1 and the second processor 2 are connected to the central processing module 43 of the health monitoring processor 3 through the inter-module bus 7, respectively, and transmit a heartbeat signal (i.e., heartbeat information).
The level signals corresponding to the first processor 1 and the second processor 2, which are sent by the central processing module 43 of the health monitoring processor 3, are obtained by sending heartbeat signals to the first processor 1 and the second processor 2 for processing. It should be noted that, receiving the heartbeat signal corresponding to the source device through the processing module, and determining whether the heartbeat signal fails after processing is a currently known and relatively mature technology; for example, the heartbeat may be defined as a sequence of [0,1] alternating sent in a period, and when the heartbeat in 25 consecutive data packets received by the processing module and sent by the source device remains unchanged (both are 0 or both are 1), it is determined that the heartbeat state of the source device is abnormal. Other determination manners are not repeated herein, that is, the specific determination method and steps of the health monitoring processor 3 for the health states of the first processor 1 and the second processor 2 are not the points to be protected by the present application and belong to the known technology, so the present application does not relate to the improvement of the computer program, and the emphasis is placed on the electrical connection relationship among the devices of the first processor 1, the second processor 2 and the health monitoring processor 3.
Further, the bus modules 41 of the first processor 1, the second processor 2, and the health monitoring processor 3 are connected to the external bus 8, respectively.
In specific operation, when the health monitoring processor 3 determines that the health of the first processor 1 is abnormal, the high level (stop instruction) is sent to the logic processing module 42 of the health monitoring processor 3 through the hard wire 6, the logic processing module 42 of the health monitoring processor 3 transmits the high level (stop instruction) to the logic processing module 42 of the first processor 1 through the hard wire 6, and the logic processing module 42 of the first processor 1 sends the high level signal to the bus module 41 of the first processor 1 through the hard wire 6, so as to close the bus module 41 (bus card) of the first processor 1.
Similarly, when the health monitoring processor 3 determines that the health of the second processor 2 is abnormal, the logic processing module 42 of the health monitoring processor 3 sends a high level (stop instruction) to the logic processing module 42 of the health monitoring processor 3 through the hard wire 6, the logic processing module 42 of the health monitoring processor 3 transmits a high level (stop instruction) to the logic processing module 42 of the second processor 2 through the hard wire 6, and the logic processing module 42 of the second processor 2 sends a high level signal to the bus module 41 of the second processor 2 through the hard wire 6, so as to close the bus module 41 (bus card) of the second processor 2.
Further, the bus module 41 of the present application may include at least one of an aviation 1553B bus module, a 1394B bus module, an AFDX bus module, and an FC bus module. The logic processing module 42 includes a programmable logic controller CLPD or FPGA. The central processing module 43 includes, but is not limited to, Intel series CPU, DSP, PowerPC series CPU, ARM series CPU. The inter-module bus 7 includes at least one of an ARINC429 bus, a 422 bus, and a 485 bus. The internal bus 5 includes a PCI bus, I2At least one of a T-bus and a CAN-bus.
According to the dual-redundancy electromechanical management computer architecture, due to the reasonable layout of the first processor, the second processor and the health monitoring processor, the health monitoring processor can monitor and correspondingly control the health states of the first processor and the second processor, redundancy management and switching of data are achieved, processing burden of receiving equipment is effectively relieved, the situation that the health states cannot be reported or are reported mistakenly after a processing module fails (or an output line of the processing module is disconnected) is avoided, and the receiving equipment selects invalid data to cause error control.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (5)
1. The dual-redundancy electromechanical management computer architecture is characterized by comprising a first processor (1), a second processor (2) and a health monitoring processor (3), wherein the first processor (1), the second processor (2) and the health monitoring processor (3) internally comprise a bus module (41), a logic processing module (42) and a central processing module (43), and the logic processing module (42) and the central processing module (43) are arranged in the first processor (1), the second processor (2) and the health monitoring processor (3), wherein the bus module, the logic processing module and the central processing module are respectively connected with the
In the first processor (1), the second processor (2) and the health monitoring processor (3), the central processing module (43) is connected with the bus module (41) through an internal bus (5) to realize the receiving and sending of external data;
the logic processing modules (42) of the first processor (1) and the second processor (2) are respectively connected with the bus module (41) thereof through hard wires (6), wherein the logic processing modules (42) are used for sending corresponding level signals to the bus module (41) according to the received level signals;
the logic processing module (42) of the health monitoring processor (3) is respectively connected with the logic processing modules (42) of the first processor (1) and the second processor (2) through hard wires (6) and sends level signals;
the central processing modules (43) of the first processor (1) and the second processor (2) are respectively connected with the central processing module (43) of the health monitoring processor (3) through an inter-module bus (7) and send heartbeat signals;
a central processing module (43) of the health monitoring processor (3) is connected with a logic processing module (42) thereof through a hard wire (6) and sends a level signal, and the level signal is obtained by processing the received heartbeat signal by the central processing module (43);
and the bus modules (41) of the first processor (1), the second processor (2) and the health monitoring processor (3) are respectively connected with an external bus (8).
2. The dual-redundancy electro-mechanical management computer architecture of claim 1, wherein the bus module (41) comprises at least one of an aviation 1553B bus module, a 1394B bus module, an AFDX bus module, and an FC bus module.
3. Dual-redundancy electro-mechanical management computer architecture according to claim 1, characterized in that said logic processing module (42) comprises a programmable logic controller CLPD or FPGA.
4. Dual-redundancy electro-mechanical management computer architecture according to claim 1, characterized in that the inter-module bus (7) comprises at least one of an ARINC429 bus, a 422 bus and a 485 bus.
5. Dual-redundancy electro-mechanical management computer architecture according to claim 1, wherein the internal bus (5) comprises a PCI bus, I2At least one of a T-bus and a CAN-bus.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112702249A (en) * | 2020-12-29 | 2021-04-23 | 中国航空工业集团公司西安飞机设计研究所 | Dual-redundancy ring network architecture |
| CN113850033A (en) * | 2021-09-27 | 2021-12-28 | 广东汇天航空航天科技有限公司 | Redundancy system, redundancy management method and readable storage medium |
| CN115185877A (en) * | 2022-07-29 | 2022-10-14 | 中航机载系统共性技术有限公司 | Dual-redundancy general processing module and information synchronization method thereof |
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2019
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112702249A (en) * | 2020-12-29 | 2021-04-23 | 中国航空工业集团公司西安飞机设计研究所 | Dual-redundancy ring network architecture |
| CN113850033A (en) * | 2021-09-27 | 2021-12-28 | 广东汇天航空航天科技有限公司 | Redundancy system, redundancy management method and readable storage medium |
| CN115185877A (en) * | 2022-07-29 | 2022-10-14 | 中航机载系统共性技术有限公司 | Dual-redundancy general processing module and information synchronization method thereof |
| CN115185877B (en) * | 2022-07-29 | 2023-09-05 | 中航机载系统共性技术有限公司 | Dual-redundancy general processing module and information synchronization method thereof |
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