CN210072612U

CN210072612U - Internet of things chip system

Info

Publication number: CN210072612U
Application number: CN201920938516.9U
Authority: CN
Inventors: 张俊峰
Original assignee: Individual
Current assignee: Individual
Priority date: 2018-11-13
Filing date: 2019-06-20
Publication date: 2020-02-14
Anticipated expiration: 2029-06-20

Abstract

The utility model provides a thing networking chip system, including at least one real-time processor, at least one application processor and general operation treater, wherein, every real-time processor connects all respectively application processor with general operation treater, just at least one application processor or general operation treater by at least one real-time processor awakens up according to the size of the data volume that receives or detect. The utility model discloses a sleep and awaken up through real-time processor control application processor and general operation treater can reduce entire system's consumption, and the business of controlling difference in addition is handled by the treater of difference, and the make full use of resource improves the system performance.

Description

Internet of things chip system

Technical Field

The embodiment of the application relates to the field of circuits, in particular to an Internet of things chip system.

Background

At present, the application of the Internet of things is to construct an actual system based on the existing chip, and power control can be only performed from the levels of the chip, board-level circuit design, system software, bottom layer driving software and the like to optimize power consumption.

With the application scenario of the intelligent hardware becoming more and more complex, the performance requirement on the main control processor of the intelligent hardware becomes higher and higher, and thus the running power consumption of the chip becomes higher and higher — the processor power consumption becomes a main power consumption source of the related application of the intelligent hardware. Especially for a master control processor with excellent performance, the interfaces are large and complete, which often results in a large number of interfaces being unused in an actual system, and this part of interface circuits is also an important source of high power consumption of the processor chip. Therefore, how to perform customized development and system optimization On a chip of a required processor and construct a low-power-consumption and high-performance processor SOC (system On chip) system-On-chip from the characteristics of a specific use scene of the internet of things is an important engineering technical problem in the current technical field.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides an internet of things chip system, which controls the application processor and the general operation processor to sleep and wake up through the real-time processor, reduces the power consumption of the whole system, controls different services to be processed by different processors, makes full use of resources and improves the system performance.

One aspect of the present application provides an internet of things chip system, including at least one real-time processor, at least one application processor and a general operation processor, wherein, every real-time processor connects all respectively the application processor with the general operation processor, and the at least one application processor or the general operation processor is awakened by the at least one real-time processor according to the size of the received or detected data volume.

When the number of the application processors is more than one, the processing capacity of each application processor is the same or different from each other.

Each real-time processor is also connected with an APB (advanced peripheral bus), each application processor is also connected with an AXI (advanced extensible interface) bus, and the APB bus and the AXI bus are connected in a bridging mode.

Further, the APB bus is connected with at least one of the following devices: the system comprises a Serial Peripheral Interface (SPI) device, a general input/output (GPIO) device, an internal integrated circuit I2C device, a Universal Asynchronous Receiver Transmitter (UART) device and a real-time clock (RTC) device.

Further, the AXI bus is connected to at least one of: the device comprises a direct memory access DMA device, a camera device, a joint test group JTAG protocol device, a trusted computer module TCM device, a secure digital input output SDIO device, an embedded multimedia card EMMC device, a universal serial bus USB device and a double-rate DDR controller.

Further, the AXI bus is also connected with a neural network acceleration unit.

Further, the neural network accelerating unit is connected with an acquisition module or an acquisition unit of at least one of the following devices: the device comprises a voice recognition device, a human face recognition device, a retina recognition device, a fingerprint recognition device, a video processing device and an image processing device.

Further, the neural network acceleration unit is also in communication connection with at least one of the following devices: dynamic random access memory, static random access memory, read only memory, and random access memory.

Furthermore, a local buffer is arranged in the neural network acceleration unit.

Further, each real-time processor and each application processor communicate with each other in at least one of the following ways: interrupt mode, Mailbox mode and memory data sharing mode.

According to the Internet of things chip system, the real-time processor controls the application processor and the general operation processor to sleep and wake up, so that the power consumption of the whole system can be reduced, in addition, different services are controlled to be processed by different processors, resources are fully utilized, and the system performance is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic structural diagram of an internet of things chip system according to an embodiment of the present application;

fig. 2 is a schematic view of a workflow of an internet of things chip system according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship. Additionally, the terms "system" and "network" are often used interchangeably herein.

The various embodiments of the present application describe an internet of things Chip system as a system including a System On Chip (SOC) Chip, where Chip and processor are often used interchangeably herein, but essentially represent the same elements. Herein, the SoC system refers to integrating a microprocessor, an analog IP core, a digital IP core, and a memory (or an off-chip memory control interface) on a single chip.

As shown in fig. 1, the chip system of the internet of things according to an embodiment of the present invention includes at least one Real-Time Processor (RTU) 11, at least one Application Processor (APU) 12, and a General purpose Computing Processor (GCEU) 13, which are communicatively connected, for example, the chip system of the internet of things includes one, two, or more Real-Time processors 11 and one, two, or more Application processors 12, which are communicatively connected.

In another embodiment of the present application, the general-purpose arithmetic processor 13 may be replaced by a Digital Signal Processor (DSP), which may process data alone without cooperation of the real-time processor 11.

In another embodiment of the present application, the general arithmetic processor 13 and the DSP may exist at the same time.

After the internet of things chip system is started, the real-time processor 11 is always in an activated state (or a power-on state), when the internet of things chip system is started, the application processor 12 and the general-purpose operation processor 13 and/or the DSP enter a sleep state, and when the application processor 12 and the general-purpose operation processor 13 and/or the DSP are started, the application processor 12 and the general-purpose operation processor 13 and/or the DSP enter the sleep state and are set by the real-time processor 11 or set by the real-time processor. In this embodiment, the starting of the chip system of the internet of things may be a power-on starting or a power-on starting of the chip system of the internet of things, or may be a restart, which is not limited in this embodiment.

However, for the sake of brevity, the following embodiments will be described by taking the general-purpose operation processor 13 as an example.

Each real-time processor 11 is connected to all the application processors 12 and the general-purpose operation processor 13, respectively, the processing capacity of each real-time processor 11 is smaller than that of the general-purpose operation processor 13, and the processing capacity of the general-purpose operation processor 13 is smaller than that of each application processor 12. The processing capacity of each of the real-time processors 11, the processing capacity of each of the application processors 12, and the processing capacity of the general-purpose arithmetic processor 13 correspond to the maximum data amount of the respective processable data. When the number of the application processors 12 is more than one, the processing capabilities of the application processors 12 are different or different from each other.

Preferably, in order to reduce the power consumption of the application processors 12 to the maximum extent, thereby reducing the power consumption of the entire SOC system fundamentally, the number of the application processors 12 may be two or more, and according to different performance requirements, different types of processors may be selected, for example, at least one 32-bit processor and at least one 64-bit processor are selected for combination, and particularly during the use process, a user selects a specific application processor to be used according to a specific application scenario.

The at least one real-time processor 11 is configured to determine whether to process the data by itself or to wake up the general-purpose computing processor or which of the at least one application processor to process the data according to a data size of the received or detected data when receiving or detecting any task data or collected data.

For example, if the data amount of the data is less than or equal to the maximum value of the data amount processed by the at least one real-time processor 11, the at least one real-time processor 11 processes the data.

For another example, the at least one real-time processor 11 is configured to wake up the general-purpose computing processor 13 to process the data when the data amount of the data is greater than the maximum value of the data amount processed by the at least one real-time processor 11 but less than or equal to the maximum value of the data amount processed by the general-purpose computing processor 13, for example, the at least one real-time processor 11 is configured to send an interrupt signal to the general-purpose computing processor 13, the interrupt signal is configured to wake up the general-purpose computing processor 13, and after the general-purpose computing processor 13 is woken up, the at least one real-time processor 11 sends the currently received data to the general-purpose computing processor 13. The general arithmetic processor 13 needs to be controlled by the real-time processor 11, and processes the data under the control of the real-time processor 11.

When the general arithmetic processor 13 and the DSP exist at the same time, the real-time processor 11 sends different services to the general arithmetic processor 13 or the DSP for processing according to the processing capability of the general arithmetic processor 13 and the processing capability of the DSP, wherein the general arithmetic processor 13 needs to be controlled by the real-time processor 11, the data is processed under the control of the real-time processor 11, and the DSP can process the data independently without the cooperation of the real-time processor 11.

For another example, when the real-time processor 11 determines that the received data amount is greater than the maximum value of the data amount processed by the general operation processor 13, it wakes up one of the application processors 12 whose processing capability is greater than the data amount of the data to process the data, if the processing capabilities of two or more application processors in the application processors 12 are greater than the data amount of the data, the real-time processor 11 selects the application server with the largest processing capability and sends an interrupt signal to the application server with the largest processing capability, the interrupt signal wakes up the application server with the largest processing capability, and when the application server with the largest processing capability is woken up, the real-time processor 11 sends the currently received data to the application server with the largest processing capability.

For convenience of description, the following embodiments are described by taking a real-time processor 11 and an application processor 12 as examples.

The real-time processor 11 is directed to relevant tasks that require real-time management and processing, such as sampling and processing of digital or analog signals for various sensors, interrupt requests, etc.; a Real-Time Operation System (RTOS) is directly run on the Real-Time processor 11, so as to ensure excellent Real-Time performance of the Real-Time processor 11 and ensure response speed. The real-time processor 11 has the smallest processing capacity, for example, the smallest CPU size, and is in a power-on state after being started, and the other application processors 12 can perform power-on and power-off operations according to actual tasks during application, thereby ensuring extremely low power consumption.

The general arithmetic processor 13 is used for processing data which come from partial peripheral or sensors and cannot be processed by the real-time processor 11. This allows more tasks to be performed by the real-time processor 11 and the general-purpose arithmetic processor 13 of a smaller size, further reducing the number of times the application processor 12 is woken up, thereby reducing system power consumption.

The application processor 12 is directed to related applications with low real-time requirements and complexity, for example, to biometric applications such as face recognition, fingerprint recognition based on a neural network accelerator. The application processor 12 is characterized in that the application processor does not need to run in the background every moment, only needs to start the application in a specific stage, and can partially power off to enter deep sleep after relevant identification is completed so as to save the power consumption of the system. The power management of the application processor 12 may be managed by the real-time processor 11 according to the situation of the task.

For example, the real-time processor 11 and the application processor 12 may be of the type of an authorized Advanced Reduced Instruction Set Computer (RISC) Machines (ARM) processor family, or alternatively, of the RISCV or LEON processor family, which are commercially available.

For another example, the real-time processor 11 and the Application processor 12 may be a Central Processing Unit (CPU), other general-purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate device or a transistor logic device, a discrete hardware component, or the like. The general processor may be a microprocessor or the processor may be any conventional processor, such as a single chip microcomputer.

The real-time processor 11 is further connected to an Advanced Peripheral Bus (APB), the application processor 12 is further connected to an Advanced eXtensible Interface (AXI) Bus, and the APB Bus and the AXI Bus are connected in a bridging manner.

The APB bus is used for connecting with at least one of the following devices: an SPI device, a general purpose input/Output (GPIO) device, an Inter-Integrated Circuit (I2C) device, a Universal Asynchronous Receiver/Transmitter (UART) device, and a Real-Time Clock (RTC) device, the AXI bus being configured to connect to at least one of the following devices: direct Memory Access (DMA) equipment, an image pickup device, Joint Test Action Group (JTAG) protocol equipment, Trusted Computing Module (TCM) equipment, Secure Digital Input and Output (SDIO) equipment, embedded multimedia Card (EMMC) equipment, USB equipment, and a Double Data Rate (DDR) controller, where the DDR controller is used to connect an external Memory.

In another embodiment of the present application, the AXI bus is also connected to a neural network acceleration unit.

In another embodiment of the present application, the neural network acceleration unit is connected to an acquisition module or an acquisition unit of at least one of the following devices: the device comprises a voice recognition device, a human face recognition device, a retina recognition device, a fingerprint recognition device, a video processing device and an image processing device. In another embodiment of the present application, the neural network acceleration unit further comprises a local buffer (not shown). The neural network acceleration unit is further connected with a memory or comprises a buffer, the neural network acceleration unit is controlled by the APP processor, for example, an acquisition module or an acquisition unit of each device sends data acquired from a corresponding device to the memory connected with the neural network acceleration unit or the buffer of the neural network acceleration unit, and when the APP processor needs to process data, the data is acquired from the memory connected with the neural network acceleration unit or the memory of the neural network acceleration unit through the neural network acceleration unit.

The neural network acceleration unit can effectively process complex algorithms, such as feature point calculation in the process of processing face recognition, a Sobel algorithm of a video image and the like. In order to improve the efficiency of operation, the participation frequency of the application processor 12 can be reduced, and the vector command processing unit of the application processor 12 is designed to perform operation control of the operation array. Meanwhile, in order to reduce the frequent memory access times, a local cache is set inside the neural network acceleration unit.

The real-time processor 11 is further communicatively connected to one of: static Random Access Memory (SRAM), Boot Read-Only Memory (Boot ROM), and Internal Random Access Memory (IRAM).

Each real-time processor and each application processor communicate by at least one of the following modes: interrupt mode, Mailbox mode and memory data sharing mode. For example, the control signal (i.e. interrupt) sent by the real-time processor includes a control word, and the application processor receiving the control signal queries the mailbox according to the control word and queries the corresponding data from the memory according to the result of the mailbox query, as described below.

Interrupting: the interrupt is used for the time information transfer between the real-time processor 11 and the application processor 12. After the real-time processor 11 receives data of an external device, it first determines whether it can process the data according to the data, if it cannot, it determines whether the general arithmetic processor 13 can process the data, if it cannot, it determines whether the application processor 12 needs to be woken up, if so, it turns on the power and clock control of the application processor 12, and sends an interrupt to the application processor 12. After the application processor 12 completes the relevant processing, an interrupt is also sent back to the real-time processor 11. The real-time processor 11 decides whether to let the application processor enter a sleep state according to the application task situation.

Mailbox is used for control information transfer between the real-time processor 11 and the application processor 12. Before the real-time processor 11 sends an interrupt to the application processor 12, the information code that needs to be notified to the application processor 12 is put into the Mailbox. The application processor 12 wakes up to read the relevant control information and then decides on the next data operation based on the control. The Mailbox will also be used for control information transfer of the application processor 12 back to the real-time processor.

Memory data sharing: a memory (not shown) is provided between the application processor 12 and the real-time processor 11, and the memory data is shared for data transfer between the application processor 12 and the real-time processor 11. After the real-time processor 11 collects the relevant data to be processed, it stores the data into the memory, and sends the relevant information of the memory to the application processor 12 through the Mailbox. After the application processor 12 obtains the relevant information, it reads the relevant data to be processed from the memory for processing.

In another embodiment of the present application, each of the real-time processors communicates with the DSP by at least one of: the foregoing details are specifically referred to in the interrupt mode, Mailbox mode, and memory data sharing mode.

In another embodiment of the present application, the system is hosted as an external DDR, data that needs to be processed by the neural network and programs and data of the application processors 12 need to be stored in the external DDR, and in order to improve the execution efficiency of the CPU of each application processor 12, a Cache (Cache) is used for the CPU of each application processor 12.

The real-time processor 11 is always turned on, so that the real-time processor 11 has local instruction and data storage, and also needs a ROM for storing a system boot code, for example, the real-time processor 11 is further connected to a local Memory, such as an SRAM, a boot ROM, and/or an internal Dynamic random access Memory (IRAM).

In summary, through the interactive cooperation mechanism of the real-time processor 11 and the application processor 12, it is possible to implement that the real-time processor 11 with low power consumption and low clock frequency is used to complete the function of keeping the time and the external environment in the application requirement of the internet of things aware, and after the data is accumulated to a certain amount, it is determined whether the real-time processor 11 performs data processing under the cooperation of the necessary general-purpose operation processor 13 according to the task requirement, or it is necessary to wake up part or all of the application processor 12 according to the task evaluation in advance, and then the computing capability of the relevant dedicated accelerator unit connected to the application processor 12 is used to perform computing and feed back the final result. Once the relevant tasks of the application processor 12 are completed, the application processor 12 and the relevant dedicated accelerator unit go back to sleep again, in whole or in part. By using the wake-up and sleep mechanism of all or part of the application processor 12, the power consumption of the application processor 12 part can be reduced to the maximum extent, thereby reducing the power consumption of the whole SOC system fundamentally. As mentioned above, for the at least one application processor 12, a specific application processor combination can be selected according to different performance requirements, and specifically, during the use process, a user selects a specific application processor to be used according to a specific application scenario.

As shown in fig. 2, a schematic view of a workflow of an internet of things chip system according to another embodiment of the present application, the workflow of the internet of things chip system can be as follows.

Step 201, the chip system of the internet of things is powered on.

Step 202, the real-time processor downloads programs to all application processors and completes the initial configuration of the system.

And step 203, completing the state configuration of the peripheral equipment and/or the sensor.

Herein, "peripheral device and/or sensor" means: the presence of only peripheral devices, the presence of only sensors, and the presence of both peripheral devices and sensors. For example, the real-time processor performs status configuration of peripheral devices and/or sensors, for example, the peripheral devices include at least one of: DMA equipment, camera equipment, JTAG protocol equipment, TCM equipment, SDIO equipment, EMMC equipment, USB equipment and DDR controller, SPI equipment, GPIO equipment, I2C equipment, UART equipment and RTC equipment, the sensor includes at least one of following: speech recognition device, face recognition device, retina recognition device, fingerprint identification device.

Step 204, configuring the general arithmetic processor and/or the DSP and all application processors to enter a sleep mode.

Herein, "general purpose arithmetic processor and/or DSP" means: there is only a general-purpose arithmetic processor, only a DSP, and both a general-purpose arithmetic processor and a DSP. For example, the real-time processor configures a general purpose arithmetic processor and/or a DSP and all application processors to enter a sleep mode. Or the general arithmetic processor and/or the DSP automatically enter the sleep mode according to the configuration of the general arithmetic processor and/or the DSP, and each application processor automatically enters the sleep mode according to the configuration of the application processor.

The real-time processor monitors the peripheral devices and/or sensors, step 205.

For example, the real-time processor monitors peripheral devices and/or sensors for interrupt signals or data inputs.

Step 206, whether there is an interrupt for the peripheral device and/or sensor.

For example, the real-time processor determines whether the peripheral device and/or the sensor has an interrupt signal or data input. If so, the process starts in step 207, and if not, the process returns to step 205 to continue monitoring.

Step 207, the real-time processor collects data of peripheral devices and/or sensors.

Step 208, whether to wake up the general purpose computing processor and/or DSP.

For example, the real-time processor determines whether to wake up the general-purpose arithmetic processor and/or the DSP according to the data size of the collected data.

For example, if the data amount of the data is greater than the maximum data processing amount of the real-time processor but less than or equal to the maximum data processing amount of the general-purpose operation processor, the real-time processor wakes up the general-purpose operation processor and/or the DSP, and step 212 and step 213 are performed.

For example, if the data amount of the data is larger than the maximum value of the data amount processed by the general purpose computing processor and/or the DSP, the real-time processor determines not to wake up the general purpose computing processor and/or the DSP, and performs

step

209 and 211.

Step 209, whether to wake up the application processor.

For example, if the real-time processor determines that the data amount of the collected data is greater than the maximum value of the data amount processed by the general operation processor, the real-time processor wakes up the application processor to process the data, and then step 210 is executed.

In another embodiment of the present application, if there are two or more application processors, the real-time processor wakes up one of the two or more application processors having a processing capability greater than the data amount of the data to process the data, and then step 210 is executed.

Step 210, the application processor performs data processing.

In step 211, the application processor returns an interrupt and proceeds to step 204.

At step 212, the general purpose arithmetic processor performs data processing and/or DSP.

The general arithmetic processor processes data under the control of the real-time processor, and the DSP can process data independently without the cooperation of the real-time processor.

In step 213, the general purpose arithmetic processor and/or DSP returns an interrupt to step 204.

The memories described above may be used to store program codes or instructions, the program codes including computer operation instructions, and the real-time processor 11 and the application processor 12 are used to execute the program codes or instructions stored in the respective memories, so as to implement the respective working processes or functions of the internet of things chip system described in the foregoing embodiments. The memory may comprise volatile memory, such as Random Access Memory (RAM), which may include SRAM or DRAM. The memory may also include a non-volatile memory (non-volatile memory), such as a read-only memory (PROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory may also be external flash memory, at least one disk memory, or a buffer.

As will be appreciated by one of ordinary skill in the art, various aspects of the present application, or possible implementations of various aspects, may be embodied as a system, method, or computer program product. Accordingly, aspects of the present application, or possible implementations of aspects, may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "circuit," module "or" system. Furthermore, aspects of the present application, or possible implementations of aspects, may take the form of a computer program product, which refers to computer-readable program code stored in a computer-readable storage medium.

The computer readable storage medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing, such as Random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, and portable read-only memory (CD-ROM).

A processor in the computer reads the computer-readable program code stored in the computer-readable storage medium, so that the processor can perform the functional actions specified in each step, or a combination of steps, in the flowcharts; and means for generating a block diagram that implements the functional operation specified in each block or a combination of blocks.

The computer readable program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. It should also be noted that, in some alternative implementations, the functions noted in the flowchart or block diagram block may occur out of the order noted in the figures. For example, two steps or two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.

For example, another embodiment of the present application provides a computer-readable storage medium having stored therein program code for execution by a real-time processor, the program code including instructions for performing the functions and processes described above for the real-time processor.

For example, another embodiment of the present application provides a computer-readable storage medium having stored therein program code for execution by an application processor, general-purpose arithmetic processor, and/or DSP, the program code comprising instructions for performing the functions and processes described above for the application processor, general-purpose arithmetic processor, and/or DSP.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. An Internet of things chip system is characterized by comprising at least one real-time processor, at least one application processor and a general operation processor, wherein each real-time processor is respectively connected with all the application processors and the general operation processor, and the at least one application processor or the general operation processor is awakened by the at least one real-time processor according to the size of received or detected data volume;

when the number of the application processors is more than one, the processing capacity of each application processor is the same or different from each other;

2. The internet of things chip system of claim 1, wherein the APB bus is connected to at least one of: the system comprises a Serial Peripheral Interface (SPI) device, a general input/output (GPIO) device, an internal integrated circuit I2C device, a Universal Asynchronous Receiver Transmitter (UART) device and a real-time clock (RTC) device.

3. The internet of things chip system of claim 1, wherein the AXI bus is connected to at least one of: the device comprises a direct memory access DMA device, a camera device, a joint test group JTAG protocol device, a trusted computer module TCM device, a secure digital input output SDIO device, an embedded multimedia card EMMC device, a universal serial bus USB device and a double-rate DDR controller.

4. The internet of things chip system of claim 2, wherein the AXI bus is further connected to a neural network acceleration unit.

5. The chip system of the internet of things of claim 3, wherein the neural network acceleration unit is connected with the acquisition module or the acquisition unit of at least one of the following devices: the device comprises a voice recognition device, a human face recognition device, a retina recognition device, a fingerprint recognition device, a video processing device and an image processing device.

6. The internet of things chip system of claim 4, wherein the neural network acceleration unit is further communicatively connected to at least one of: dynamic random access memory, static random access memory, read only memory, and random access memory.

7. The internet of things chip system of claim 2, wherein a local buffer is arranged in the neural network acceleration unit.

8. The internet of things chip system of claim 1, wherein each real-time processor communicates with each application processor by at least one of: interrupt mode, Mailbox mode and memory data sharing mode.