CN209815676U - MEMS structure - Google Patents
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- CN209815676U CN209815676U CN201822243225.6U CN201822243225U CN209815676U CN 209815676 U CN209815676 U CN 209815676U CN 201822243225 U CN201822243225 U CN 201822243225U CN 209815676 U CN209815676 U CN 209815676U
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Abstract
The application discloses a MEMS structure. The MEMS structure includes: a cavity in the semiconductor substrate; a sensitive diaphragm located over the cavity; and a plurality of sensing resistors located in the sensing diaphragm; the sensitive membrane comprises an island part and a connecting part surrounding the island part, the thickness of the island part is larger than that of the connecting part, and the plurality of sensitive resistors are located on the connecting part. The structure adopts the sensitive membrane with uneven thickness, so that the pressure is concentrated on the connecting part to improve the sensitivity.
Description
Technical Field
The present invention relates to the field of microelectronics, and more particularly, to MEMS structures and methods of making the same.
Background
MEMS devices are micro-electromechanical devices that have been developed based on microelectronics and are fabricated using micro-fabrication processes, and have been widely used as sensors and actuators. For example, the MEMS device may be a pressure sensor, accelerometer, gyroscope, silicon condenser microphone.
The pressure sensor includes, for example, a sensor chip and a circuit chip assembled together. Wherein the MEMS structure is formed in the sensor chip and the detection circuit is formed in the circuit chip. The sensor chip and the circuit chip are then bonded together by a die bonding technique to form the MEMS assembly.
Pressure sensors can be classified into various types, including piezoresistive, capacitive, resonant, etc., according to detection elements and methods. Piezoresistive pressure sensors have appeared in the last 60 th century. Compared with other types of pressure sensors, the piezoresistive pressure sensor has obvious advantages, such as high sensitivity, quick response, high reliability, low power consumption, miniaturization and the like. With the progress of technology, the technology of piezoresistive pressure sensors using MEMS structures has grown, and mass production and cost reduction have been achieved.
The existing piezoresistive pressure sensor is mainly formed by micromachining by utilizing a bulk silicon technology, and comprises a sensitive diaphragm positioned above a cavity, a piezoresistor positioned on the sensitive diaphragm and a detection circuit. The sensing diaphragm is, for example, square or circular in shape, and the detection circuit detects the external pressure change, for example, by means of a wheatstone bridge including piezoresistors.
The main performance parameters of a pressure sensor are sensitivity and linearity. In conventional pressure sensors, the sensing diaphragm is a flat diaphragm that is fixed at its periphery. The sensitivity of the sensitive membrane is improved by adopting a method of reducing the thickness of the sensitive membrane. However, when the sensitive diaphragm is thinned, the surface stress of the sensitive diaphragm will cause a severe increase in the nonlinearity. Therefore, the sensing diaphragm with the planar structure is mainly used for a pressure sensor with a medium-high range, and is not suitable for manufacturing a pressure sensor with a small range. As a result, the size of the pressure sensor is difficult to reduce.
Therefore, it is desired to further improve the MEMS structure for the pressure sensor so that the sensitivity and linearity can be improved while miniaturization is possible.
SUMMERY OF THE UTILITY MODEL
Accordingly, it is an object of the present invention to provide a MEMS structure and a method for fabricating the same, in which a sensing diaphragm having a non-uniform thickness is used to concentrate a pressure on a connection portion to improve sensitivity.
The utility model provides a MEMS structure, include:
a cavity in the semiconductor substrate;
a sensitive diaphragm located over the cavity; and
a plurality of sensing resistors located in the sensing diaphragm;
the sensitive membrane comprises an island part and a connecting part surrounding the island part, the thickness of the island part is larger than that of the connecting part, and the plurality of sensitive resistors are located on the connecting part.
Preferably, a well region surrounding the cavity is also included.
Preferably, the sensitive membrane comprises:
a third doped region forming an island frame of the sensitive membrane;
a fifth doping area of the connecting part frame of the sensitive membrane is formed; and
an epitaxial layer on the third doped region and the fifth doped region,
the third doped region and the fifth doped region form a grid pattern, the epitaxial layer covers the third doped region and the fifth doped region and fills meshes of the grid pattern to close the cavity.
Preferably, the fifth doped region surrounds the third doped region.
Preferably, the plurality of sensitive resistors are doped regions in the epitaxial layer.
Preferably, the method further comprises the following steps:
an interlayer dielectric layer located on the epitaxial layer; and
through the interlevel dielectric layer to a plurality of sensitive resistive interconnects.
Preferably, the plurality of sensitive resistors are uniformly distributed on the connecting part of the sensitive membrane.
Preferably, the plurality of sensing resistors are interconnected in a wheatstone bridge.
Preferably, the semiconductor substrate and the sensitive resistor are of a first doping type, the well region, the third doping region and the fifth doping region are of a second doping type, and the first doping type is opposite to the second doping type.
Preferably, the first doping type is P-type and the second doping type is N-type.
Preferably, the junction depth of the well region is greater than the junction depth of the third doped region, and the junction depth of the third doped region is greater than the junction depth of the fifth doped region.
Preferably, the island-like portion and the connection portion are plural, and the island-like portion and the connection portion are provided at an interval.
According to the utility model discloses MEMS structure forms the sensitive diaphragm of inhomogeneous thickness in the cavity top, receives pressure effect at sensitive diaphragm, concentrates on the less connecting portion of thickness with pressure to make the sensitivity of MEMS structure obtain improving, but also can realize overvoltage protection and nonlinear compensation. The thickness of the island-shaped part is larger than that of the connecting part, so that the island-shaped part is equivalent to the function of the baffle plate, when the sensitive membrane is subjected to larger pressure, the bearable deformation quantity of the sensitive membrane is larger, the sensitive membrane is not easy to break, and the sensitivity is higher.
In a preferred embodiment, the third doped region and the fifth doped region are used to form an island part and a connection part frame of the sensitive membrane respectively, the frame is a grid pattern, and the epitaxial growth characteristic of the epitaxial layer is used to fill the meshes of the grid pattern. The structure transfers the thickness control of the island-shaped part and the connecting part into the junction depth control of the two doped regions, so that the deep groove etching of multiple steps can be avoided, the process is simplified, the precision of the thickness control is improved, and the precision and the yield of the MEMS structure are improved. The structure avoids the defects of a bonding process, is realized on a single wafer, has simple manufacturing method and low cost, and is easy to integrate with a CMOS circuit.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 to 13 show cross-sectional views of a MEMS structure manufacturing method according to an embodiment of the present invention at various stages, respectively.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.
Numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The present invention may be presented in a variety of forms, some of which are described below.
Fig. 1 to 13 show cross-sectional views of a MEMS structure manufacturing method according to an embodiment of the present invention at various stages, respectively.
The method starts with a semiconductor substrate 201. The substrate is for example a B-doped P-type silicon substrate, with a crystal orientation of for example <100> and a resistivity of for example 5-10 ohm cm.
Then, a resist mask 101 having an opening is formed on the surface of the semiconductor substrate 201 by a photolithography method. A first ion implantation is performed through a photoresist mask to form a first doped region 102 of N + type in the semiconductor substrate 201, as shown in fig. 1.
The N-type dopant used in the first ion implantation is, for example, phosphorus ions. By controlling the energy of the ion implantation, the first doped region 102 is extended downward from the surface of the semiconductor substrate 201 to a predetermined depth. After the first ion implantation, the photoresist mask 101 is removed, for example, by ashing or dissolution.
Then, high temperature annealing is performed, so that the dopants in the first doped region 102 are diffused to form a well region 103 of N + type, as shown in fig. 2.
The depth of the well region 103 is, for example, 5 to 15 micrometers. The well region 103 surrounds a first region of the semiconductor substrate 201 for defining a shape in which a cavity is to be formed. Rinsing with, for example, HF acid after the high temperature annealing is performed to remove the silicon oxide layer on the surface of the semiconductor substrate 201.
Then, for example, a chemical vapor deposition process is used to sequentially form the first insulating layer 104 and the second insulating layer 105 on the surface of the semiconductor substrate 201. The first insulating layer 104 is, for example, a silicon oxide layer, having a thickness of less than 200 nm, for example, a thickness of 20 nm. The second insulating layer 105 is, for example, a silicon nitride layer having a thickness of about 200 to 500 nm.
A portion of the first insulating layer 104 and the second insulating layer 105 is etched away via the photoresist mask, thereby forming an opening 301. The etching stops, for example, at the surface of the semiconductor substrate 201 due to the etch selectivity between the different materials. The photoresist mask is removed after etching, as shown in fig. 3.
In this embodiment, the opening 301 substantially corresponds to a first region surrounded by the well region 103, thereby exposing the entire first region. In an alternative embodiment, the opening 301 is located over a first region surrounded by the well region 103, thereby exposing only a portion of the first region. In a subsequent electrochemical etching step, the patterned first insulating layer 104 and the second insulating layer 105 together act as a hard mask.
Then, a resist mask 106 having an opening is formed on the surface of the semiconductor substrate 201 by a photolithography method. A second ion implantation is performed through the photoresist mask to form a second doped region 107 of N-type in the semiconductor substrate 201, as shown in fig. 4.
The N-type dopant used in the second ion implantation is, for example, phosphorus ions. By controlling the energy of the ion implantation, the second doped region 107 is extended downward from the surface of the semiconductor substrate 201 to a predetermined depth. After the second ion implantation, the photoresist mask 106 is removed, for example, by ashing or dissolution.
Then, a high temperature anneal is performed so that the dopants in the second doped region 107 are diffused to form a third doped region 108 of N-type, as shown in fig. 5.
The depth of the third doped region 108 is smaller than the depth of the well region 103, for example, 2 to 10 μm. The third doped regions 108 form a grid-like pattern in the first region of the semiconductor substrate 201 for forming a framework of islands in the final device. The junction depth of the third doped region 108 will determine the thickness of the island.
Then, a resist mask 109 having an opening is formed on the surface of the semiconductor substrate 201 by a photolithography method. A third ion implantation is performed through the photoresist mask to form a fourth doped region 110 of N-type in the semiconductor substrate 201, as shown in fig. 6.
The N-type dopant used in the third ion implantation is, for example, phosphorus ions. By controlling the energy of the ion implantation, the fourth doped region 110 is extended downward from the surface of the semiconductor substrate 201 to a predetermined depth. After the third ion implantation, the photoresist mask 109 is removed, for example, by ashing or dissolution.
Then, a high temperature annealing is performed so that the dopant in the fourth doping region 110 is diffused to form a fifth doping region 111 of N-type, as shown in fig. 7.
The junction depth of the fifth doped region 111 is smaller than the junction depth of the third doped region 108, for example, 1 to 5 μm. The fifth doped region 111 surrounds the third doped region 108 and forms a grid-like pattern in the first region of the semiconductor substrate 201 for forming a frame of connections in the final device. The junction depth of the fifth doped region 111 will determine the thickness of the connection.
Then, in the first region of the semiconductor substrate 201, the porous layer 112 is formed by electrochemical etching, as shown in fig. 8.
In this step, the first insulating layer 104 and the second insulating layer 105 are used together as a hard mask. The entire semiconductor structure is immersed in an acidic solution, such as an ethanol/hydrofluoric acid/water mixture, or an acetone/hydrofluoric acid/water mixture. For example, the ethanol of the acidic solution: the volume ratio of hydrofluoric acid (50%) is 1: 1.
electrochemical etching is generated in the first region of the semiconductor substrate 201, thereby forming the porous layer 112 extending downward from the surface. The well 103 of N + type, the third doped region 108 of N-type and the fifth doped region 111 do not electrochemically react and still maintain a single crystal structure. The entire semiconductor structure is then removed from the etching solution and cleaned, thereby completing the electrochemical etching step.
The porous layer 112 is then removed to form a cavity 302, as shown in FIG. 9.
In this step, the porous silicon layer 112 is removed by wet etching. For example, an alkaline etchant (for example, SC1) or a tetramethylammonium hydroxide (TMAH) etchant is used as the etchant. Due to the selectivity of the etchant, the porous silicon layer 112 is removed with respect to the semiconductor substrate 201, the well region 103, the third doped region 108, and the fifth doped region 111.
After etching, the third doped region 108 is a grid pattern as a framework of an island portion, and the fifth doped region 111 is a grid pattern as a framework of a connection portion. The cavity 302 is located below the third doped region 108 and the fifth doped region 111, and communicates with the outside via the mesh of the grid-like pattern. The depth of the cavity 302 corresponds approximately to the junction depth of the well region 103, for example 3 to 10 microns.
Then, an epitaxial layer 113 of N-type is formed over the cavity 302, the epitaxial layer 113 enclosing the cavity 302, as shown in fig. 10.
For example, a low pressure chemical vapor deposition (LPVCD) method, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, or the like may be used to epitaxially grow single crystal silicon with the third doped region 108 and the fifth doped region 111 as a frame, thereby forming the N-type epitaxial layer 113. The gas source used in the epitaxial growth is, for example, SiH2Cl2The temperature is, for example, 900 to 1200 degrees celsius. The thickness of epitaxial layer 113 can be controlled by controlling the composition and concentration of the vapor phase precursor and the deposition time. In this embodiment, the thickness of the epitaxial layer 113 is, for example, 6 to 10 microns, preferably 8 microns.
Due to the nature of epitaxial growth, the epitaxial layer 113 not only grows vertically on the surface of the semiconductor substrate 201, the well region 103, the third doped region 108, and the fifth doped region 111, but also grows laterally on the inner walls of the meshes in the grid-like pattern formed by the third doped region 108 and the fifth doped region 111, thereby filling the meshes and thus closing the cavities 302.
The epitaxial layer 113 together with the third doped region 108 and the fifth doped region 111 form a sensitive membrane suspended above the cavity 302. An island 202A of the sensitive membrane is formed at a corresponding position of the third doped region 108, and a connection 202B of the sensitive membrane at a corresponding position of the fifth doped region 111 connects the island 202A to the well region 103. The thickness of the island 202A is greater than the thickness of the connection 202B, corresponding to the junction depths of the third doped region 108 and the fifth doped region 111, respectively. The thickness of the island-shaped part is larger than that of the connecting part, so that the island-shaped part is equivalent to the function of the baffle plate, when the sensitive membrane is subjected to larger pressure, the bearable deformation quantity of the sensitive membrane is larger, the sensitive membrane is not easy to break, and the sensitivity is higher.
The figure shows only a single island 202A and a connection 202B surrounding the island 202A, and further, a plurality of islands 202A and a plurality of connections 202B may be formed by the above method, wherein the plurality of islands 202A and the plurality of connections 202B are disposed at intervals.
Then, a resist mask having an opening is formed on the surface of the epitaxial layer 113 by a photolithography method. A fourth ion implantation is performed through the photoresist mask to form a P-type sensitive resistor 114 in the epitaxial layer 113, as shown in fig. 11.
The P-type dopant used in the fourth ion implantation is, for example, phosphorus ions. By controlling the energy of the ion implantation, the sensitive resistor 114 is extended downward from the surface of the epitaxial layer 113 to a predetermined depth. For example, the junction depth of the sense resistor 114 is about 1 micron to 2 microns. A tilt angle of 7 to 10 degrees may be used in the implantation and the photoresist mask is removed after the fourth ion implantation, for example by ashing or dissolution.
In the MEMS structure, for example, four sensitive resistors 114 are formed, and are symmetrically distributed in the connecting portion 202B of the sensitive membrane.
Then, an interlayer dielectric layer 115 is formed on the surface of the epitaxial layer 113, and an opening 303 to the sensitive resistor 114 is formed in the interlayer dielectric layer 115, as shown in fig. 12.
In the step of forming the interlayer dielectric layer 115, for example, by the above-mentioned known deposition process, preferably, chemical vapor deposition is used to form borophosphosilicate glass (BPSG) or Tetraethylorthosilicate (TEOS) on the surface of the semiconductor structure as the interlayer dielectric layer 115.
In the step of forming the opening, for example, a resist layer is formed on the surface of the interlayer dielectric layer 115, and a pattern including the opening is formed in the resist layer by a photolithography process. The exposed portions of the insulating layer are removed with a selective etchant using the resist layer as a mask. Due to the selectivity of the etching, the etching may stop at the surface of the sensitive resistor 114. After etching, the resist layer may be removed by ashing or dissolution in a solvent.
Then, an interconnect 116 electrically connecting the sensitive resistor 114 via the opening is formed on the interlayer dielectric layer 115, as shown in fig. 13.
In the above step of forming the interconnect, a conductor layer, such as aluminum, is formed, for example, by sputtering. The conductor layer fills the opening in the interlayer dielectric layer 115 and also covers the surface of the interlayer dielectric layer 115. Preferably, Chemical Mechanical Planarization (CMP) may be further employed to planarize the surface of the conductor layer and to pattern the conductor layer into the interconnects 116.
The above-mentioned interconnect 116 provides an electrical connection to the sensitive resistor 114. In the case where the MEMS sensor is a piezoresistive sensor, the interconnection 116 connects the four sensing resistors 114 into a wheatstone bridge.
The method forms a MEMS structure 100 as shown in fig. 13. The MEMS structure 100 includes a cavity 302 formed in a semiconductor substrate 201, a sensitive diaphragm 202 located over the cavity 302, and a plurality of sensitive resistors 114 located in the sensitive diaphragm 202.
In this embodiment, well region 103 surrounds cavity 302. The sensitive diaphragm 202 includes an island 202A and a connection portion 202B surrounding the island 202A, and a thickness of the island 202A is larger than a thickness of the connection portion 202B. Further, the sensitive membrane 202 includes an island frame formed by the third doped region 108, a connection frame formed by the fifth doped region 111, and the epitaxial layer 113 located on the third doped region 108 and the fifth doped region 111. The third doped region 108 and the fifth doped region 111 form a grid pattern, and the epitaxial layer 113 covers the third doped region 108 and the fifth doped region 111 and fills the meshes of the grid pattern to close the cavity 302. The sense resistor 114 is located in the epitaxial layer 113 corresponding to the position of the connection portion 202B. The junction depth of the third doped region 108 is greater than the junction depth of the fifth doped region 111, and the fifth doped region 111 surrounds the third doped region 108. Further, the junction depth of the third doped region 108 and the fifth doped region 111 is smaller than the junction depth of the well region 103.
The MEMS structure 100 further includes an interlevel dielectric layer 115 overlying the epitaxial layer 113, and an interconnect 116 passing through the interlevel dielectric layer 115 to the plurality of sensitive resistors 114. The plurality of sensing resistors 114 are uniformly distributed on the connecting portion 202B of the sensing diaphragm, and form a wheatstone bridge via interconnection.
In the MEMS structure, the semiconductor substrate 201 and the sensitive resistor 114 are, for example, P-type doped regions, and the well region 103, the third doped region 108 and the fifth doped region 111 are, for example, N-type doped regions.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.
Claims (12)
1. A MEMS structure, comprising:
a cavity in the semiconductor substrate;
a sensitive diaphragm located over the cavity; and
a plurality of sensing resistors located in the sensing diaphragm;
the sensitive membrane comprises an island part and a connecting part surrounding the island part, the thickness of the island part is larger than that of the connecting part, and the plurality of sensitive resistors are located on the connecting part.
2. The MEMS structure of claim 1, further comprising a well region surrounding the cavity.
3. The MEMS structure of claim 2, wherein the sensitive diaphragm comprises:
a third doped region forming an island frame of the sensitive membrane;
forming a fifth doped region of a connecting part frame of the sensitive membrane; and
an epitaxial layer on the third doped region and the fifth doped region,
wherein the third doped region and the fifth doped region form a grid pattern, the epitaxial layer covers the third doped region and the fifth doped region and fills meshes of the grid pattern to close the cavity.
4. The MEMS structure of claim 3, wherein the fifth doped region surrounds the third doped region.
5. The MEMS structure of claim 3, wherein the plurality of sensitive resistors are doped regions in the epitaxial layer.
6. The MEMS structure of claim 5, further comprising:
an interlayer dielectric layer located on the epitaxial layer; and
an interconnect through the interlevel dielectric layer to the plurality of sensitive resistors.
7. The MEMS structure of claim 6, wherein the plurality of sensing resistors are uniformly distributed at the connecting portion of the sensing diaphragm.
8. The MEMS structure of claim 6, wherein the plurality of sensitive resistors are interconnected in a wheatstone bridge.
9. The MEMS structure of claim 3, wherein the semiconductor substrate and the sensitive resistor are of a first doping type, and the well region, the third doped region, and the fifth doped region are of a second doping type, the first doping type being opposite to the second doping type.
10. The MEMS structure of claim 9, wherein the first doping type is P-type and the second doping type is N-type.
11. The MEMS structure of claim 9, wherein the junction depth of the well region is greater than the junction depth of the third doped region, and wherein the junction depth of the third doped region is greater than the junction depth of the fifth doped region.
12. The MEMS structure of claim 1, wherein the island and the connection are plural, the island being spaced apart from the connection.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109678102A (en) * | 2018-12-28 | 2019-04-26 | 杭州士兰集成电路有限公司 | MEMS structure and its manufacturing method |
| US11305985B2 (en) | 2018-12-29 | 2022-04-19 | Hangzhou Silan Integrated Circuit Co., Ltd. | MEMS device and manufacturing method thereof |
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2018
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109678102A (en) * | 2018-12-28 | 2019-04-26 | 杭州士兰集成电路有限公司 | MEMS structure and its manufacturing method |
| US11305985B2 (en) | 2018-12-29 | 2022-04-19 | Hangzhou Silan Integrated Circuit Co., Ltd. | MEMS device and manufacturing method thereof |
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