CN209787040U - power impact detection circuitry is prevented to power and have this detection circuitry's power - Google Patents
power impact detection circuitry is prevented to power and have this detection circuitry's power Download PDFInfo
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- CN209787040U CN209787040U CN201920559275.7U CN201920559275U CN209787040U CN 209787040 U CN209787040 U CN 209787040U CN 201920559275 U CN201920559275 U CN 201920559275U CN 209787040 U CN209787040 U CN 209787040U
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Abstract
the utility model provides a power supply anti-power impact detection circuit and a power supply with the same, wherein the circuit comprises a signal sampling circuit arranged at the power supply side of an inverter circuit, and the output end of the signal sampling circuit is connected with the signal input end of a monitoring chip; the signal sampling circuit comprises 1 or more sampling resistors which are mutually connected in parallel, and when the number of the sampling resistors is 1, the signal sampling circuit is connected with the original sampling resistor on the power supply side of the inverter circuit in parallel; when the sampling resistor is a plurality of, signal sampling circuit independently sets up in inverter circuit power supply side or connects in parallel with the original sampling resistor of inverter circuit power supply side. Compared with a signal sampling circuit formed by a single sampling resistor, the sampling resistors can share the same role during power impact, the risk that the sampling resistors are burnt by power impact current is reduced, the power supply detection circuit can work continuously, and the power supply detection is not interrupted due to the fact that power impact generates faults.
Description
Technical Field
The utility model relates to a power supply detection circuitry, concretely relates to power impact detection circuitry is prevented to power and has this detection circuitry's power.
Background
Currently, power supplies, such as UPS power supplies, are used to provide a stable, uninterrupted supply of power to a single computer, computer network system, street lamp, or other power electronic device, such as a solenoid valve, pressure transmitter, or other load. A UPS (uninterruptible Power Supply) is a System device that connects a battery to a host and converts direct current Power into commercial Power through a module circuit such as a host inverter. When the mains supply is input normally, the UPS supplies the mains supply to the load for use after stabilizing the voltage of the mains supply, and the UPS is an alternating current mains supply voltage stabilizer and also charges a battery at the load end; when the commercial power is interrupted, the UPS immediately supplies the direct current electric energy of the battery to the load by an inversion zero switching conversion method to continuously supply 220V alternating current to ensure that the load keeps normal work and protects the software and hardware of the load from being damaged. Therefore, the UPS power supply is a core device of a system where the load is located, and the running state of the UPS power supply system directly determines whether the load can run normally, stably and reliably, so that it is necessary to monitor the working state of the UPS power supply.
in the prior art, integrated monitoring chips such as EG8010 and EG8011 are generally used to monitor output voltage, output current, output fluctuation, etc. of a power supply, and these chips generally have a function of controlling an inverter circuit to implement dc-to-ac inversion. A signal sampling resistor is usually arranged between a direct-current ground terminal of an inverter circuit of the UPS power supply and ground, and a monitoring chip detects the state of voltage at two ends of the signal sampling resistor to obtain the output voltage of the UPS power supply and/or the state of the output voltage in real time. However, in practical applications, when a load is started or stopped or power supply is switched, a large power surge is generated, the amplitude of the voltage and the current at this time is often more than twice of the normal value, and particularly when multiple loads are started or stopped simultaneously, the surge of the power detection end of the UPS is larger (can reach 5-6 times of the rated current), and the UPS enters a protection program and cannot continue to work.
SUMMERY OF THE UTILITY MODEL
In order to overcome the defects existing in the prior art, the utility model aims to provide a power surge detection circuit is prevented to power and has this detection circuit's power.
In order to achieve the above object of the present invention, according to a first aspect of the present invention, the present invention provides a power supply anti-power impact detection circuit, comprising a signal sampling circuit disposed on the power supply side of an inverter circuit, wherein the output end of the signal sampling circuit is connected to the signal input end of a monitoring chip;
the signal sampling circuit comprises 1 or more sampling resistors which are connected in parallel with each other,
When the number of the sampling resistors is 1, the signal sampling circuit is connected with the original sampling resistor on the power supply side of the inverter circuit in parallel;
when the sampling resistor is a plurality of, signal sampling circuit independently sets up in inverter circuit power supply side or connects in parallel with the original sampling resistor of inverter circuit power supply side.
the beneficial effects of the above technical scheme are: add signal sampling circuit or connect signal sampling circuit in the both ends of the original sampling resistor of inverter circuit power supply side and connect in parallel at inverter circuit power supply side, the signal sampling circuit that single sampling resistor constitutes relatively, power impulse current can be born jointly to a plurality of sampling resistors, has reduced the risk that sampling resistor is burnt by power impulse current, is of value to power monitoring circuit continuous work in addition, does not break off the current monitoring to the power because of power impact produces the trouble.
In a preferred embodiment, a first end of the signal sampling circuit is connected to a ground terminal of the inverter circuit and a signal input terminal of the monitoring chip, respectively, and a second end of the signal sampling circuit is connected to ground.
the beneficial effects of the above technical scheme are: the signal sampling circuit is arranged between the grounding end of the inverter circuit and the ground, so that the implementation is convenient, and the current of the inverter circuit can be stably sampled.
In a preferred embodiment, the power supply further comprises a switching circuit, wherein the switching circuit comprises an electric control switch, a comparator and a first reference power supply;
The first end of the signal sampling circuit is respectively connected with the grounding end of the inverter circuit, the signal input end of the monitoring chip, the positive input end of the comparator and the first end of the original resistor on the power supply side of the inverter circuit, a normally open contact of the electric control switch is connected between the second end of the signal sampling circuit and the ground in series, and the second end of the original resistor on the power supply side of the inverter circuit is connected with the ground; the negative input end of the comparator is connected with the output end of the first reference power supply, the output end of the comparator is connected with the input end of the trigger, and the output end of the trigger is connected with the on-off control end of the electric control switch;
the voltage value of the output end of the first reference power supply is larger than the voltage value of the first end of the original resistor on the power supply side of the inverter circuit when no power impact exists, and is smaller than the voltage value corresponding to the rated power of the original resistor on the power supply side of the inverter circuit.
The beneficial effects of the above technical scheme are: when no power impact exists, the comparator outputs a low level, the trigger outputs a low level, two contacts of the electric control switch are in a disconnected state, the signal sampling circuit does not participate in work, and only the original resistor on the power supply side of the inverter circuit samples; when power impact occurs, and the voltage value of the first end of the original resistor on the power supply side of the inverter circuit is higher than the voltage value of the output end of the first reference power supply, the output of the comparator is changed from low to high, the trigger outputs high level to enable the two contacts of the electric control switch to be connected, and the signal sampling circuit starts to work. Therefore, the signal sampling circuit is ensured to participate in working only when the power impact is large, and the hierarchical circuit protection is formed on the premise of ensuring that the current detection of the power supply is uninterrupted.
in a preferred embodiment, the signal sampling circuit comprises 6 sampling resistors connected in parallel, and the resistance of the sampling resistors is the same as or equal to the resistance of the original sampling resistors on the power supply side of the inverter circuit.
the beneficial effects of the above technical scheme are: the application scene of meeting the street lamp power supply is disclosed, and the sampling resistor is simple in configuration and easy to implement.
In a preferred embodiment, the number and value of the sampling resistors satisfy the following conditions:
The number of the sampling resistors in the signal sampling circuit is n, the resistance values are all R,
If the inverter circuit power supply side does not originally have a sampling resistor, then there are:
wherein int () is an rounding-up function; i isSMMaximum current value for power surge, I0The current corresponding to the rated power of the sampling resistor;
if the inverter circuit power supply side originally has a sampling resistor and the resistance is R, then have:
The beneficial effects of the above technical scheme are: the number of sampling resistors can be quickly determined.
In a preferred embodiment, the number and value of the sampling resistors satisfy the following conditions:
(1)(Rsense*I)＜VP(ii) a Wherein R issenseis equivalent resistance value after a plurality of sampling resistors are connected in parallel, I is working current of the inverter circuit, and VPAn input voltage protection threshold value for the monitoring chip;
(2)Pis＜Pio(ii) a Wherein, Piothe rated power of the ith sampling resistor; i is a positive integer and is less than or equal to n; the n is the number of sampling resistors in the signal sampling circuit or the sum of the number of the sampling resistors in the signal sampling circuit and the number of original sampling resistors on the power supply side of the inverter circuit; pisThe power impact current of the ith sampling resistor in the inverter circuit is ISthe power of the time-varying power, The ratio of the current obtained for the ith sampling resistor to the current of the inverter circuit, RiIs the resistance value of the ith sampling resistor.
The beneficial effects of the above technical scheme are: and a value taking condition which meets the requirement that the sampling resistor is not burnt out by power impact is given, and the selection of the number and the resistance value of the sampling resistor is guided.
In a preferred embodiment, the n sampling resistors have the same resistance value, and the n sampling resistors have the same resistance value
the beneficial effects of the above technical scheme are: the selection of resistance and implementation are facilitated.
in a preferred embodiment, the monitoring chip further comprises a low-pass circuit composed of one or more low-pass filters in cascade connection, wherein an input end of the low-pass circuit is connected with the first end of the signal sampling circuit, and an output end of the low-pass circuit is connected with the signal input end of the monitoring chip.
The beneficial effects of the above technical scheme are: the high-frequency current component when the filtering power strikes protects the signal input end of the monitoring chip from being damaged, and the plurality of low-pass circuits are cascaded to filter the high-frequency part as much as possible, so that the signal input end of the monitoring chip is protected in a hierarchical mode, and the effect is better.
In a preferred embodiment, the low-pass filter is a passive RC low-pass filter.
the beneficial effects of the above technical scheme are: the circuit is easy to build, and the cost is low.
In a preferred embodiment, the low-pass circuit includes two cascaded passive RC low-pass filters, specifically including: a fourteenth resistor, a fifteenth resistor, a sixteenth capacitor and a seventeenth capacitor;
The first end of the fourteenth resistor is connected with the first end of the signal sampling circuit, the second end of the fourteenth resistor is respectively connected with the first end of the fifteenth resistor and the first end of the sixteenth capacitor, the second end of the fifteenth resistor is respectively connected with the first end of the seventeenth capacitor and the signal input end of the monitoring chip, and the second ends of the sixteenth capacitor and the seventeenth capacitor are connected with the ground.
The beneficial effects of the above technical scheme are: a specific circuit structure of the low-pass circuit is disclosed, which is simple and easy to implement. Power surge
in order to realize the above object of the utility model, according to the utility model discloses a second aspect, the utility model provides a voltage source, including inverter circuit with power supply power surge protection detection circuit.
the beneficial effects of the above technical scheme are: the power surge detection circuit has the beneficial effect of preventing the power surge.
in a preferred embodiment, the inverter circuit includes a seventh NMOS transistor, a fourth NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a second inductor, a fourteenth capacitor, a sixth transformer, and a fifteenth capacitor;
The drain electrode of the seventh NMOS tube and the drain electrode of the fourth NMOS tube are both connected with a direct current power supply end, the grid electrode of the seventh NMOS tube is connected with the first control end of the monitoring chip, the source electrode of the seventh NMOS tube is respectively connected with the first end of the second inductor and the drain electrode of the eighth NMOS tube, the grid electrode of the eighth NMOS tube is connected with the second control end of the monitoring chip, and the source electrode of the eighth NMOS tube is connected with the first end of the signal sampling circuit;
the grid electrode of a fourth NMOS tube is connected with the third control end of the monitoring chip, the second end of a second inductor is respectively connected with the first end of a fourteenth capacitor and the first end of a first coil of a sixth transformer, the second end of the first coil of the sixth transformer is respectively connected with the first end of a fifteenth capacitor and an alternating current live wire end, the second end of the fifteenth capacitor is respectively connected with an alternating current zero wire end and the first end of a second coil of the sixth transformer, the second end of the second coil of the sixth transformer is respectively connected with the second end of the fourteenth capacitor and the drain electrode of a ninth NMOS tube, the source electrode of the ninth NMOS tube is connected with the first end of the signal sampling circuit, and the grid electrode of the ninth NMOS tube is connected with the fourth control end of the monitoring chip.
the utility model has the advantages that: the inversion from direct current to alternating current is realized by orderly opening or closing four control ends of the monitoring chip.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
the above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
Fig. 1 is a schematic circuit diagram of a preferred embodiment of the present invention;
fig. 2 is a schematic structural diagram of a switching circuit in a preferred embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.
In the description of the present invention, unless otherwise specified and limited, it is to be noted that the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, mechanically or electrically connected, or may be connected between two elements through an intermediate medium, or may be directly connected or indirectly connected, and specific meanings of the terms may be understood by those skilled in the art according to specific situations.
the utility model provides a power supply anti-power impact detection circuit, in a preferred embodiment, the circuit structure is as shown in figure 1, which comprises a signal sampling circuit arranged at the power supply side of an inverter circuit, the output end of the signal sampling circuit is connected with the signal input end of a monitoring chip;
The signal sampling circuit comprises 1 or more sampling resistors which are connected in parallel with each other,
When the number of the sampling resistors is 1, the signal sampling circuit is connected with the original sampling resistor on the power supply side of the inverter circuit in parallel;
When the sampling resistor is a plurality of, signal sampling circuit independently sets up in inverter circuit power supply side or connects in parallel with the original sampling resistor of inverter circuit power supply side.
In a preferred embodiment, a first terminal of the signal sampling circuit is connected to a ground terminal of the inverter circuit and a signal input terminal of the monitoring chip, respectively, and a second terminal of the signal sampling circuit is connected to ground.
In a preferred embodiment, as shown in fig. 2, the power supply further comprises a switching circuit, wherein the switching circuit comprises an electrically controlled switch S, a comparator U and a first reference power supply;
The first end of the signal sampling circuit is respectively connected with the grounding end of the inverter circuit, the signal input end of the monitoring chip, the positive input end of the comparator U and the first end of the original resistor R13 on the power supply side of the inverter circuit, a normally open contact of the electric control switch S is connected between the second end of the signal sampling circuit and the ground in series, and the second end of the original resistor R13 on the power supply side of the inverter circuit is connected with the ground; the negative input end of the comparator U is connected with the output end of the first reference power supply, the output end of the comparator U is connected with the input end of the trigger, and the output end of the trigger is connected with the on-off control end of the electric control switch S;
The voltage value of the output end of the first reference power supply is larger than the voltage value of the first end of the original resistor R13 on the power supply side of the inverter circuit when no power impact exists, and is smaller than the voltage value corresponding to the rated power of the original resistor R13 on the power supply side of the inverter circuit.
In this embodiment, the comparator U is preferably, but not limited to, LM324 or LM358, and the flip-flop is preferably a rising edge flip-flop, which may be a D flip-flop of 74LS 74. Can be selected according to the resistance R and rated power P of the original resistor0Based onCalculating to obtain a voltage value U corresponding to the rated power of the original resistor0The voltage value of the output end of the first reference power supply is preferably U00.5-0.9 times of the total weight of the composition. Preferably, the reference voltage chip and its peripheral circuit provided by companies such as TI or ADI can be selected to construct the circuit of the first reference power supply, and the specific circuit structure can refer to the technical manual of the selected chip.
in a preferred embodiment, the signal sampling circuit comprises 6 sampling resistors connected in parallel, and the resistance values of the sampling resistors are the same or the same as the resistance values of the original sampling resistors on the power supply side of the inverter circuit, for example, the resistors with 50 milli-ohms and the power capacity of 2 watts are selected. The total power impact is ensured to exceed the single resistance power impact capacity by 6 times and can work normally.
in a more preferred embodiment, the number and value of the sampling resistors satisfy the following condition:
the number of the sampling resistors in the signal sampling circuit is n, the resistance values are all R,
If the inverter circuit power supply side does not originally have a sampling resistor, then there are:
Wherein int () is an rounding-up function; i isSMIs the maximum current value of the power surge,
can be obtained by multiple measurements, I0The current corresponding to the rated power of the sampling resistor;
If the inverter circuit power supply side originally has a sampling resistor and the resistance is R, then have:
In a preferred embodiment, to avoid the sampling resistor being burned out due to power impact, the resistance value of the sampling resistor should be:
(1)(Rsense*I)＜VP(ii) a Wherein R issenseIs the equivalent resistance value after a plurality of sampling resistors are connected in parallel, I is the inverseOperating current, V, of the converter circuitPan input voltage protection threshold value for the monitoring chip;
(2)Pis＜Pio(ii) a Wherein, PioThe rated power of the ith sampling resistor is shown, i is a positive integer and is less than or equal to n, and n is the number of the sampling resistors; pisThe power impact current of the ith sampling resistor in the inverter circuit is ISthe power of the time-varying power, The proportional coefficient of the current obtained for the ith sampling resistor and the current of the inverter circuit can be obtained by a resistor parallel shunt principle well known to those skilled in the art; riis the resistance value of the ith sampling resistor. In the present embodiment, the sampling resistor is preferably a high-precision resistor of the order of m Ω, for example, 100m Ω.
In this embodiment, as shown in fig. 1, when n is 5, the 5 sampling resistors include a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13.
In this embodiment, n is calculated as prior art, as disclosed in the website https:// wenku.baidu.com/view/3 b62116b651e79b8968022646.html.
In a preferred embodiment, the n sampling resistors have the same resistance value, and at this time,The current divided by each sampling resistor is the same asOr
In an application scenario, when the resistance values of the n sampling resistors are the same and are in phase with the resistance value of the signal sampling circuit formed by the single sampling resistorsimilarly, if R is set, and the signal sampling circuit formed by a single sampling resistor satisfies the condition (1), then the equivalent resistance of the signal sampling circuit in the application scenario isThe condition (1) is necessarily satisfied. In the signal sampling circuit composed of single sampling resistor, the power obtained by the sampling resistor is I when the power is impactedS 2R; in the signal sampling circuit of the application scene, the power obtained by a single sampling resistor during power impact isIs IS 2of RAnd (4) doubling.
In a preferred embodiment, the monitoring chip further comprises a low-pass circuit composed of one or more low-pass filters in cascade connection, wherein an input end of the low-pass circuit is connected with the first end of the signal sampling circuit, and an output end of the low-pass circuit is connected with the signal input end of the monitoring chip.
In this embodiment, it is preferable that the cut-off frequency of the low-pass filter should be lower than the KHz level to avoid the high-frequency component of the power surge from damaging the signal input pin of the monitoring chip. The low-pass filter can be selected from an integrated filter chip or a low-pass filter circuit built by elements such as a resistor, a capacitor and the like.
in a preferred embodiment, the low-pass filter is a passive RC low-pass filter.
In a preferred embodiment, as shown in fig. 1, the low-pass circuit includes two cascaded passive RC low-pass filters, specifically including: a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth capacitor C16 and a seventeenth capacitor C17;
the first end of the fourteenth resistor R14 is connected with the first end of the signal sampling circuit, the second end of the fourteenth resistor R14 is respectively connected with the first end of the fifteenth resistor R15 and the first end of the sixteenth capacitor C16, the second end of the fifteenth resistor R15 is respectively connected with the first end of the seventeenth capacitor C17 and the signal input end of the monitoring chip, and the second end of the sixteenth capacitor C16 and the second end of the seventeenth capacitor C17 are connected with the ground.
In this embodiment, the fourteenth resistor R14 and the sixteenth capacitor C16 form a first-stage passive RC low-pass filter, and the fifteenth resistor R15 and the seventeenth capacitor C17 form a second-stage passive RC low-pass filter.
In a preferred embodiment, the anti-power surge device is connected in parallel at two ends thereof, a first end of the anti-power surge device is connected with a first end of the signal sampling circuit, a second end of the anti-power surge device is connected with the ground, and the anti-power surge device is preferably, but not limited to, one or more piezoresistors connected in parallel with each other and/or one or more TVS tubes connected in parallel with each other. Preferably, the connecting wires at the two ends of the power surge resistant device are thicker than other wires, and the connecting wire with the ground end is as short as possible, so that power surge current can be discharged quickly, and other devices can be protected.
the utility model also provides a voltage source, this power include inverter circuit with the power prevent power impact detection circuit.
In a preferred embodiment, as shown in fig. 1, the inverter circuit includes a seventh NMOS transistor Q7, a fourth NMOS transistor Q4, an eighth NMOS transistor Q8, a ninth NMOS transistor Q9, a second inductor L2, a fourteenth capacitor C14, a sixth transformer T6, and a fifteenth capacitor C15;
A drain electrode of a seventh NMOS transistor Q7 and a drain electrode of a fourth NMOS transistor Q4 are both connected with a direct current power supply end, a grid electrode of the seventh NMOS transistor Q7 is connected with a first control end of the monitoring chip, a source electrode of the seventh NMOS transistor Q7 is respectively connected with a first end of a second inductor L2 and a drain electrode of an eighth NMOS transistor Q8, a grid electrode of an eighth NMOS transistor Q8 is connected with a second control end of the monitoring chip, and a source electrode of the eighth NMOS transistor Q8 is connected with a first end of the signal sampling circuit;
A grid electrode of a fourth NMOS tube Q4 is connected to the third control end of the monitoring chip, a second end of a second inductor L2 is connected to a first end of a fourteenth capacitor C14 and a first end of a first coil of a sixth transformer T6, a second end of the first coil of the sixth transformer T6 is connected to a first end of a fifteenth capacitor C15 and an alternating current live wire end, a second end of a fifteenth capacitor C15 is connected to an alternating current live wire end and a first end of a second coil of the sixth transformer T6, a second end of the second coil of the sixth transformer T6 is connected to a second end of a fourteenth capacitor C14 and a drain electrode of a ninth NMOS tube Q9, a source electrode of the ninth NMOS tube Q9 is connected to the first end of the signal sampling circuit, and a grid electrode of the ninth NMOS tube Q9 is connected to the fourth control end of the monitoring chip.
In the present embodiment, the second inductor L2 is preferably, but not limited to, a tape core inductor, and the sixth transformer T6 is preferably, but not limited to, an air core transformer.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims (7)
1. a power supply anti-power impact detection circuit is characterized by comprising a signal sampling circuit arranged on the power supply side of an inverter circuit, wherein the output end of the signal sampling circuit is connected with the signal input end of a monitoring chip;
The signal sampling circuit comprises 1 or more sampling resistors which are connected in parallel with each other,
when the number of the sampling resistors is 1, the signal sampling circuit is connected with the original sampling resistor on the power supply side of the inverter circuit in parallel;
When the sampling resistor is a plurality of, signal sampling circuit independently sets up in inverter circuit power supply side or connects in parallel with the original sampling resistor of inverter circuit power supply side.
2. the power supply power surge detection circuit according to claim 1, wherein a first terminal of the signal sampling circuit is connected to a ground terminal of the inverter circuit and a signal input terminal of the monitoring chip, respectively, and a second terminal of the signal sampling circuit is connected to ground;
Or the switching circuit comprises an electric control switch, a comparator, a first reference power supply and a trigger;
The first end of the signal sampling circuit is respectively connected with the grounding end of the inverter circuit, the signal input end of the monitoring chip, the positive input end of the comparator and the first end of the original resistor on the power supply side of the inverter circuit, a normally open contact of the electric control switch is connected between the second end of the signal sampling circuit and the ground in series, and the second end of the original resistor on the power supply side of the inverter circuit is connected with the ground; the negative input end of the comparator is connected with the output end of the first reference power supply, the output end of the comparator is connected with the input end of the trigger, and the output end of the trigger is connected with the on-off control end of the electric control switch;
The voltage value of the output end of the first reference power supply is larger than the voltage value of the first end of the original resistor on the power supply side of the inverter circuit when no power impact exists, and is smaller than the voltage value corresponding to the rated power of the original resistor on the power supply side of the inverter circuit.
3. The power supply power surge detection circuit as claimed in claim 1, wherein said signal sampling circuit comprises 6 sampling resistors connected in parallel, and the resistance of the sampling resistors is the same as or the same as the original sampling resistor on the power supply side of the inverter circuit.
4. the power supply power surge-prevention detection circuit as claimed in claim 1, further comprising a low pass circuit composed of one or more cascaded low pass filters, wherein an input terminal of the low pass circuit is connected to the first terminal of the signal sampling circuit, and an output terminal of the low pass circuit is connected to the signal input terminal of the monitoring chip.
5. The power supply power surge detection circuit of claim 4, wherein said low pass filter is a passive RC low pass filter.
6. the power supply power surge detection circuit of claim 5, wherein said low pass circuit comprises two cascaded passive RC low pass filters, in particular comprising: a fourteenth resistor, a fifteenth resistor, a sixteenth capacitor and a seventeenth capacitor;
The first end of the fourteenth resistor is connected with the first end of the signal sampling circuit, the second end of the fourteenth resistor is respectively connected with the first end of the fifteenth resistor and the first end of the sixteenth capacitor, the second end of the fifteenth resistor is respectively connected with the first end of the seventeenth capacitor and the signal input end of the monitoring chip, and the second ends of the sixteenth capacitor and the seventeenth capacitor are both connected with the ground.
7. A voltage source comprising an inverter circuit and the power supply power surge detection circuit of any of claims 1-6;
The inverter circuit comprises a seventh NMOS tube, a fourth NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a second inductor, a fourteenth capacitor, a sixth transformer and a fifteenth capacitor;
The drain electrode of the seventh NMOS tube and the drain electrode of the fourth NMOS tube are both connected with a direct current power supply end, the grid electrode of the seventh NMOS tube is connected with the first control end of the monitoring chip, the source electrode of the seventh NMOS tube is respectively connected with the first end of the second inductor and the drain electrode of the eighth NMOS tube, the grid electrode of the eighth NMOS tube is connected with the second control end of the monitoring chip, and the source electrode of the eighth NMOS tube is connected with the first end of the signal sampling circuit;
The grid electrode of a fourth NMOS tube is connected with the third control end of the monitoring chip, the second end of a second inductor is respectively connected with the first end of a fourteenth capacitor and the first end of a first coil of a sixth transformer, the second end of the first coil of the sixth transformer is respectively connected with the first end of a fifteenth capacitor and an alternating current live wire end, the second end of the fifteenth capacitor is respectively connected with an alternating current zero wire end and the first end of a second coil of the sixth transformer, the second end of the second coil of the sixth transformer is respectively connected with the second end of the fourteenth capacitor and the drain electrode of a ninth NMOS tube, the source electrode of the ninth NMOS tube is connected with the first end of the signal sampling circuit, and the grid electrode of the ninth NMOS tube is connected with the fourth control end of the monitoring chip.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920559275.7U CN209787040U (en) | 2019-04-23 | 2019-04-23 | power impact detection circuitry is prevented to power and have this detection circuitry's power |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920559275.7U CN209787040U (en) | 2019-04-23 | 2019-04-23 | power impact detection circuitry is prevented to power and have this detection circuitry's power |
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| CN209787040U true CN209787040U (en) | 2019-12-13 |
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| CN201920559275.7U Active CN209787040U (en) | 2019-04-23 | 2019-04-23 | power impact detection circuitry is prevented to power and have this detection circuitry's power |
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| CN (1) | CN209787040U (en) |
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2019
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