CN209710099U - A kind of channel calibrating installation - Google Patents
A kind of channel calibrating installation Download PDFInfo
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Abstract
This application provides a kind of channel calibrating installation and methods, computer installation and readable storage medium storing program for executing, described device includes: FPGA device and the DSP device connecting with FPGA device, FPGA device includes adopting digital-to-analogue block and calibration filter, it adopts digital-to-analogue block and acquires and send the calibrating sequence in channel to be calibrated and the calibrating sequence of reference channel；DSP device is used to receive the calibrating sequence of the calibrating sequence and reference channel of adopting the channel to be calibrated of digital-to-analogue block transmission；Using the frequency domain response between the calibrating sequence in channel to be calibrated and the calibrating sequence of reference channel, the calibration filter coefficient in channel to be calibrated is calculated；Using the autocorrelation of the calibrating sequence in channel to be calibrated, first time delay value in channel to be calibrated is obtained, using the autocorrelation of the calibrating sequence of reference channel, obtains the second time delay value of reference channel；Obtain the delay inequality between channel to be calibrated and reference channel；Delay inequality and calibration filter coefficient are sent to calibration filter.
Description
Technical field
The utility model relates to wireless communication technology field more particularly to a kind of channel calibrating installations.
Background technique
Intelligent multi-antenna technology due to its have many advantages, such as improve cell coverage area, inhibit signal interference, when
Divide S-CDMA-Synchronous Code Division Multiple Access (Time Division Synchronized Code Division Multiple Acess, TD-
SCDMA), in the mobile communication system such as time-division long term evolution (TD-SCDMA Long Term Evolution, TD-LTE) extensively
It uses.
However intelligent multi-antenna technology is in practical applications, radio frequency send and receive circuit device and its composition it is active
Circuit is inevitably present the difference of amplitude and phase, so that generating amplitude and phase not between transmission channel and receiving channel
Unanimously, and since time, temperature, the change of environment and the aging of device also can cause each channel amplitude and phase characteristic different
It causes.
Since the difference (including phase or amplitude inconsistent) of interchannel causes existing intelligent multiple antennas service performance low.
Utility model content
The utility model embodiment provides a kind of channel calibrating installation, for solving existing intelligent multiple antennas service performance
Low technical problem.
The utility model embodiment provides a kind of channel calibrating installation, is applied to multi-channel radio remote unit RRU, institute
Stating multichannel includes channel to be calibrated and reference channel, comprising: on-site programmable gate array FPGA device and with the FPGA device
The Digital Signal Processing DSP device of part connection, in which:
The FPGA device includes adopting digital-to-analogue block and calibration filter, it is described adopt digital-to-analogue block for collecting and sending it is described to
The calibrating sequence of the calibrating sequence of calibrated channel and the reference channel；
The DSP device, for receiving the calibrating sequence in the channel to be calibrated for adopting the transmission of digital-to-analogue block, Yi Jisuo
State the calibrating sequence of reference channel；Using between the calibrating sequence in the channel to be calibrated and the calibrating sequence of the reference channel
Frequency domain response calculates the calibration filter coefficient in the channel to be calibrated；Using the channel to be calibrated calibrating sequence from
Correlation obtains first time delay value in the channel to be calibrated, and, utilize the auto-correlation of the calibrating sequence of the reference channel
Property, obtain the second time delay value of the reference channel；Based on first time delay value and second time delay value, obtain it is described to
Delay inequality between calibrated channel and the reference channel；The delay inequality and the calibration filter coefficient are sent to the school
Quasi- filter, the delay inequality and the calibration filter coefficient are for characterizing the calibration filter；
Wherein, the calibration filter is used for according to the calibration filter coefficient and the delay inequality to described to be calibrated
It is calibrated in channel.
It in the utility model embodiment, is acted synergistically by FPGA device and DSP device, determines characterization calibration filter
The delay inequality and calibration filter coefficient of wave device, treat calibrated channel by calibration filter and compensate, to improve intelligence
The service performance of energy multiple antennas.
Optionally, the calibration filter is specially the variable filter of order, at the first time, passes through the characterization school
The first delay inequality and first filter coefficient of quasi- filter calibrate the first channel to be calibrated；With the first time
It is the second different time, to be calibrated to second by the second delay inequality and second filter coefficient that characterize the calibration filter
It is calibrated in channel, wherein the order of the calibration filter is R when the first time, described in when second time
It is positive integer that the order for calibrating filter, which is S, R and S,.
Optionally, the DSP device is specifically used for:
Frequency-domain transform is carried out to the calibrating sequence in the channel to be calibrated and obtains the first numerical value, and to the reference channel
Calibrating sequence carry out frequency-domain transform obtain second value；
Determine the ratio between the second value and first numerical value, wherein the ratio is the channel to be calibrated
With the frequency domain response between the reference channel；
Fourier inversion is carried out to the frequency domain response and obtains the school between the channel to be calibrated and the reference channel
Quasi-divisor；
Determine that the calibration factor corresponds to M maximum impact response point, wherein M maximum impact response point is specially institute
Calibration filter coefficient is stated, M is positive integer.
Optionally, the DSP device is specifically used for:
Obtain local sequence；
It is related that the calibrating sequence in the channel to be calibrated and the local sequence are subjected to conjugation, determination be conjugated it is relevant most
First location information where high peak value point, and, the calibrating sequence of the reference channel and the local sequence are carried out
Conjugation is related, determines the second location information being conjugated where relevant highest peak value point；
First time delay value in the channel to be calibrated is obtained based on the first location information, and, based on described
Second location information obtains second time delay value of the reference channel.
Optionally, the DSP device is specifically used for filtering the delay inequality and the calibration according to preset data packet format
Wave device coefficient is sent to the calibration filter, wherein the preset data packet format includes short packet verification and verifies with long packet
With；
The calibration filter is according to the short packet verification and wraps verification with the length and verifies what the DSP device was sent
The calibration filter coefficient and the delay inequality, it is whether consistent with the data after being received via the calibration filter, wherein
The short packet verifies and including the calibration filter coefficient and the delay inequality, the long packet verification and including removing packet header, wrapping
The sum of all data except tail.
Optionally, the calibration filter is specially to have limit for length's unit impulse response FIR filter.
Optionally, the digital-to-analogue block of adopting is used for:
The calibrating sequence of respective channel is sent by the GP time slot of the radio frequency transmitting terminal in any channel.
Optionally, the FPGA device is connected with the DSP device by external memory interface EMIF.
Detailed description of the invention
A kind of exemplary block diagram for the eight channel RRU loops that Fig. 1 is applicable in by the utility model embodiment；
Fig. 2 is a kind of structural schematic diagram of channel calibrating installation provided by the embodiment of the utility model；
Fig. 3 is that a kind of channel calibrating installation alignment provided by the embodiment of the utility model sends out number position view；
Fig. 4 is that uplink calibrates schematic diagram in a kind of channel calibrating installation provided by the embodiment of the utility model；
Fig. 5 is that downlink calibrates schematic diagram in a kind of channel calibrating installation provided by the embodiment of the utility model；
Fig. 6 is 8 rank filter schematics in a kind of channel calibrating installation provided by the embodiment of the utility model；
Fig. 7 is a kind of data packet format signal used in a kind of channel calibrating installation provided by the embodiment of the utility model
Figure；
Fig. 8 is that the transversality structure of FIR filter in a kind of channel calibrating installation provided by the embodiment of the utility model is shown
It is intended to.
Specific embodiment
" first ", " second " in the specification and claims of the utility model and above-mentioned attached drawing etc. are for distinguishing
Different objects, are not use to describe a particular order.In addition, term " includes " and their any deformation, it is intended that cover
It covers and non-exclusive includes.Such as it contains the process, method, system, product or equipment of a series of steps or units and does not limit
In listed step or unit, but optionally further comprising the step of not listing or unit, or optionally further comprising for
The intrinsic other step or units of these process, methods, product or equipment.
Referenced herein " embodiment " is it is meant that a particular feature, structure, or characteristic described can wrap in conjunction with the embodiments
It is contained at least one embodiment of the utility model., which there is the phrase, in each position in the description to be each meant
Identical embodiment, nor the independent or alternative embodiment with other embodiments mutual exclusion.Those skilled in the art are explicit
Ground and implicitly understand, embodiment described herein can be combined with other embodiments.
In order to better understand the above technical scheme, below by attached drawing and specific embodiment to the utility model technology
Scheme is described in detail, it should be understood that the specific features in the utility model embodiment and embodiment are to the utility model
The detailed description of technical solution, rather than the restriction to technical solutions of the utility model, in the absence of conflict, this is practical
Technical characteristic in new embodiment and embodiment can be combined with each other.
Fig. 1 show eight channel radio frequency extension unit RRU (the Radio Remote that the utility model embodiment is applicable in
Unit a kind of) exemplary block diagram of loop.Wherein, the radio-frequency receiving-transmitting end of RX/TX expression RRU, shared RX1/TX1, RX2/TX2,
The eight radio-frequency receiving-transmitting ends RX3/TX3, RX4/TX4, RX5/TX5, RX6/TX6, RX7/TX7, RX8/TX8, RX correspond to radio frequency reception
End, TX correspond to radio-frequency transmissions end, have eight transceiver channels in the RRU loop in eight channel, be at least arranged on each transceiver channel
One such as low-noise amplifier (Low Noise Amplifier, i.e. LNA) or power amplifier (Power Amplifier,
That is PA) power amplifier module, wherein low-noise amplifier can be used for amplifying uplink signal, and power amplifier can be used for pair
Downlink signal amplifies.Signal is sent it into coupler through the power amplifier module in corresponding channel through each transceiver channel,
Coupler can be sent to corresponding radio frequency reception end through same calibrated channel to the signal that multichannel sends over.
In the specific implementation process, in order to which the difference for eliminating interchannel passes through school in each channel addition calibration filter
Quasi- filter compensates channel.
Referring to FIG. 2, being a kind of channel calibrating installation provided by the embodiment of the utility model, it is applied to multi-channel radio frequency and draws
Remote unit R RU, comprising:
On-site programmable gate array FPGA (Field-Programmable Gate Array) device 10 and and FPGA device
Digital Signal Processing DSP (Digital Signal Processing) device 20 of 10 connections；In the specific implementation process,
FPGA device 10 is connected with DSP device 20 by external memory interface EMIF (External Memory Interface).
FPGA device 10 includes adopting digital-to-analogue block 101 and calibration filter 102, adopts the institute for collecting and sending of digital-to-analogue block 101
State the calibrating sequence in channel to be calibrated and the calibrating sequence of the reference channel；
DSP device 20 adopts the calibrating sequence in the channel to be calibrated of the transmission of digital-to-analogue block 101 and described for receiving
The calibrating sequence of reference channel；Utilize the frequency between the calibrating sequence in the channel to be calibrated and the calibrating sequence of the reference channel
Domain response calculates the calibration filter coefficient in the channel to be calibrated；Using the channel to be calibrated calibrating sequence from phase
Guan Xing obtains first time delay value in the channel to be calibrated, and, utilize the auto-correlation of the calibrating sequence of the reference channel
Property, obtain the second time delay value of the reference channel；Based on first time delay value and second time delay value, obtain it is described to
Delay inequality between calibrated channel and the reference channel；The delay inequality and the calibration filter coefficient are sent to calibration filter
Wave device 102, the delay inequality and the calibration filter coefficient are for characterizing calibration filter 102；
Wherein, calibration filter 102 is used for according to the calibration filter coefficient and the delay inequality to described to be calibrated
It is calibrated in channel.It is described to be calibrated logical according to the calibration filter coefficient and delay inequality adjustment to calibrate filter 102
Amplitude, phase and delay inequality between road and reference channel.
In the utility model embodiment, in order to determine whether channel to be calibrated needs to be compensated by calibration filter,
It needs to be determined that whether the amplitude difference between channel to be calibrated and reference channel and phase difference meet index out, such as, it is thus necessary to determine that two
Whether the amplitude difference of interchannel is within the scope of predetermined amplitude difference, and whether the phase difference of two interchannels is within the scope of preset phase difference.
In the specific implementation process, if the frequency domain response of reference channel is Href, the frequency domain response in channel to be calibrated is Hi, then to be calibrated
Amplitude difference between channel and reference channel are as follows: 20*log10 (Href/Hi), the phase difference between channel to be calibrated and reference channel are as follows:
arctan((Href/Hi)), it, can be true after determining the amplitude difference and phase difference between channel to be calibrated and reference channel
It is fixed whether to need to compensate corresponding channel to be calibrated.
In the utility model embodiment, the calibrating sequence in channel to be calibrated, and reference are acquired by adopting digital-to-analogue block 101
The calibrating sequence in channel.The calibrating sequence in the channel to be calibrated then acquired and the calibrating sequence of reference channel are sent
To DSP device 20.The reference channel is any one channel chosen from multichannel.
Wherein, calibrating sequence is specially ZC (Zadoff-Chu) sequence, and by taking eight channel RRU as an example, the calibrating sequence is long
Degree is N, and the calibrating sequence of each channel reception is xi, i ∈ [1,8], wherein subscript i indicates i-th of channel.
ZC sequence meets CAZAC perseverance amplitude autocorrelation performance, and CAZAC sequence is that form isComplex valued signals.Length is
The N of odd numberzcZC sequence can indicate are as follows:
Wherein, q ∈ { 1 ..., Nzc- 1 } be ZC sequence radical exponent, n=0,1 ..., Nzc- 1, l ∈ N, l can be any
Integer.L=0 is usually set in LTE.
In the utility model embodiment, which receives the calibrating sequence and reference channel in channel to be calibrated
Calibrating sequence.Then, it using the frequency domain response between the calibrating sequence in channel to be calibrated and the calibrating sequence of reference channel, calculates
The calibration filter coefficient in channel to be calibrated.
In the specific implementation process, when calibrating sequence is specially ZC sequence, its characteristic is utilized: the ZC sequence of any length
With ideal circulation autocorrelation, zero auto-correlation can be formulated are as follows:
Wherein, rkk() is that time delay is σ about akThe period autocorrelation of discrete periodic auto-correlation function, ZC sequence only has
There is peak value in zero point, ZC sequence identical for two symbol lengths, as σ ≠ 0, period autocorrelation is zero；σ=0
When, period auto-correlation will appear peak value.In the utility model embodiment, using this characteristic of ZC sequence, one is used
The identical local ZC sequence of section symbol lengths, carries out time-delay calibration.By taking eight channel RRU as an example, calibrating sequence xi, i ∈ [1,8] points
Position not related to the progress of local sequence z (n), where relevant peak value point, the as time delay value of current channel.
In the utility model embodiment, using the autocorrelation of the calibrating sequence in channel to be calibrated, obtain to be calibrated logical
First time delay value in road.Using the autocorrelation of the calibrating sequence of reference channel, the second time delay value of reference channel is obtained.So
Afterwards, the second time delay value of the first time delay value based on channel to be calibrated and reference channel, can determine the channel to be calibrated with
Delay inequality between the reference channel.Then, the delay inequality and calibration filter coefficient are sent to calibration filter 102.In this way
If, determine that out the calibration filter 102 characterized by the delay inequality and calibration filter coefficient, the calibration filter 102
The channel to be calibrated can be calibrated according to the calibration filter coefficient and delay inequality.
It in the utility model embodiment, is acted synergistically by FPGA device and DSP device, determines characterization calibration filter
The delay inequality and calibration filter coefficient of wave device, treat calibrated channel by calibration filter and compensate, to improve intelligence
The service performance of energy multiple antennas.
In the utility model embodiment, in order to realize that the transmission for adopting digital-to-analogue block 101 to calibrating sequence is specifically adopted
Digital-to-analogue block 101 sends the calibrating sequence of respective channel by the GP time slot of the radio frequency transmitting terminal in any channel, and specific numerical digit of sending out is set
As shown in Figure 3.3GPP(The 3rdGeneration Partnership Project) agreement regulation, LTE is using OFDM
(Orthogonal Frequency Division Multiplexing, orthogonal frequency division multiplexing) technology, subcarrier spacing are Δ f
=15kHz, each subcarrier are that 2048 rank IFFT (Inverse Fast Fourier Transform, inverse Fourier transform) is adopted
Sample, then LTE sampling period Ts=1/ (2048x15000)=0.033us, therefore, the minimum unit that the LTE frame structure time describes
It is exactly sampling period Ts.In TDD (Time Division Duplexing, time division duplex) system, LTE radio frames are a length of
10ms, every frame are made of 10 1ms subframes (Subframe#0~Subframe#9), each subframe include two 0.5ms when
Gap.Wherein, first subframe of every frame is used as descending time slot fixedly to send broadcast message, and second subframe is fixedly used as
Special time slot, special time slot are made of DwPTS, GP and UpPTS, and total length 1ms, third subframe is fixedly used as
Row time slot；Agreement provides that different uplink and downlink time slot proportions can be configured.In addition, the length of special time slot DwPTS, GP, UpPTS
Degree is also that can configure.
In the specific implementation process, transmission process of the calibrating sequence in uplink and downlink calibration process is different.It is illustrated in figure 4
Uplink calibrates schematic diagram, and specifically, GP time slot of the uplink calibration in the TX1 of radio-frequency transmissions end sends calibrating sequence, in uplink
Radio frequency reception end RX1~RX8 receives calibrating sequence；It can also be and send calibrating sequence in radio-frequency transmissions end TX2, in upstream radio-frequency
Receiving end RX1~RX8 receives calibrating sequence.It is, of course, also possible to be other TX3 in addition to radio-frequency transmissions end TX1 and TX2~
Any one radio-frequency transmissions end in TX8 sends the calibrating sequence.Certainly, those skilled in the art can come according to actual needs
The radio-frequency transmissions end and radio frequency reception end for selecting uplink calibration, just no longer have been illustrated one by one herein.
It is illustrated in figure 5 downlink calibration schematic diagram, specifically, downlink calibrates the GP in the TX1~TX8 of radio-frequency transmissions end
Time slot sends calibrating sequence simultaneously, and in upstream radio-frequency receiving end, RX1 receives calibrating sequence respectively.It can also be and connect by upstream radio-frequency
Receiving end RX2 is received respectively.It is, of course, also possible to be by radio frequency reception end RX3~RX8 in addition to upstream radio-frequency receiving end RX1 and RX2
In any one radio frequency reception end receive, just no longer have been illustrated one by one herein.
In addition, to those skilled in the art, it can also be according to actual needs to other letters in addition to calibrating sequence
Number transmission process controlled, for example, the LTE signal through the channel to be calibrated, and another LTE through the reference channel
Signal can be transmitted to the radio frequency reception end after the coupler by same calibrated channel.It is, of course, also possible to be other
Signal, just do not repeat one by one herein.
In the utility model embodiment, the amplitude-phase and delay inequality of each interchannel are changed over time, in order to
Improve the service performance of intelligent multiple antennas, FPGA device 10 can according to calibration filter coefficient that DSP device 20 issues and when
Prolong difference, adaptively changing calibrates the order of filter, that is to say, that the calibration filter is specially the variable filter of order.
In the specific implementation process, corresponding delay inequality and filter coefficient are received in different moments calibration filter.Specifically, In
At the first time, the calibration filter for being R by the order that the first delay inequality and first filter coefficient characterize is to be calibrated to first
It is calibrated in channel；In second time different from first time, pass through the rank of the second delay inequality and the second filter factor characterization
Number is that the calibration filter of S calibrates the second channel to be calibrated, and R and S are positive integer.
For example, calibration filter aa when treating calibrated channel A progress channel calibration at the first time, DSP device is handed down to
The calibration filter coefficient of FPGA device isDelay inequality is that Delay0 is 1, Delay1 1, Delay2 1, Delay3
For 1, Delay4 1, Delay5 1, Delay6 1, with z-nTime delay unit is represented as n, time delay unit is corresponding for characterizing
Delay inequality.At this point, the mathematic(al) representation of the calibration filter aa characterized by calibration filter coefficient and delay inequality are as follows:
At this point, calibration filter aa is specially the filter of 8 ranks, at this point, the 8 rank filter schematic is as shown in Figure 6.
For another example, when the second time treating calibrated channel A progress channel calibration, DSP device issues calibration filter aa
Calibration filter coefficient to FPGA device isIt is 1, Delay1 2, Delay2 3 that delay inequality, which is Delay0,
Delay3 is 4, Delay4 5, Delay5 6, Delay6 7, then calibration filter mathematic(al) representation at this time are as follows:
At this point, calibration filter aa is the filter of 29 ranks.
For another example, when the third time treating calibrated channel A progress channel calibration, DSP device issues calibration filter aa
To the calibration filter coefficient of FPGA device are as follows:Time delay D elay0 be 16, Delay1 16, Delay2 16,
Delay3 is 16, Delay4 16, Delay5 16, Delay6 16, then calibration filter mathematic(al) representation at this time are as follows:
At this point, calibration filter aa is the filter of 113 ranks.
In the utility model embodiment, in order to determine that calibration filter coefficient, DSP device 20 treat calibrated channel
Calibrating sequence carries out frequency-domain transform and obtains the first numerical value, and carries out frequency-domain transform to the calibrating sequence of reference channel and obtain the second number
Value；Then, it is determined that the ratio between the first numerical value and second value, which is the frequency domain between channel to be calibrated and reference channel
Response.Then, Fourier inversion is carried out to frequency domain response and obtains the calibration factor between channel to be calibrated and reference channel；So
Afterwards, the corresponding M maximum impact response point of the calibration factor is determined, which is specially to calibrate filter
Coefficient, M are positive integer.
By taking the RRU in eight channels as an example, specifically, N point DFT (Discrete is carried out to the calibrating sequence of channel i
Fourier Transform, discrete Fourier transform), it obtains:
Any channel is chosen as reference channel, the second value after the frequency-domain transform of reference channel is Xref, to be calibrated logical
The first numerical value after the frequency-domain transform in road is expressed as Xi。
Then, it is determined that the ratio between second value and the first numerical value, which is between channel i and reference channel to be calibrated
Frequency domain response H:
The frequency domain response H between calibrated channel i and reference channel is treated, Fourier inversion is carried out and obtains channel i to be calibrated
The calibration factor ht between reference channeli:
Having A maximum impact response point in ht (n) the first half RB sampled point is respectively [h (0), h (1) ... h (A-1)]；Afterwards
Having B maximum impact response point in half BR sampled point is respectively [h (N-B+1), h (N-B+2) ..., h (N)], A+B=M；[h
(N-B+1), h (N-B+2) ..., h (N), h (0), h (1) ..., h (A-1)] it is calibration filter coefficient.
In the utility model embodiment, in order to realize the delay compensation in channel, which is used for:
Obtain local sequence；
It is related that the calibrating sequence in the channel to be calibrated and the local sequence are subjected to conjugation, determination be conjugated it is relevant most
First location information where high peak value point, and, the calibrating sequence of the reference channel and the local sequence are carried out
Conjugation is related, determines the second location information being conjugated where relevant highest peak value point；
First time delay value in the channel to be calibrated is obtained based on the first location information, and, based on described
Second location information obtains second time delay value of the reference channel.
In the specific implementation process, by taking eight channel RRU as an example, one section and calibrating sequence x are choseniThe identical sequence of symbol lengths
Column are used as local sequence z (n).
Calibrating sequence xi, it is related that i ∈ [1,8] carries out conjugation to local sequence z (n) respectively:
Seek the location information where relevant peak value point:
(Ti, value) and=max (Rzx)
Based on the location information, the time delay value in channel to be calibrated is obtained.TiAs current i time delay value in channel to be calibrated,
Process is realized based on same, determines that the time delay value of the reference channel is Tref.Then, it is just capable of determining that be calibrated logical
Delay inequality between road and reference channel.
In the specific implementation process, DSP device 20 will be calibrated after calculating calibration filter coefficient and delay inequality
Filter coefficient and delay inequality are issued to FPGA device 10, and the width phase and time delay for treating calibrated channel with this compensate.
In the utility model embodiment, in order to guarantee the reliability of data transmission, DSP device 20 is according to preset data packet
Data packet including calibration filter coefficient and delay inequality is sent to calibration filter by format, the preset data packet format packet
Include the verification of short packet and with long packet verification and.It so-called verification and the data issued for sender and is received with recipient
Data with it is whether consistent.Wherein, short packet verifies and including calibration filter coefficient and delay inequality, long packet verification and including removing packet
The sum of all data except head, packet tail.Then, it is sent according to short packet verification and with long packet verification and verification DSP device 20
Filter coefficient and delay inequality are calibrated, it is whether consistent with the data after being received via calibration filter 102.It is illustrated in figure 7 this
One of data packet format schematic diagram that utility model embodiment uses.The data packet format includes packet header, algorithm types, leads to
Taoist monastic name or carrier number, reserve bytes, calibration filter coefficient and delay inequality, the verification of short packet and long packet verification and packet tail.
In the utility model embodiment, in order to improve channel calibration accuracy, calibration filter 102 is specially to have limit for length single
Position impulse response FIR filter.If the unit impulse response h (n) of FIR filter be a N point sequence, 0≤n≤N-1, then
The system function of FIR filter are as follows:
The FIR filter system function has (N-1) rank pole at z=0, has (N-1) a zero point to be located at limited z-plane
Any position.The difierence equation known to the system function of FIR filter are as follows:
The formula is the transverse structure of the convolution sum formula of linear time invariant system and the time delay chain of x (n), such as Fig. 8 institute
It is shown as the transversal type or Convolution-type structure of FIR filter, also referred to as Direct-type structure, wherein N is filter order, CN-1For filtering
Coefficient, z-1Representing time delay unit is 1.
Obviously, those skilled in the art can carry out various modification and variations without departing from the essence of the application to the application
Mind and range.In this way, if these modifications and variations of the application belong to the range of the claim of this application and its equivalent technologies
Within, then the application is also intended to include these modifications and variations.
Claims (8)
1. a kind of channel calibrating installation, be applied to multi-channel radio remote unit RRU, the multichannel include channel to be calibrated and
Reference channel characterized by comprising on-site programmable gate array FPGA device and the number letter being connect with the FPGA device
Number processing DSP device, in which:
The FPGA device includes adopting digital-to-analogue block and calibration filter, and described to adopt digital-to-analogue block described to be calibrated for collecting and sending
The calibrating sequence of the calibrating sequence in channel and the reference channel；
The DSP device, for receiving the calibrating sequence for adopting the channel to be calibrated that digital-to-analogue block is sent and the ginseng
Examine the calibrating sequence in channel；Utilize the frequency domain between the calibrating sequence in the channel to be calibrated and the calibrating sequence of the reference channel
Response calculates the calibration filter coefficient in the channel to be calibrated；Utilize the auto-correlation of the calibrating sequence in the channel to be calibrated
Property, first time delay value in the channel to be calibrated is obtained, and, using the autocorrelation of the calibrating sequence of the reference channel,
Obtain the second time delay value of the reference channel；Based on first time delay value and second time delay value, obtain described to school
Delay inequality between quasi- channel and the reference channel；The delay inequality and the calibration filter coefficient are sent to the calibration
Filter, the delay inequality and the calibration filter coefficient are for characterizing the calibration filter；
Wherein, the calibration filter is used for according to the calibration filter coefficient and the delay inequality to the channel to be calibrated
It is calibrated.
2. device as described in claim 1, which is characterized in that the calibration filter is specially the variable filter of order,
In first time, by characterizing first delay inequality for calibrating filter and first filter coefficient to the first channel to be calibrated
It is calibrated；In second time different from the first time, by characterize the calibration filter the second delay inequality and
Second filter coefficient calibrates the second channel to be calibrated, wherein the rank of the calibration filter when first time
Number is R, and it is positive integer that the order with calibration filter described when second time, which is S, R and S,.
3. device as described in claim 1, which is characterized in that the DSP device is specifically used for:
Frequency-domain transform is carried out to the calibrating sequence in the channel to be calibrated and obtains the first numerical value, and the school to the reference channel
Quasi- sequence carries out frequency-domain transform and obtains second value；
Determine the ratio between the second value and first numerical value, wherein the ratio is the channel to be calibrated and institute
State the frequency domain response between reference channel；
To the frequency domain response carry out Fourier inversion obtain the calibration between the channel to be calibrated and the reference channel because
Son；
Determine that the calibration factor corresponds to M maximum impact response point, wherein M maximum impact response point is specially the school
Quasi- filter coefficient, M are positive integer.
4. device as described in claim 1, which is characterized in that the DSP device is specifically used for:
Obtain local sequence；
It is related that the calibrating sequence in the channel to be calibrated and the local sequence are subjected to conjugation, determine the relevant highest height of conjugation
First location information where peak point, and, the calibrating sequence of the reference channel and the local sequence are conjugated
Correlation determines the second location information being conjugated where relevant highest peak value point；
First time delay value in the channel to be calibrated is obtained based on the first location information, and, it is based on described second
Location information obtains second time delay value of the reference channel.
5. device as described in claim 1, which is characterized in that the DSP device is specifically used for according to preset data packet format
The delay inequality and the calibration filter coefficient are sent to the calibration filter, wherein the preset data packet format
Verified including short packet and with long packet verification and；
The calibration filter is verified and is verified described in the DSP device transmission according to the short packet verification and with the long packet
Filter coefficient and the delay inequality are calibrated, it is whether consistent with the data after being received via the calibration filter, wherein described
Short packet verification and include the calibration filter coefficient and the delay inequality, it is described it is long wrap verify and including remove packet header, packet tail it
The sum of outer all data.
6. device as described in claim 1, which is characterized in that the calibration filter is specially to have limit for length's unit impulse response
FIR filter.
7. device as described in claim 1, which is characterized in that the digital-to-analogue block of adopting is used for:
The calibrating sequence of respective channel is sent by the GP time slot of the radio frequency transmitting terminal in any channel.
8. device as described in claim 1, which is characterized in that the FPGA device and the DSP device pass through external storage
Device interface EMIF is connected.
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