CN209690498U - A kind of signal source of S-band wave observation radar - Google Patents
A kind of signal source of S-band wave observation radar Download PDFInfo
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- CN209690498U CN209690498U CN201821984508.XU CN201821984508U CN209690498U CN 209690498 U CN209690498 U CN 209690498U CN 201821984508 U CN201821984508 U CN 201821984508U CN 209690498 U CN209690498 U CN 209690498U
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Abstract
The utility model provides a kind of signal source of S-band wave observation radar, it is characterised in that: integrally disposed synchronous trigger circuit, signal generating circuit and radio frequency signal processing circuit on a printed circuit board, synchronous trigger circuit incoming radio frequency signal processing circuit；The signal generating circuit includes external clock input, clock distribution chip, single-ended transfer difference clock buffer chip, Direct Digital Frequency Synthesizers 1, Direct Digital Frequency Synthesizers 2, phaselocked loop and host computer interface, the radio frequency signal processing circuit is provided with 3 signal paths, 1st channel is connected with the output of Direct Digital Frequency Synthesizers 1,2nd channel is connected with the output of Direct Digital Frequency Synthesizers 2, and the 3rd channel is connected with the output of phaselocked loop.The characteristics of the utility model is designed using independent printed board, has small size, highly integrated, stable output signal, very well satisfies the requirement of microwave radar systems miniaturization.
Description
Technical field
The utility model belongs to the signal source device field of microwave radar, especially suitable for S-band wave observation radar.
Background technique
Currently, the intermediate-freuqncy signal and carrier signal of most of radar are all autonomous by system in the application of microwave radar
It generates, to the transmitting of radar and receives progress overall-in-one control schema using a radar host computer, obtain higher level of integrated system,
To obtain preferable stability and coherence.Traditional design scheme is to be divided signal generating circuit and rf processing circuitry
It cuts, it is individually designed respectively as two modules, it is then connected again by radio-frequency cable, this design scheme, it can be with
Ensure that all there is preferable performance when two modules work independently, but in actual application, but to the company between two modules
It connects and proposes higher requirement.Especially in coherent operation, the line-hit and transmission delay generated on circuit can direct shadow
The performance for arriving radar system is rung, meanwhile, different degrees of interference may also be generated in the analysis of radar echo signal.
Utility model content
Aiming at the problem that technical background proposes, the utility model provides a kind of signal source of S-band wave observation radar.Directly will
Signal generating circuit and rf processing circuitry carry out comprehensive design.
A kind of signal source of S-band wave observation radar of the technical solution of the utility model, it is integrally disposed on a printed circuit board
Synchronous trigger circuit, signal generating circuit and radio frequency signal processing circuit, synchronous trigger circuit incoming radio frequency signal processing circuit；
The signal generating circuit include external clock input, clock distribution chip, single-ended transfer difference clock buffer chip,
Direct Digital Frequency Synthesizers 1, Direct Digital Frequency Synthesizers 2, phaselocked loop and host computer interface,
Host computer interface is separately connected Direct Digital Frequency Synthesizers 1, Direct Digital Frequency Synthesizers 2, phaselocked loop；It is external
Clock inputs the input for being connected to clock distribution chip, and clock distribution chip exports two paths of signals, is directly accessed phaselocked loop all the way,
The input of single-ended transfer difference clock buffer chip is connected all the way；Single-ended transfer difference clock buffer chip exports two paths of signals, respectively
Connect the input of Direct Digital Frequency Synthesizers 1 and Direct Digital Frequency Synthesizers 2；
The radio frequency signal processing circuit is provided with 3 signal paths, the 1st channel and Direct Digital Frequency Synthesizers 1
Output is connected, and the 2nd channel is connected with the output of Direct Digital Frequency Synthesizers 2, and the 3rd channel is connected with the output of phaselocked loop.
Moreover, in the radio frequency signal processing circuit,
1st channel includes that sequentially connected difference turns single-end transformer 109, filter 110, amplifier circuit 111 and function
Rate adjusts circuit 112；
2nd channel includes that sequentially connected difference turns single-end transformer 104, the 1st filter 105, frequency mixer, the 2nd
The input all the way of filter 106, amplifier circuit 107 and power conditioning circuitry 108, frequency mixer is the defeated of the 1st filter 105
Out, another way input is the output of the electronic switch in the 3rd channel；
3rd channel includes electronic switch and sequentially connected filter 100, amplifier circuit 101, power divider
102 and power conditioning circuitry 103；The input of the connection power conditioning circuitry 103 of output all the way of power divider 102, it is another defeated
Electronic switch is connected out；The input all the way of electronic switch is the output of amplifier circuit 101, and another way input is synchronous triggering
The output of circuit.
Moreover, the synchronous trigger circuit includes switching signal input, switching signal output and buffer chip, switching signal
Input is directly connected to buffer chip, and buffer chip exports two paths of signals, is directly output to the electricity of radio frequency signal processing circuit all the way
Sub switch accesses switching signal output all the way.
Moreover, on a printed circuit board, V on plate corresponding with 3 signal paths of radio frequency signal processing circuit being arranged and cuts
And fluting.
Moreover, setting shielding cavity corresponding with printed circuit board shape.
Moreover, the shielding cavity is aluminum shielding cavity.
Moreover, the clock signal of clock distribution chip reaches Direct Digital frequency using delay matched line output with waiting delay
Rate synthesizer 1 and Direct Digital Frequency Synthesizers 2 and phaselocked loop.
The utility model removes the connecting interface of signal generating circuit and rf processing circuitry, and is plotted in one piece of printing
On circuit board, avoid signal quality caused by due to external interface poor contact, assembly are improper etc. be deteriorated, system work
Unstable situation.Compared to the prior art, other the advantages of and effect be:
1. the signal generating circuit route clock distribution chip and single-ended transfer difference clock buffer chip composition, can incite somebody to action
Direct Digital Frequency Synthesizers and phaselocked loop are distributed in the delays such as externally input clock signal, it is ensured that the clock that signal generates
Benchmark is consistent.
2. radio frequency signal processing circuit turns single-end transformer, filter circuit, mixting circuit, electronic switch, radio frequency by difference
Amplifying circuit, power conditioning circuitry composition carry out rear class amplification filtering and Frequency mixing processing to the radiofrequency signal of generation, then export
Signal.When due to work the radiofrequency signal parameter that generates can be directly controlled by external host computer and output loop in penetrate
The design of frequency switch, makes the signal source have good signal synchronism in transceiver radar system and coherent radar system
Energy.
3 signals that 2 Direct Digital Frequency Synthesizers and 1 phaselocked loop described in 3. generate handle electricity through radiofrequency signal
After the processing of road, 3 signals of output, intermediate frequency, radio frequency, local oscillation signal needed for can satisfy traditional S-band microwave radar systems
It is required that.
4. the setting of frequency mixer makes the signal source can be suitably used for L-band-C-band radar system, there is wider array of be applicable in
Range.
5. it is small-sized that compact circuit structure and corresponding Printed Circuit Board Design also very well satisfy microwave radar systems
The requirement of change.Therefore, the utility model is mainly used in novel miniaturization microwave radar systems.It is set using independent printed board
The characteristics of meter has small size, highly integrated, stable output signal.
Detailed description of the invention
Fig. 1 is the synchronous trigger circuit structural schematic diagram of the utility model embodiment；
Fig. 2 is the signal generating circuit structural schematic diagram of the utility model embodiment；
Fig. 3 is the radio frequency signal processing circuit structural schematic diagram of the utility model embodiment；
Fig. 4 is the overall structure diagram of the utility model embodiment；
Fig. 5 is the printed circuit board schematic diagram of the utility model embodiment.
Fig. 6 is the printed circuit board distribution schematic diagram of the utility model embodiment.
Specific embodiment
The embodiments of the present invention are further described with reference to the accompanying drawing.
Referring to fig. 4, the signal source of S-band wave observation radar provided by the embodiment of the utility model includes synchronous trigger circuit
(including switching signal input, switching signal output, buffer chip), signal generating circuit (including external clock input, clock point
Distribution chip, single-ended transfer difference clock buffer chip, 2 Direct Digital Frequency Synthesizers, 1 phaselocked loop, host computer interface), penetrate
Audio signalprocessing circuit (including difference turns single-end transformer, filter, power divider, electronic switch, frequency mixer, amplifier
Circuit, power conditioning circuitry etc.).
Synchronous trigger circuit incoming radio frequency signal processing circuit, for supporting delays such as externally input clock signals
Distribute to Direct Digital Frequency Synthesizers and phaselocked loop, it is ensured that the clock reference that signal generates is consistent.Referring to Fig. 1, synchronous triggering
In circuit, switching signal input is directly connected to buffer chip, and buffer chip exports two paths of signals, is directly output to radio frequency letter all the way
The electronic switch of number processing circuit directly exports all the way, i.e., switching signal exports.The synchronous trigger circuit, can be by external defeated
Radiofrequency signal after the switching signal entered is mixed signal source synchronizes output control, and the switching signal of input is by buffering core
It is directly exported after piece, can support to realize that multi-module cascade is synchronous using multiple signal sources provided by the utility model, it is ensured that
The synchronous consistency of system.In signal generating circuit, upper interface is directly connected to Direct Digital Frequency Synthesizers and locking phase respectively
Ring, clock signal are input from the outside, and radar system is made to share a reference clock.It is arranged by the order of host computer, it can be real-time
On-line control output signal amplitude, frequency, phase parameter, can strictly ensure the coherence of entire radar system work.
Referring to fig. 2, the input of the present embodiment external clock is connected to the input of clock distribution chip, and clock distribution chip exports two-way letter
Number, it is directly accessed phaselocked loop all the way, connects the input of single-ended transfer difference clock buffer chip all the way.Single-ended transfer difference clock buffer
Chip exports two paths of signals, is separately connected the input of Direct Digital Frequency Synthesizers 1 and Direct Digital Frequency Synthesizers 2.It is upper
Machine interface is separately connected phaselocked loop, Direct Digital Frequency Synthesizers 1 and Direct Digital Frequency Synthesizers 2.
The signal expense that phaselocked loop, Direct Digital Frequency Synthesizers 2 and Direct Digital Frequency Synthesizers 1 export is denoted as letter respectively
Numbers 3, signal 2 and signal 1.
The radio frequency signal processing circuit carries out rear class amplification filtering and Frequency mixing processing to the radiofrequency signal of generation, then
Output signal.The present embodiment radio frequency signal processing circuit is provided with 3 signal paths, the 1st channel and direct digital synthesis technique
The output of device 1 is connected, the 2nd channel is connected with the output of Direct Digital Frequency Synthesizers 2, the output phase in the 3rd channel and phaselocked loop
Even.The constant power power splitter of the amplifier circuit output connection 1/2 in the 3rd channel, then 1 road signal passes through after power conditioning circuitry
Output, 1 road signal are given frequency mixer by electronic switch and are mixed with the signal in channel 2.
Referring to Fig. 3,3 signal path specific structures are as follows:
1st channel includes that sequentially connected difference turns single-end transformer 109, filter 110, amplifier circuit 111 and function
Rate adjusts circuit 112, inputs as signal 1, the signal output in i.e. the 1st channel of the output of power conditioning circuitry 112.
2nd channel includes that sequentially connected difference turns single-end transformer 104, the 1st filter 105, frequency mixer, the 2nd
Filter 106, amplifier circuit 107 and power conditioning circuitry 108, input as signal 2, and the output of power conditioning circuitry 108 is
The signal in the 2nd channel exports；The input all the way of frequency mixer is the output of the 1st filter 105, and another way input is the 3rd channel
Electronic switch output.
3rd channel includes electronic switch and sequentially connected filter 100, amplifier circuit 101, power divider
102 and power conditioning circuitry 103, it inputs as signal 3, the output of power conditioning circuitry 103 is the signal output in the 3rd channel.Function
The input of the connection power conditioning circuitry 103 of output all the way of rate distributor 102, another output connect electronic switch.Electronic switch
Input all the way be amplifier circuit 101, another way input be synchronous trigger circuit output.
Through the above structure, 3 signal paths of the radio frequency signal processing circuit setting include at 2 independent signals
Manage channel and 1 mixing channel.Wherein 2 independent signal processing channels correspond to the 1st Direct Digital Frequency Synthesizers and
Phaselocked loop exports connect power splitter；It is mixed the output that channel corresponds to frequency mixer, input signal is from the 2nd Direct Digital frequency
Rate synthesizer and phaselocked loop export connect power splitter.Direct Digital Frequency Synthesizers can export linearly sweeping for 40-1250MHz
Frequency or frequency-fixed signal.Phaselocked loop can export the frequency-fixed signal of 40-6000MHz.
Wherein, difference turns single-end transformer the differential signal that Direct Digital Frequency Synthesizers export is switched to single-ended signal.
Filter filters out unwanted noise signal.The insertion loss of each device in the transmission loss and loop of amplifier offset signal,
Output signal is set to reach the output power of system requirements.The output signal of phaselocked loop is carried out 1/2 constant power distribution by power splitter, so
Frequency mixer is given on 1 tunnel afterwards, and another 1 tunnel exports after level-one power conditioning circuitry.Electronic switch controls the output signal of frequency mixer,
Output signal energy synchronism output after ensuring to be mixed by outer synchronous signal.Signal that frequency mixer generates phaselocked loop and the 2nd
The signal that Direct Digital Frequency Synthesizers generate carries out uppermixing, obtains the output signal of 1000-7000MHz.Power regulation electricity
Pin network composition is routed, when it is implemented, can flexibly adjust the output power of output signal, according to application demand to protect
The amplitude of card output signal meets the index demand of designing system, and defaulting undistorted output amplitude is+7dBm, and adjustable range is-
30dBm to+7dBm, adjustable extent is big, applied widely.
V on plate will be carried out on the present embodiment printed circuit board at 3 channel interconnections to cut and slot treatment, such as Fig. 5
With shown in Fig. 6, the V of the 1st channel upper and lower cuts shape 1, V cuts shape 2；Fluting shape 1, V below 2nd channel cut shape 3；The
V below 3 channels cuts shape 4.The signal cross-talk that special structure of being cut and slotted using V keeps radiofrequency signal treatment channel mutual
Reach minimum.Pcb board design outline is as shown in Fig. 5.The shielding cavity shape of aluminum is consistent with Fig. 5 shape.
When the present embodiment PCB routing designs, the clock signal that clock distribution chip is exported is with the side of isometric line
Formula is connected to Direct Digital Frequency Synthesizers and phaselocked loop, and the delay for realizing reference clock to each chip is identical, guarantees to generate
Signal phase it is consistent, make output signal stringent synchronization.Embodiment is set to clock distribution electricity using the matched serpentine that is delayed
Road makes the arrival Direct Digital Frequency Synthesizers and phaselocked loop of the delays such as input clock.
Preferably, the difference turns single-end transformer model ADT1-1WT+, filter model LFCN530,
LFCN630, BFCN2850, BFCN2275, Amplifier Model Gail84, Gail59, Gail39, Gail74, power splitter model
For SP2U, electronic switch model is Sky13286, and frequency mixer model ADE-18W, clock distribution chip model is ICS524, single
End turns differential clocks buffer chip model ADCLK925BCPZ, Direct Digital Frequency Synthesizers model AD9915, phaselocked loop
Model HMC833.
The above is only the preferred embodiments of the present utility model only, is not intended to limit the protection scope of the utility model,
Therefore, any modification, equivalent substitution, improvement and etc. made within the spirit and principle of the present invention, should be included in
Within the protection scope of the utility model.
Claims (7)
1. a kind of signal source of S-band wave observation radar, it is characterised in that: integrally disposed synchronous triggering electricity on a printed circuit board
Road, signal generating circuit and radio frequency signal processing circuit, synchronous trigger circuit incoming radio frequency signal processing circuit；
The signal generating circuit include external clock input, clock distribution chip, single-ended transfer difference clock buffer chip, directly
Digital frequency synthesizer 1, Direct Digital Frequency Synthesizers 2, phaselocked loop and host computer interface,
Host computer interface is separately connected Direct Digital Frequency Synthesizers 1, Direct Digital Frequency Synthesizers 2, phaselocked loop；External clock
Input is connected to the input of clock distribution chip, and clock distribution chip exports two paths of signals, is directly accessed phaselocked loop all the way, all the way
Connect the input of single-ended transfer difference clock buffer chip；Single-ended transfer difference clock buffer chip exports two paths of signals, is separately connected
The input of Direct Digital Frequency Synthesizers 1 and Direct Digital Frequency Synthesizers 2；
The radio frequency signal processing circuit is provided with 3 signal paths, the output in the 1st channel and Direct Digital Frequency Synthesizers 1
It is connected, the 2nd channel is connected with the output of Direct Digital Frequency Synthesizers 2, and the 3rd channel is connected with the output of phaselocked loop.
2. the signal source of S-band wave observation radar according to claim 1, it is characterised in that: the radio frequency signal processing circuit
In,
1st channel include sequentially connected difference turn single-end transformer (109), filter (110), amplifier circuit (111) and
Power conditioning circuitry (112)；
2nd channel includes that sequentially connected difference turns single-end transformer (104), the 1st filter (105), frequency mixer, the 2nd
Filter (106), amplifier circuit (107) and power conditioning circuitry (108), the input all the way of frequency mixer are the 1st filter
(105) output, another way input are the output of the electronic switch in the 3rd channel；
3rd channel includes electronic switch and sequentially connected filter (100), amplifier circuit (101), power divider
(102) and power conditioning circuitry (103)；The output all the way of power divider (102) connects the defeated of power conditioning circuitry (103)
Enter, another output connects electronic switch；The input all the way of electronic switch is the output of amplifier circuit (101), another way input
For the output of synchronous trigger circuit.
3. the signal source of S-band wave observation radar according to claim 2, it is characterised in that: the synchronous trigger circuit includes
Switching signal input, switching signal output and buffer chip, switching signal input are directly connected to buffer chip, buffer chip output
Two paths of signals is directly output to the electronic switch of radio frequency signal processing circuit all the way, accesses switching signal output all the way.
4. the signal source of the according to claim 1 or 2 or 3 S-band wave observation radars, it is characterised in that: on a printed circuit board,
V on plate corresponding with 3 signal paths of radio frequency signal processing circuit is arranged to cut and slot.
5. the signal source of S-band wave observation radar according to claim 4, it is characterised in that: setting and printed circuit board shape
Corresponding shielding cavity.
6. the signal source of S-band wave observation radar according to claim 5, it is characterised in that: the shielding cavity is aluminum screen
Cover cavity.
7. the signal source of the according to claim 1 or 2 or 3 S-band wave observation radars, it is characterised in that: clock distribution chip
Clock signal reaches Direct Digital Frequency Synthesizers 1 and direct digital synthesis technique with waiting delay using delay matched line output
Device 2 and phaselocked loop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821984508.XU CN209690498U (en) | 2018-11-29 | 2018-11-29 | A kind of signal source of S-band wave observation radar |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821984508.XU CN209690498U (en) | 2018-11-29 | 2018-11-29 | A kind of signal source of S-band wave observation radar |
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| Publication Number | Publication Date |
|---|---|
| CN209690498U true CN209690498U (en) | 2019-11-26 |
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ID=68595276
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821984508.XU Expired - Fee Related CN209690498U (en) | 2018-11-29 | 2018-11-29 | A kind of signal source of S-band wave observation radar |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110988830A (en) * | 2020-01-03 | 2020-04-10 | 零八一电子集团有限公司 | Multi-frequency-band radar target simulator |
| CN111308579A (en) * | 2020-03-20 | 2020-06-19 | 南京大桥机器有限公司 | L-waveband narrow-band electronic sonde |
-
2018
- 2018-11-29 CN CN201821984508.XU patent/CN209690498U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110988830A (en) * | 2020-01-03 | 2020-04-10 | 零八一电子集团有限公司 | Multi-frequency-band radar target simulator |
| CN111308579A (en) * | 2020-03-20 | 2020-06-19 | 南京大桥机器有限公司 | L-waveband narrow-band electronic sonde |
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| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
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Granted publication date: 20191126 Termination date: 20201129 |