CN209390099U - Detection circuit and clock data recovery circuit - Google Patents
Detection circuit and clock data recovery circuit Download PDFInfo
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- CN209390099U CN209390099U CN201920301453.6U CN201920301453U CN209390099U CN 209390099 U CN209390099 U CN 209390099U CN 201920301453 U CN201920301453 U CN 201920301453U CN 209390099 U CN209390099 U CN 209390099U
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Abstract
Disclose a kind of detection circuit and clock data recovery circuit.The phase discriminator includes: main circuit, for providing multiple M signals according to data input signal and reference clock signal and adjusting indication signal, first detection unit, for according to data input signal, reference clock signal, corresponding M signal and the first clock signal the first logical signal of generation for being ahead of reference clock signal；Second detection unit, for according to data input signal, reference clock signal, corresponding M signal and second clock signal the second logical signal of generation for lagging behind reference clock signal；And judging unit, for generating indication signal, jitter compensation type needed for indication signal characterize data input signal according to the logical relation between the first logical signal, the second logical signal and data input signal.Jitter compensation type needed for the indication signal characterize data input signal of the detection circuit, to take corresponding measure to reduce the bit error rate.
Description
Technical field
The utility model relates to digital communication technology fields, extensive more particularly, to a kind of detection circuit and clock data
Compound circuit.
Background technique
Clock data recovery circuit (Clock and Data Recovery, CDR) is the nucleus module of high-speed transceiver,
And high-speed transceiver is the important component in communication system.When data flow is transmitted in tandem data circuit, not
Subsidiary clock signal, Serial data receiving end need to be extracted from the data input signal received by clock data recovery circuit
Synchronised clock, and reliable and stable data are obtained to data input signal resampling using the synchronised clock.However, high speed
The data input signal of interconnection circuit signal quality after long distance transmission often has serious loss, this external environment is made an uproar
Sound can further deteriorate signal quality, to cause the bit error rate (symbol error rate, SER) of data input signal no
Meet demand, receiving end are restored data difficulty and are increased.
The long distance transmission loss of signal normally behaves as intersymbol interference (Inter Symbol Interference, ISI).
Fig. 1 shows the waveform diagram of the clock data recovery circuit of the prior art.As shown in Figure 1, when transmission channel bandwidth is not enough to pass
When transmission of data input signal, this means that the time span in individual signals period can not enable data input signal is intact to build
It is vertical.As shown in t1 and t2, output signal can not establish in one cycle ceiling voltage and can not be in one cycle
Restore to minimum voltage, thus the signal after being resumed its rising edge and failing edge will relative ideal signal be deviated.
When transmission channel bandwidth further becomes smaller, signal is possible to can not also establish within the time in two periods, it will generates more
Complicated intersymbol interference phenomenon simultaneously brings bigger time deviation, further deteriorates so as to cause the quality of signal, or even letter
It number can not be in one cycle more than V0/ 2, so that signal can not normally restore.In order to solve the problems, such as intersymbol interference, existing skill
Art carries out preemphasis in output end and adds balanced device (Equalizer, EQ) in input receiving end, and principle is increase high frequency
Gain, to compensate the high frequency loss of channel.But excessive increase high-frequency gain, so that the overcompensation of signal high frequency section can also be led
It causes signal jitter to be deteriorated, and will also result in the waste of power consumption.
Another influence data input signal performance factor be exactly noise, data input signal generate, transmission and
During received, can all there be noise to introduce so as to cause data input signal quality variation.When input signal noise is biggish
When, need clock data recovery circuit bandwidth to increase to track the shake of input signal, to correctly restore signal.But when
The shake that the bandwidth increase of clock data recovery circuit also results in clock data recovery circuit itself becomes larger, to influence error code
Rate.
Intersymbol interference and noise both effect signal quality, cause high bit-error, but the solution of the two and different.
And the channel circumstance of high speed interconnection equipment is not unalterable, such as network interface, video interface, different user institutes
Line material and wire length are all very different, and the environment of work is not also identical, are not available identical configuration
Solve all user demands.
Utility model content
In view of the above problems, the purpose of this utility model is to provide a kind of detection circuit and clock data recovery circuit,
Wherein, the reason of data input signal shake being judged according to data input signal, the second logical signal and the first logical signal, from
And balanced device and bandwidth are adjusted separately according to the result of judgement to reduce the bit error rate.
One side according to the present utility model provides a kind of detection circuit, comprising: main circuit, for being inputted according to data
Signal and reference clock signal provide multiple M signals and adjust indication signal, first detection unit, for according to the number
According to input signal, the reference clock signal, the corresponding M signal and it is ahead of the of the reference clock signal
One clock signal generates the first logical signal；Second detection unit, for according to the data input signal, the reference clock
Signal, the corresponding M signal and second clock signal generation the second logic letter for lagging behind the reference clock signal
Number；And judging unit, for according to first logical signal, second logical signal and the data input signal it
Between logical relation generate indication signal, jitter compensation type needed for the indication signal characterizes the data input signal.
Preferably, the indication signal includes the first indication signal, the second indication signal and third indication signal, if institute
Stating the first logical signal is high level, and when the data input signal level state changes, second logical signal is
High level, then first indication signal is effective, if second logical signal is high level, and when data input letter
When number level state changes, first logical signal is high level, then second indication signal is effective, if described first
Logical signal and/or second logical signal are high level, and when the data input signal level state changes, described
The level state of first logical signal and/or second logical signal remains unchanged, then the third indication signal is effective.
Preferably, the period of the reference clock signal is T, first clock signal and the reference clock signal
Phase difference is greater than 0 and is not more than T/4, and the phase difference of the second clock signal and the reference clock signal is greater than 0 and little
In T/4.
Preferably, the main circuit includes the first trigger, the second trigger, third trigger, the 4th trigger, first
XOR gate and the second XOR gate, the M signal include first M signal, second M signal, third M signal and
Four M signals, the adjusting indication signal includes the first adjusting indication signal and second adjusts indication signal, first touching
It sends out device and the first M signal, second trigger is generated according to the data input signal and the reference clock signal
Generate the second M signal according to the first M signal and the reference clock signal, the third trigger according to
The complementary signal of the data input signal and the reference clock signal generates the third M signal, the 4th triggering
Device generates the 4th M signal, the first XOR gate root according to the third M signal and the reference clock signal
Described first, which is generated, according to the second M signal and the 4th M signal adjusts indication signal, the second XOR gate root
Described second, which is generated, according to the first M signal and the 4th M signal adjusts indication signal.
Preferably, the first detection unit include the 5th trigger, the 6th trigger and third XOR gate, described second
Detection unit includes the 7th trigger, the 8th trigger and the 4th XOR gate, and the 5th trigger is inputted according to the data
Signal and the complementary signal of first clock signal generate the first sampled signal, and the 6th trigger is adopted according to described first
Sample signal and the reference clock signal generate first logical signal, and the 7th trigger is inputted according to the data to be believed
Number and the second clock signal complementary signal generate the second sampled signal, the 8th trigger according to it is described second sampling
Signal and the reference clock signal generate second logical signal.
Preferably, when being detected, it is single that the first detection unit, the second detection unit and the judgement are opened
Member turns off the first detection unit, the second detection unit and the judging unit when stopping detection.
Another aspect according to the present utility model provides a kind of clock data recovery circuit, comprising: detection as described above
Circuit, the main circuit of the detection circuit generate the data-signal recovered；And clock generating unit, when for providing
Clock signal, the clock signal include the reference clock signal, first clock signal and the second clock signal, institute
The bandwidth for stating clock signal is controlled by the indication signal.
Preferably, further includes: balanced device, for receiving original signal and providing thermal compensation signal to the original signal, with
Generate the data input signal, the thermal compensation signal it is gain controlled in the indication signal.
Preferably, the indication signal includes the first indication signal, the second indication signal and third indication signal, if institute
Stating the first logical signal is high level, and when the data input signal level state changes, second logical signal is
High level, then first indication signal is effective, if second logical signal is high level, and when data input letter
When number level state changes, first logical signal is high level, then second indication signal is effective, if described first
Logical signal and/or second logical signal are high level, and when the data input signal level state changes, described
The level state of first logical signal and/or second logical signal remains unchanged, then the third indication signal is effective,
In, when first indication signal is effective, the gain of the thermal compensation signal reduces, when second indication signal is effective,
The gain of the thermal compensation signal increases, and when the third indication signal is effective, the bandwidth of the clock signal increases.
Preferably, before starting to receive the original signal, the clock generating unit provides first clock signal
With the second clock signal to carry out signal detection, after receiving the original signal, the clock generating unit stops
First clock signal is provided and the second clock signal is detected with stop signal.
Preferably, the clock generating unit includes: clock generator, for generating first clock signal；First
Delay unit, for generating the reference clock signal according to first clock signal；And second delay unit, it is used for root
The second clock signal is generated according to the reference clock signal, wherein the period of the reference clock signal is T, described the
The phase difference of one clock signal and the reference clock signal is greater than 0 and is not more than T/4, the second clock signal and the ginseng
The phase difference for examining clock signal is greater than 0 and no more than T/4.
Preferably, further includes: filter is connected to the detection circuit, for being generated according to the adjusting indication signal
Voltage signal, wherein the output end of the filter is connected to the clock generating unit, the clock generating unit also according to
The voltage signal generates the clock signal recovered, and the clock signal recovered is provided to the detection circuit.
Detection circuit provided by the utility model and clock data recovery circuit, according to data input signal, the first logic
Phase relation between signal and the second logical signal is distinguished is trembled due to caused by intersymbol interference and noise in data input signal
It is dynamic, and go adjustment balanced device and bandwidth respectively according to the result of judgement, so that the bit error rate be made to be preferably minimized.Further, the inspection
Slowdown monitoring circuit and clock data recovery circuit do not need to continue working, can be only when Path Setup or certain interval of time
Starting is primary, will not bring additional power consumption to original receiving terminal circuit.
Detailed description of the invention
By referring to the drawings to the description of the utility model embodiment, above-mentioned and other mesh of the utility model
, feature and advantage will be apparent from, in the accompanying drawings:
Fig. 1 shows the waveform diagram of clock data recovery circuit according to prior art；
Fig. 2 shows the electrical block diagrams of phase discriminator according to prior art；
Fig. 3 shows the timing diagram of phase discriminator according to prior art；
Fig. 4 shows the structural block diagram of the clock data recovery circuit according to the utility model embodiment；
Fig. 5 shows the schematic diagram of the clock generating unit according to the utility model embodiment；
Fig. 6 shows the timing diagram of the clock generating unit according to the utility model embodiment；
Fig. 7 shows the electrical block diagram of the phase discriminator according to the utility model embodiment.
Reference signs list
100 clock data recovery circuits
110 balanced devices
120 clock generating units
121 first delay units
122 second delay units
123 clock generators
130 phase discriminators
131 main circuits
132 first detection units
133 second detection units
140 judging units
150 filters
200 detection circuits
Specific embodiment
Hereinafter reference will be made to the drawings is more fully described the various embodiments of the utility model.In various figures, identical
Element is indicated using same or similar appended drawing reference.For the sake of clarity, the various pieces in attached drawing are not drawn to draw
System.
With reference to the accompanying drawings and examples, specific embodiment of the present utility model is described in further detail.
Fig. 2 shows the electrical block diagrams of phase discriminator according to prior art；Fig. 3 is shown according to prior art
The timing diagram of phase discriminator.
Phaselocked loop (Phase-locked loops, PLL) is the core component of clock data recovery circuit, and phase discriminator is lock
Critical component in phase loop circuit.As shown in Fig. 2, by taking the clock data recovery circuit of bang-bang phase discriminator type as an example, it is existing
The phase discriminator for having technology includes first order trigger and second level trigger and logic circuit.First order trigger includes trigger
Q1 and trigger Q2 obtains data sample sequence for sampling to data input signal.Second level trigger includes triggering
Device Q3 and trigger Q4 exports the data-signal recovered for retiming to data sample sequence.Logic circuit packet
Include XOR gate U1 and XOR gate U2, the phase difference between data-signal for comparing data sample sequence and recovering and export
Phase signal UP and DN.
As shown in figure 3, the failing edge of clock signal CKS and the data of input are defeated when clock data recovery circuit locking
Enter the overturning of signal DIN along alignment, to guarantee there is maximum nargin when clock signal CKS rising edge adopts data.Cause
It is aligned for the failing edge of clock signal CKS and the overturning edge of data input signal DIN, so clock signal CKS failing edge samples
Data before being possible to adopt data input signal DIN overturning when data input signal DIN are also possible to sample data defeated
Enter the data after signal DIN overturning, the probability occurred both when not considering non-ideal effects is almost the same.
Clock data recovery circuit can promote clock signal CKS to go the shake of tracking data input signal DIN, but if counting
Shake according to input signal DIN is as caused by ISI, and traditional design clock signal CKS can not judge, will lead to clock signal
The change direction of CKS and intersymbol interference it is contrary, increase the bit error rate, and if the shake of data input signal DIN is
As caused by noise, then clock signal CKS is needed to be capable of fast tracking the variation of data input signal DIN.Therefore intersymbol interference
Requirement with noise to clock data recovery circuit responsive bandwidth is not consistent, i.e., if shake is caused by intersymbol interference, when
Clock data recovery circuit does not go to track as far as possible, and shakes if it is caused by noise, and clock data recovery circuit should be as far as possible
Tracking on.
In order to solve this intersymbol interference and the exactly the opposite demand of noise, the application by the jittering characteristic of detection signal simultaneously
Then record counts in digital circuit and analyzes it and shakes reason for intersymbol interference or noise, then if it is intersymbol interference
Adjust balancer characteristic or if the adjustable transmission of function that transport protocol has reverse transfer to instruct of frontend amplifying circuit
The pre-emphasis characteristic of grade, clock data recovery circuit bandwidth is then adjusted if it is noise keeps clock data recovery circuit better
Track input signal.
Fig. 4 shows the structural block diagram of the clock data recovery circuit according to the utility model embodiment.
As shown in figure 4, the clock data recovery circuit 100 of the utility model embodiment includes balanced device 110, clock generation
Unit 120, phase discriminator 130, judging unit 140 and filter 150.Detection circuit 200 includes phase discriminator 130 and judging unit
140。
Balanced device 110 is connected to the first input end of phase discriminator 120, the original number inputted for receiving external circuit to it
It is compensated according to input signal, and to the initial data input signal, generates data input signal, and enter data into signal
It is transmitted to phase discriminator 120.
The output end of clock generating unit 120 is connected to phase discriminator 130, for providing clock signal.Clock generating unit
120 the first output end, second output terminal and third output end generates reference clock signal CKS, advanced clock signal respectively
CSK_LEAD (i.e. the first clock signal) and lagging clock signal CKS_LAG (i.e. second clock signal).
The first input end of phase discriminator 130 is connected to balanced device 110, for receiving data input signal, phase discriminator 130
Second input terminal, third input terminal and the 4th input terminal are respectively connected to the first output end of clock generating unit 130, second defeated
Outlet and third output end receive reference clock signal CKS, advanced clock signal CSK_LEAD and lagging clock signal respectively
CKS_LAG.Phase discriminator 130 is used for the data-signal Q2 for generating data sample sequence and recovering, and compares data sample sequence
Phase difference and output phase difference signal UPL (i.e. the first logical signal), phase difference letter between the data-signal Q2 recovered
Number DNL (i.e. the second logical signal), phase signal UP (i.e. first adjusts control signal) and phase signal DN (the i.e. second tune
Section control signal).
Judging unit 140 is used to receive the data-signal Q2 and phase signal UPL, UP, DN and DNL recovered, and
Be converted into parallel data, reduce frequency, using digital signal judge data input signal and phase signal UPL with
Relationship between DNL, thus the reason of judgement causes data input signal to be shaken, and at least two are generated according to the result of judgement
Indication signal is to adjust separately the high-frequency gain of balanced device 110 and the bandwidth of clock generating unit 120.For example, judging unit 140
It generates the first indication signal and the second indication signal is used to adjust the high-frequency gain of balanced device 110, judging unit 140 generates third
Indication signal is used to adjust the bandwidth of clock generating unit 120.Judging unit 140 is for example including microcontroller
(microcomputer,MCU)。
Preferably, it after the Bandwidth adjustment of the high-frequency gain of balanced device 110 and clock generating unit 120 finishes, closes
Advanced two sampling accesses of clock signal CSK_LEAD and lagging clock signal CKS_LAG and judging unit 140, to reduce function
Consumption.
Preferably, only when the transmission channel of transceiver is established or certain interval of time opens advanced clock signal CSK_
Two sampling accesses of LEAD and lagging clock signal CKS_LAG and judging unit 140, to reduce power consumption, and when will not influence
The performance of clock data recovery circuit.
In this embodiment, if the number of phase signal DNL and UPL appearance 1 is less, judging unit 140 is sentenced
Determining result is that the bit error rate is smaller, without being adjusted to 120 clock generating unit 120 of balanced device.If phase signal DNL and
The number that UPL occurs 1 is more, then the judgement result of judging unit 140 is larger for the bit error rate, needs further to data input signal
The reason of shake, is analyzed.
When continuous multiple constant data input signals change, if phase signal UPL is always 1, and data
Phase signal DNL is often 1 when input signal continuous overturning, then the judgement result of judging unit 140 is serious for intersymbol interference,
Judging unit 140 generates the first indication signal and is transmitted to balanced device 120, so that balanced device 120 be adjusted, reduces high frequency and increases
Benefit.
When continuous multiple constant data input signals change, if phase signal DNL is always 1, and data
Phase signal UPL is often 1 when input signal continuous overturning, then the judgement result of judging unit 140 is serious for intersymbol interference,
Judging unit 140 generates the second indication signal and is transmitted to balanced device 120, so that balanced device 120 be adjusted, increases high frequency and increases
Benefit.
If phase signal DNL or UPL are continuously 1, and unrelated with the series styles of data input signal, then it is assumed that defeated
Enter to shake larger, the bandwidth of clock generating unit 120 is not enough to normally track, and judging unit 140 generates the second indication signal
It is transmitted to clock generating unit 120, to improve the bandwidth of clock generating unit 120.
Detection circuit 200 includes phase discriminator 130 and judging unit 140, for detecting to data input signal, and extremely
Few to generate detection signal, the detection signal includes at least an above-mentioned judgement result.Preferably, detection circuit 200 also exports
According at least two indication signals that detection signal generates, it is used for according to the judgement result respectively to balanced device 110 and clock
Generation unit 120 is controlled.
Filter 150 is connected to the output end of phase discriminator 140, and clock generating unit 120 is connected to the output of filter 150
End, filter 150 and clock generating unit 120 are used to receive the phase signal UP and DN of the generation of phase discriminator 150, and export extensive
The clock signal appeared again.
Fig. 5 shows the schematic diagram of the clock generating unit according to the utility model embodiment；Fig. 6 is shown according to this reality
With the timing diagram of the clock generating unit of new embodiment.
As shown in figure 5, the clock generating unit 120 of the utility model embodiment is for example including the first delay unit 151,
Two delay units 122 and clock generator 123, for providing clock signal.First output end of clock generating unit 120,
Two output ends and third output end generate reference clock signal CKS, advanced clock signal CSK_LEAD and lagging clock letter respectively
Number CKS_LAG.
Clock generator 123 generates advanced clock signal CSK_LEAD, and advanced clock signal CSK_LEAD is transmitted to
First delay unit 121；First delay unit 121 generates reference clock signal CKS according to advanced clock signal CSK_LEAD, and
Reference clock signal CKS is transmitted to the second delay unit 122, the second delay unit 122 generates lagging clock signal CKS_
LAG.Clock generator 123 is for example including at least one of voltage controlled oscillator, phase interpolator or quartz-crystal resonator.
As shown in fig. 6, the period of reference clock signal CKS is T on the basis of the phase of reference clock signal CKS.In advance
Clock signal CSK_LEAD is more advanced than reference clock signal CKS, advanced clock signal CSK_LEAD and reference clock signal CKS it
Between phase difference be greater than 0, be less than or equal to T/4；Lagging clock signal CKS_LAG is lagged than reference clock signal CKS, lagging clock
Phase difference between signal CKS_LAG and reference clock signal CKS is greater than 0, is less than or equal to T/4.Preferably, advanced clock signal
Phase difference between CSK_LEAD and reference clock signal CKS is equal to T/8；Lagging clock signal CKS_LAG and reference clock are believed
Phase difference between number CKS is equal to T/8.
Fig. 7 shows the electrical block diagram of the phase discriminator according to the utility model embodiment.
As shown in fig. 7, the phase discriminator 130 of the utility model embodiment includes main circuit 131,132 and of first detection unit
Second detection unit 133.
Main circuit 131 includes trigger Q1, trigger Q2, trigger Q3, trigger Q4, XOR gate U1 and XOR gate
U2.Trigger Q1 generates first M signal according to data input signal DIN and reference clock signal CKS, trigger Q1 according to
First M signal and reference clock signal CKS generate second M signal, when trigger Q3 is according to data-signal DIN and reference
The complementary signal of clock signal generates third M signal, and trigger Q4 is raw according to third M signal and reference clock signal CKS
At the 4th M signal, XOR gate U1 generates first according to second M signal and the 4th M signal and adjusts indication signal, different
Or door U2 generates second according to first M signal and the 4th M signal and adjusts indication signal.Main circuit 131 will be among second
Signal exports as the data-signal DIN recovered and receives circuit to next stage.
First detection unit 132 includes trigger Q5, trigger Q6 and XOR gate U3.Trigger Q5 is according to data-signal
The complementary signal of DIN and advanced clock signal CSK_LEAD generate the first sampled signal, and the 6th trigger is believed according to the first sampling
Number and reference clock signal CKS generate the first logical signal,
Second detection unit 133 includes trigger Q7, trigger Q8 and XOR gate U4.Trigger Q7 is according to data-signal
The complementary signal of DIN and lagging clock signal CKS_LAG generate the second sampled signal, trigger Q8 according to the second sampled signal and
Reference clock signal CKS generates the second logical signal.Trigger Q1 to Q8 is for example d type flip flop.
Compared with prior art, increase the first detection unit including trigger Q5, trigger Q6 and XOR gate U3 with
And the second detection unit including trigger Q7, trigger Q8 and XOR gate U4, utilize data input signal DIN, advanced clock
Signal CSK_LEAD and lagging clock signal CKS_LAG signal generate two signals of DNL and UPL.Because of advanced clock signal
CKS_LEAD is prior to reference clock signal CKS, so if UPL signal is 1, it is believed that reference clock signal CKS falls behind number
It is excessive according to input signal DIN；Because lagging clock signal CKS_LAG is later than reference clock signal CKS, if DNL signal
It is 1, then it is believed that the leading data input signal DIN of reference clock signal CKS is excessive；If UPL signal and DNL signal are often
1, then it represents that reference clock signal CDR tracking data input signal DIN is relatively difficult, and clock has biggish tremble relative to data
It is dynamic.
It is as described above according to the embodiments of the present invention, these embodiments details all there is no detailed descriptionthe,
Also not limiting the utility model is only the specific embodiment.Obviously, as described above, many modification and change can be made
Change.These embodiments are chosen and specifically described to this specification, is in order to preferably explain the principles of the present invention and actually to answer
With so that skilled artisan be enable to utilize the utility model and repairing on the basis of the utility model well
Change use.The utility model is limited only by the claims and their full scope and equivalents.
Claims (12)
1. a kind of detection circuit characterized by comprising
Main circuit, for providing multiple M signals according to data input signal and reference clock signal and adjusting indication signal,
First detection unit, for according to the data input signal, the reference clock signal, the corresponding M signal
And it is ahead of the first clock signal the first logical signal of generation of the reference clock signal；
Second detection unit, for according to the data input signal, the reference clock signal, the corresponding M signal
And lag behind second clock signal the second logical signal of generation of the reference clock signal；And
Judging unit, for according between first logical signal, second logical signal and the data input signal
Logical relation generate indication signal, jitter compensation type needed for the indication signal characterizes the data input signal.
2. detection circuit according to claim 1, which is characterized in that the indication signal includes the first indication signal, the
Two indication signals and third indication signal,
If first logical signal is high level, and when the data input signal level state changes, described second
Logical signal is high level, then first indication signal is effective,
If second logical signal is high level, and when the data input signal level state changes, described first
Logical signal is high level, then second indication signal is effective,
If first logical signal and/or second logical signal are high level, and when the data input signal electricity
When level state changes, the level state of first logical signal and/or second logical signal is remained unchanged, then and described the
Three indication signals are effective.
3. detection circuit according to claim 1, which is characterized in that the period of the reference clock signal is T, described the
The phase difference of one clock signal and the reference clock signal is greater than 0 and is not more than T/4, the second clock signal and the ginseng
The phase difference for examining clock signal is greater than 0 and no more than T/4.
4. detection circuit according to claim 1, which is characterized in that
The main circuit includes the first trigger, the second trigger, third trigger, the 4th trigger, the first XOR gate and the
Two XOR gates,
The M signal includes first M signal, second M signal, third M signal and the 4th M signal,
The adjusting indication signal includes that the first adjusting indication signal and second adjust indication signal,
First trigger generates the first M signal according to the data input signal and the reference clock signal,
Second trigger generates the second M signal according to the first M signal and the reference clock signal,
The third trigger generates described the according to the complementary signal of the data input signal and the reference clock signal
Three M signals,
4th trigger generates the 4th M signal according to the third M signal and the reference clock signal,
First XOR gate generates described first according to the second M signal and the 4th M signal and adjusts instruction
Signal,
Second XOR gate generates described second according to the first M signal and the 4th M signal and adjusts instruction
Signal.
5. detection circuit according to claim 4, which is characterized in that
The first detection unit includes the 5th trigger, the 6th trigger and third XOR gate,
The second detection unit includes the 7th trigger, the 8th trigger and the 4th XOR gate,
5th trigger generates first according to the data input signal and the complementary signal of first clock signal and adopts
Sample signal, the 6th trigger, which generates first logic according to first sampled signal and the reference clock signal, to be believed
Number,
7th trigger generates second according to the complementary signal of the data input signal and the second clock signal and adopts
Sample signal, the 8th trigger, which generates second logic according to second sampled signal and the reference clock signal, to be believed
Number.
6. detection circuit according to claim 1, which is characterized in that
When being detected, the first detection unit, the second detection unit and the judging unit are opened,
When stopping detection, the first detection unit, the second detection unit and the judging unit are turned off.
7. a kind of clock data recovery circuit characterized by comprising
Such as detection circuit as claimed in any one of claims 1 to 6, the main circuit of the detection circuit generates the number recovered
It is believed that number；And
Clock generating unit, for providing clock signal, the clock signal include the reference clock signal, it is described first when
Clock signal and the second clock signal, the bandwidth of the clock signal are controlled by the indication signal.
8. clock data recovery circuit according to claim 7, which is characterized in that further include: balanced device, for receiving original
Beginning signal simultaneously provides thermal compensation signal to the original signal, to generate the data input signal, the gain of the thermal compensation signal
It is controlled by the indication signal.
9. clock data recovery circuit according to claim 8, which is characterized in that
The indication signal includes the first indication signal, the second indication signal and third indication signal,
If first logical signal is high level, and when the data input signal level state changes, described second
Logical signal is high level, then first indication signal is effective,
If second logical signal is high level, and when the data input signal level state changes, described first
Logical signal is high level, then second indication signal is effective,
If first logical signal and/or second logical signal are high level, and when the data input signal electricity
When level state changes, the level state of first logical signal and/or second logical signal is remained unchanged, then and described the
Three indication signals are effective,
Wherein, when first indication signal is effective, the gain of the thermal compensation signal reduces,
When second indication signal is effective, the gain of the thermal compensation signal increases,
When the third indication signal is effective, the bandwidth of the clock signal increases.
10. clock data recovery circuit according to claim 8, which is characterized in that
Before starting to receive the original signal, the clock generating unit provide first clock signal and it is described second when
Clock signal to carry out signal detection,
After receiving the original signal, the clock generating unit stops providing first clock signal and described second
Clock signal is detected with stop signal.
11. clock data recovery circuit according to claim 7, which is characterized in that the clock generating unit includes:
Clock generator, for generating first clock signal；
First delay unit, for generating the reference clock signal according to first clock signal；And
Second delay unit, for generating the second clock signal according to the reference clock signal,
Wherein, the period of the reference clock signal is T, the phase difference of first clock signal and the reference clock signal
Greater than 0 and it is not more than T/4, the phase difference of the second clock signal and the reference clock signal is greater than 0 and is not more than T/4.
12. clock data recovery circuit according to claim 7, which is characterized in that further include:
Filter is connected to the detection circuit, for generating voltage signal according to the adjusting indication signal,
Wherein, the output end of the filter is connected to the clock generating unit, and the clock generating unit is also according to described
Voltage signal generates the clock signal recovered, and the clock signal recovered is provided to the detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920301453.6U CN209390099U (en) | 2019-03-08 | 2019-03-08 | Detection circuit and clock data recovery circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109787925A (en) * | 2019-03-08 | 2019-05-21 | 北京集创北方科技股份有限公司 | Detection circuit, clock data recovery circuit and signal detecting method |
| CN112688701A (en) * | 2020-12-22 | 2021-04-20 | 北京奕斯伟计算技术有限公司 | Receiver circuit and receiver circuit control method |
| CN114967807A (en) * | 2022-03-28 | 2022-08-30 | 清华大学 | Timing detection circuit and adaptive voltage regulation circuit |
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2019
- 2019-03-08 CN CN201920301453.6U patent/CN209390099U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109787925A (en) * | 2019-03-08 | 2019-05-21 | 北京集创北方科技股份有限公司 | Detection circuit, clock data recovery circuit and signal detecting method |
| CN112688701A (en) * | 2020-12-22 | 2021-04-20 | 北京奕斯伟计算技术有限公司 | Receiver circuit and receiver circuit control method |
| CN114967807A (en) * | 2022-03-28 | 2022-08-30 | 清华大学 | Timing detection circuit and adaptive voltage regulation circuit |
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