CN209267704U - A kind of signal generation apparatus - Google Patents

Abstract

The utility model embodiment provides a kind of signal generation apparatus, including FPGA field programmable gate array and the first level shifting circuit, the FPGA includes high speed signal output interface set, each high speed signal output interface exports high speed signal in the high speed signal output interface set；The input terminal of first level shifting circuit is connected with the high speed signal output interface set, first level shifting circuit can be inputted the high speed signal that termination receives and be converted into the high speed signal that level belongs to the described first default amplitude range, based on this, the high speed signal of the available different types of high speed signal output interface output of FPGA can be converted to by first level shifting circuit meets high speed signal as defined in C-PHY specification protocol, reduce the limitation selected FPGA signal output interface type or FPGA signal output interface output signal level, increase the versatility of signal generation apparatus.

Description

A kind of signal generation apparatus

Technical field

The utility model embodiment is related to signal processing technology field, more particularly relates to a kind of signal generation apparatus.

Background technique

MIPI (Mobile Industry Processor Interface, Mobile Industry Processor Interface) is a kind of shifting Dynamic communications industry equipment interior video data transmission interface standard, PHY (Port Physical Layer, the end of common MIPI Mouth physical layer) it include the multiple types such as D-PHY, M-PHY, with the development of smart machine, in recent years, electronic equipment is for example intelligent The camera of mobile phone, the pixel of display screen and frame frequency are continuously increased, and original D-PHY, M-PHY interface is gradually difficult to meet data The demand quickly transmitted, C-PHY are a kind of new MIPI interfaces, and signal transmission form is different from D-PHY and M-PHY every logical Road uses 2 signal generating circuits, and the every channel C-PHY uses three signal generating circuits, and in high speed mode, C-PHY connects Mouth output high speed signal, and C-PHY interface output state includes six kinds, wherein each output state is sent out by three signals Three different high speed signal level compositions that raw circuit exports respectively, the transmission mode transmitted by three lines, C-PHY interface More data volumes can be sent in the same time, i.e., can support higher compared to existing D-PHY and M-PHY, C-PHY Transmission rate.

From the above mentioned, C-PHY interface transmission high speed signal needs the output end output of each signal generating circuit to meet C- High speed signal as defined in PHY specification protocol can export the generation circuit of high speed signal as defined in meeting at present and connect to signal output Mouthful requirement it is relatively high, generally require specific signal output interface and could export to meet defined high speed signal.

Utility model content

In view of this, the present invention provides a kind of C-PHY signal generation apparatus, are connect using the general output of FPGA Mouthful, it obtains meeting signal as defined in C-PHY specification protocol.

To achieve the above object, the utility model provides the following technical solutions:

A kind of signal generation apparatus, comprising:

FPGA field programmable gate array, the FPGA include high speed signal output interface set, and the high speed signal is defeated Outgoing interface set includes at least one high speed signal output interface, each high speed signal output interface exports high speed signal；

First level shifting circuit, the input terminal of first level shifting circuit and the high speed signal output interface collection It closes and is connected, the output end output level of first level shifting circuit belongs to the high speed signal of the first default amplitude range；

Wherein, the high speed signal that first level shifting circuit can be inputted that termination receives is converted into level and belongs to The high speed signal of the first default amplitude range.

Preferably, the high speed signal output interface set includes the first high speed signal output interface and the second high speed signal Output interface；

The input terminal of first level shifting circuit respectively with the first high speed signal output interface and second high speed Signal output interface is connected.

Preferably, first level shifting circuit includes:

First resistor, the first end of the first resistor are connected with the first high speed signal output interface, and described first The second end of resistance is connected with the first end of the first end of second resistance, the first end of 3rd resistor and the 4th resistance respectively；

The second resistance, the second end of the second resistance are connected with the second high speed signal output interface；

The 3rd resistor, the second end of the 3rd resistor are connected with the anode of power supply；

The second end of 4th resistance, the 4th resistance is connected with the first end of the 5th resistance, the 4th resistance Second end be first level shifting circuit output end；

The second end of 5th resistance, the 5th resistance is connected with the cathode of the power supply.

Preferably, in the first high speed signal output interface and the second high speed signal output interface, a high speed Signal output interface output has the high speed signal of the first level, and a high speed signal output interface output has second electrical level High speed signal, first level are higher than the second electrical level；

Or,

The first high speed signal output interface and the second high speed signal output interface, which export, has described first The high speed signal of level, or, high speed signal of the output with the second electrical level.

Preferably, a kind of signal generation apparatus further includes three signal generating circuits, and each signal generating circuit is extremely It less include: first level shifting circuit；

The FPGA further includes two high speed signal output interface set；

Wherein, the input terminal of first level shifting circuit in each signal generating circuit and a high speed are believed Number output interface set is connected；Input terminal and the different institutes of first level shifting circuit in circuit occur for unlike signal High speed signal output interface set is stated to be connected.

Wherein, the FPGA further include:

Low speed signal output interface, the low speed signal output interface export low speed signal；

Second electrical level conversion circuit, the second electrical level conversion circuit input terminal and the low speed signal output interface phase Even, the level of the output end output of the second electrical level conversion circuit belongs to the low speed signal of the second default amplitude range；

Wherein, the low speed signal that the second electrical level conversion circuit can be inputted that termination receives is converted into level and belongs to The low speed signal of the second default amplitude range.

Preferably, a kind of signal generation apparatus further include:

High low speed switching switch, the first input end and first level shifting circuit of the high low speed switching switch Output end is connected, and the second input terminal of the high low speed switching switch is connected with the output end of the second electrical level conversion circuit； The control terminal input of the high low speed switching switch has control signal；

It is pre- that the output end output level that the control signal can control the high low speed switching switch belongs to described second If the low speed signal or level of amplitude range belong to the high speed signal of the first default amplitude range.

Preferably, the FPGA further include:

Signal output interface is controlled, the control signal can be exported.

Preferably, the FPGA further include:

Three low speed signal output interfaces, each low speed signal output interface export low speed signal；

Each signal generating circuit includes: second electrical level conversion circuit, the second electrical level conversion circuit input terminal and one A low speed signal output interface is connected, and it is default that the level of the output end output of the second electrical level conversion circuit belongs to second The low speed signal of amplitude range；

Wherein, different second electrical level conversion circuits are connected from different low speed signal output interfaces, each second electricity Flat conversion circuit, which can be inputted the low speed signal that receives of termination and be converted into level, belongs to the described second default amplitude range Low speed signal.

Preferably, each signal generating circuit further include:

Letter belonging to high low speed switching switch, the first input end of the high low speed switching switch and the high low speed switching switch The output end that first level shifting circuit in circuit number occurs is connected, the second input terminal of the high low speed switching switch The output end of the second electrical level conversion circuit in signal generating circuit belonging to switching with the high low speed switching is connected；The height The control terminal input of low speed switching switch has control signal；

It is pre- that the output end output level that the control signal can control the high low speed switching switch belongs to described second If the low speed signal or level of amplitude range belong to the high speed signal of the first default amplitude range.

It can be seen via above technical scheme that the utility model embodiment provides a kind of signal generation apparatus, including FPGA field programmable gate array and the first level shifting circuit, the FPGA includes high speed signal output interface set, described High speed signal output interface set includes at least one high speed signal output interface, and the output of each high speed signal output interface is high Fast signal；The input terminal of first level shifting circuit is connected with the high speed signal output interface set, first electricity The output end output level of flat conversion circuit belongs to the high speed signal of the first default amplitude range；Wherein, first level turns It changes circuit and can be inputted the high speed signal that receives of termination and be converted into the high speed that level belongs to the described first default amplitude range Signal, it is to be understood that when the first default amplitude range be C-PHY specification protocol as defined in high speed signal level range when, The high speed signal for the different types of high speed signal output interface output that FPGA includes can be by first level conversion Circuit conversion obtains meeting high speed signal as defined in C-PHY specification protocol, therefore, reduce to FPGA signal output interface type or The limitation of FPGA signal output interface output signal level amplitude selection, increases the versatility of signal generation apparatus.

Further, it can be seen via above technical scheme that compared with prior art, provided by the embodiment of the utility model one Kind signal generation apparatus, FPGA pin needed for output belongs to the high speed signal of the first default amplitude range is significantly less, reduces Cost.

Detailed description of the invention

In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only It is the embodiments of the present invention, for those of ordinary skill in the art, without creative efforts, also Other attached drawings can be obtained according to the attached drawing of offer.

Fig. 1 illustrates C-PHY output state schematic diagram；

Fig. 2 is a kind of signal generation apparatus structure chart provided by the utility model；

Fig. 3 illustrates a kind of signal generation apparatus structure chart including two high speed signal output interfaces；

Fig. 4 illustrates a kind of signal generation apparatus structure chart including three signal generating circuit output high speed signals；

Fig. 5 illustrates a kind of signal generation apparatus structure chart that can export low speed signal；

A kind of level translator low speed signal level conversion process schematic of Fig. 6 example；

Fig. 7 illustrates a kind of signal generation apparatus structure including three signal generating circuits and high low speed change-over switch Figure.

Specific embodiment

For the sake of quoting and understanding, hereafter used in technical term explanation, write a Chinese character in simplified form or abridge and be summarized as follows:

MIPI:Mobile Industry Processor Interface, Mobile Industry Processor Interface are a kind of shiftings Dynamic communications industry equipment interior video data transmission interface standard；

PHY:Port Physical Layer, port physical layer are a common abbreviations to osi model physical layer；

A kind of physical interface standards of C-PHY:MIPI, every paths use 3 transmission lines；

A kind of physical interface standards of D-PHY, M-PHY:MIPI, every paths use 2 transmission lines；

LP:Low-Power, low speed；

HS:High-Speed, high speed；

FPGA:Field-Programmable Gate Array, field programmable gate array, as specific integrated circuit One of field semi-custom circuit and occur, not only solved the deficiency of custom circuit, but also overcome original programming device The limited disadvantage of gate circuit number.

The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work Every other embodiment obtained, fall within the protection scope of the utility model.

With the update and development of smart machine, the especially camera of smart machine such as smart phone or display screen image The increase of element or frame frequency, original MIPI physical layer interface are passed as the message transmission rate of D-PHY, M-PHY are unable to satisfy data Defeated needs, and newest MIPI physical layer interface C-PHY carries out the high-speed transfer of data using the transmission mode that three lines transmit, greatly Transmission rate is improved greatly.

Specifically, every channel of C-PHY interface use three signal generating circuits, be defined as Lane A, Lane B and Lane C, and the signal transmission of C-PHY interface can be divided into high-speed mode or low-speed mode.

Wherein, the higher signal of transmission speed under high-speed mode, such as high-speed video data, usual data transmission bauds are big In 80MS/s, each signal generating circuit can be belonged in level range as defined in C-PHY specification protocol at this time with output level High speed signal, and the level of three signal generating circuits output high speed signals is different, is expressed as VA, VB and VC, generally In the case of by three signal generating circuit output levels be divided into high (height), middle (in), low (low), pass through three signals The different high speed signal level of generation circuit output, available six kinds of C-PHY output states, respectively+X ,+Y ,+Z ,-X ,- Y ,-Z, C-PHY signal receiving end identifies the variable condition of data by detecting the change of above-mentioned output state, for the ease of reason Solution, is illustrated above-mentioned six kinds of output states in conjunction with attached drawing 1, as shown in FIG. 1, FIG. 1 is C-PHY output state schematic diagrames, it may be assumed that

Work as VA > VC > VB, C-PHY interface output state is+X；

Work as VB > VA > VC, C-PHY interface output state is+Y；

Work as VC > VB > VA, C-PHY interface output state is+Z；

Work as VB > VC > VA, C-PHY interface output state is-X；

Work as VC > VA > VB, C-PHY interface output state is-Y；

Work as VA > VB > VC, C-PHY interface output state is-Z.

It should be noted that VA, VB and VC are the level in high speed signal level range as defined in C-PHY specification protocol, As long as in this level range and meeting above-mentioned level relationship, so that it may obtain corresponding C-PHY output state.In general, Ideally, high speed signal fiduciary level as defined in C-PHY specification protocol is high=300mV, middle=200mV, low =100mV.

Next, introducing a kind of signal generation apparatus provided by the embodiment of the utility model in conjunction with attached drawing 2, Fig. 2 is this reality It may include: that FPGA field programmable gate array and the first level turn with a kind of signal generation apparatus structure chart of novel offer Change circuit.

Wherein, FPGA includes high speed signal output interface set, and high speed signal output interface set includes at least one height Fast signal output interface, each high speed signal output interface export high speed signal, wherein each high speed signal output interface It can be the available any type of high speed single-ended signal output interface of FPGA, such as LVTTL (Low Voltage Transistor-Transistor Logic), LVCMOS (Low Voltage Complementary Metal Oxide Semiconductor) the types such as circuit or SSTL (Stub Series Terminated Logic), it is to be understood that appoint The high speed single-ended signal output interface of meaning type can export high speed signal, different types of high speed single-ended signal output interface The high speed signal level that can be exported is different.

Wherein, the input terminal of the first level shifting circuit is connected with high speed signal output interface set, the first level conversion The output end output level of circuit belongs to the high speed signal of the first default amplitude range；Wherein, the first level shifting circuit can It is inputted the high speed signal that termination receives and is converted into the high speed signal that level belongs to the first default amplitude range.

Wherein, the high speed signal that the first level shifting circuit input terminal receives is the output of high speed signal output interface set High speed signal, it is to be understood that the high speed signal level magnitude of different types of high speed signal output interface output is different, First level shifting circuit output end, which exports the first default amplitude range belonging to high speed signal level, to be C-PHY specification association High speed signal level range as defined in discussing, further, the first level shifting circuit can be inputted the high speed letter that termination receives Number being converted into level meets high speed signal as defined in C-PHY specification protocol.

It can be seen via above technical scheme that the utility model embodiment provides a kind of signal generation apparatus, including FPGA field programmable gate array and the first level shifting circuit, the FPGA includes high speed signal output interface set, described High speed signal output interface set includes at least one high speed signal output interface, and the output of each high speed signal output interface is high Fast signal；The input terminal of first level shifting circuit is connected with the high speed signal output interface set, first electricity The output end output level of flat conversion circuit belongs to the high speed signal of the first default amplitude range；Wherein, first level turns It changes circuit and can be inputted the high speed signal that receives of termination and be converted into the high speed that level belongs to the described first default amplitude range Signal, it is to be understood that when the first default amplitude range be C-PHY specification protocol as defined in high speed signal level range when, The high speed signal for the different types of high speed signal output interface output that FPGA includes can be by first level conversion Circuit conversion obtains meeting high speed signal as defined in C-PHY specification protocol, therefore, reduce to FPGA signal output interface type or The limitation of FPGA signal output interface output signal level amplitude selection, increases the versatility of signal generation apparatus.

Further, it can be seen via above technical scheme that compared with prior art, provided by the embodiment of the utility model one Kind signal generation apparatus, FPGA pin needed for output belongs to the high speed signal of the first default amplitude range is significantly less, reduces Cost.

Next, being further described a kind of signal generation apparatus provided by the embodiment of the utility model in conjunction with attached drawing 3, such as scheme Shown in 3, the high speed signal output interface set may include the first high speed signal output interface and the output of the second high speed signal Interface；The input terminal of first level shifting circuit respectively with the first high speed signal output interface and the second high speed signal Output interface is connected.

Wherein, the first level shifting circuit may include: first resistor, second resistance, 3rd resistor, the 4th resistance and Five resistance, as shown in figure 3, above-mentioned resistance is indicated with R1, R2, R3, R4 and R5 respectively, next to the connection type of each resistance It is introduced:

The first end of first resistor R1 is connected with the first high speed signal output interface, the second end of first resistor R1 respectively with The first end of the first end of second resistance R2, the first end of 3rd resistor R3 and the 4th resistance R4 is connected；Second resistance R2's Second end is connected with the second high speed signal output interface；The second end of 3rd resistor R3 is connected with the anode of power supply；4th resistance The second end of R4 is connected with the first end of the 5th resistance R5, and the second end of the 4th resistance R4 is the output of the first level shifting circuit End；The second end of 5th resistance R5 is connected with the cathode of power supply.

Wherein, above-mentioned each resistance can be pure resistance, or the equivalent electricity that multiple resistance are connected in series or in parallel Resistance.

It should be noted that power supply may include built-in power or external power supply, it can be the first level shifting circuit Input voltage is provided.

Wherein, the first high speed signal output interface and the second high speed signal output interface can export high speed signal, and It can be the available any type of high speed single-ended signal output interface of FPGA, the first high speed signal output interface and second high The high speed signal of fast signal output interface output can be the first level or second electrical level, it is assumed that the first level is higher than the second electricity It is flat, several different situations can be had according to output level difference, can specifically include:

The first, in the first high speed signal output interface and the second high speed signal output interface, a high speed signal output Interface output has the high speed signal of the first level, and there is the output of another high speed signal output interface the high speed of second electrical level to believe Number.

Second, the first high speed signal output interface and the second high speed signal output interface are exported with the first level High speed signal.

The third, the first high speed signal output interface and the second high speed signal output interface are exported with second electricity Flat high speed signal.

It is carried out in conjunction with output end output high speed signal level of the example to the first level shifting circuit in the case of above-mentioned three kinds It introduces, as shown in figure 3, the first high speed signal output interface and the second high speed signal output interface are expressed as HS-A1 and HS- A2；Wherein, HS-A1 output high speed signal can be the first level A1-VDD or second electrical level A1-VSS, and HS-A2 output High speed signal may be the first level A2-VDD or second electrical level A2-VSS.

It should be noted that the first level magnitude of different types of high speed signal output interface output high speed signal is not Together, for example, LVTTL output interface output high speed signal the first level magnitude according to level standard difference can for 3.3V, 2.5V or lower；Based on this, signal generation apparatus provided in this embodiment is with the first high speed signal output interface and the second high speed For signal output interface to be introduced for same type of high speed single-ended signal output interface, i.e. hypothesis A1-VDD is equal to A2- VDD is expressed as A_VDD, and A1-VSS is equal to A2-VSS, is expressed as A_VSS.

The resistance value size relation for each resistance that the first level shifting circuit includes under optionally a kind of embodiment can With are as follows: R1=R2=R3=R4+R5；Supply voltage can be A_VDD.

Optionally, the output end output level of level shifting circuit can specifically include in the case of above-mentioned three kinds::

The first, HS-A1 exports the first level A_VDD and HS-A2 and exports second electrical level A_VSS, or, HS-A1 output the Two level A_VSS, and HS-A2 exports the first level A_VDD, the then resistance for each resistance for including according to the first level shifting circuit Be worth size relation, the output end output level of available first level shifting circuit be middle (in):

Second, HS-A1 and HS-A2 export the first level A_VDD simultaneously, then include according to the first level shifting circuit The output end output level of the resistance value size relation of each resistance, available first level shifting circuit is high (height):

The third, HS-A1 and HS-A2 export second electrical level A_VSS simultaneously, then include according to the first level shifting circuit The output end output level of the resistance value size relation of each resistance, available first level shifting circuit is low (low):

Based on this, the level of the high speed signal of the output end output of the first level shifting circuit can be above-mentioned three kinds of situations Under any level.

Further, when the range that the first default amplitude range is high speed signal output level as defined in C-PHY specification protocol When, R5 and R4 can be selected according to A_VDD size, guarantee that the first level shifting circuit can be inputted the high speed that termination receives Signal is converted into the high speed signal that level meets C-PHY specification protocol prescribed limit.

For example, as A_VDD=1.2V, R4:R5=2:1, at this point, above-mentioned three kinds of output levels are C-PHY specification protocol Defined fiduciary level, i.e. high=300mV, middle=200mV, low=100mV；

Or as A_VDD=1.8V, R4:R5=7:2, at this point, above-mentioned three kinds of output levels are C-PHY specification protocol rule Fixed fiduciary level, i.e. high=300mV, middle=200mV, low=100mV.

It should be noted that high, middle and low can be any level of C-PHY specification protocol prescribed limit.

It is aforementioned it is found that in three line transmission mode of C-PHY signal, using three bars electricity occurs for the every paths of C-PHY interface Road is based on this, proposes that a kind of signal generation apparatus provided by the utility model is introduced in another optional embodiment, specifically It may include three signal generating circuits, each signal generating circuit includes at least the first level shifting circuit；Optionally, FPGA It further include two high speed signal output interface set.

As shown in figure 4, the input terminal of the first level shifting circuit in each signal generating circuit and a high speed signal Output interface set is connected；Input terminal and the different high speeds of the first level shifting circuit in circuit occur for unlike signal Signal output interface set is connected.

As can be seen from the above embodiments, each high speed signal output interface set may include the first high speed signal output interface With the second high speed signal output interface, and, the first high speed signal output interface that each high speed signal output interface set includes It may include three kinds of situations of above-described embodiment introduction, base with the high speed signal level of the second high speed signal output interface output In this, three signal generating circuits can distinguish the different high speed signal of output level, thus, it is possible to which it is defeated to obtain six kinds of C-PHY It does well, respectively+X ,+Y ,+Z ,-X ,-Y ,-Z.

Next C-PHY output state is illustrated so that output state is "-Z " as an example in conjunction with attached drawing 4.

As shown in figure 4, three signal generating circuits are expressed as Lane A, Lane B and Lane C, wherein Mei Yixin Number circuit occurs and includes to include first level shifting circuit, the first level shifting circuit that Lane A includes is respectively with the One high speed signal output interface HS-A1 and the second high speed signal output interface HS-A2 is connected；The first level that Lane B includes turns Circuit is changed to be connected with the first high speed signal output interface HS-B1 and the second high speed signal output interface HS-B2 respectively；Lane C packet The first level shifting circuit included respectively with the first high speed signal output interface HS-C1 and the second high speed signal output interface HS- C2 is connected.

When output state is "-Z ", optional a kind of implementation are as follows: R1=R2=R3=R4+R5, all high speed letters Number output interface output the first level of high speed signal is VDD, second electrical level VSS, supply voltage VDD.

At this point, HS-A1 and HS-A2 simultaneously export the first level VDD, then according to the first level shifting circuit include it is each The resistance value size relation of resistance, the output end output level VA of the first level shifting circuit in available Lane A are as follows:

Assuming that VDD=1.8V, and R4:R5=7:2, then VA=300mV.

HS-B1 exports the first level VDD and HS-B2 exports second electrical level VSS, or, HS-B1 exports second electrical level VSS, HS-B2 exports the first level VDD, then the resistance value size relation for each resistance for including according to the first level shifting circuit can be with Obtain the output end output level VB of the first level shifting circuit in Lane B are as follows:

Assuming that VDD=1.8V, and R4:R5=7:2, then VB=200mV.

HS-C1 and HS-C2 exports second electrical level VSS simultaneously, then each resistance for including according to the first level shifting circuit Resistance value size relation, the output end output level VC of the first level shifting circuit in available Lane C are as follows:

Assuming that VDD=1.8V, and R4:R5=7:2, then VC=100mV.

Obviously, VA > VB > VC, and VA, VB and VC the high-speed level as defined in C-PHY agreement within the scope of, then C-PHY High speed transmission of signals state is-Z, it is to be understood that when high speed signal output interface output level changes, VA, VB It can occur to change accordingly with VC size relation, obtain other five kinds of transmission states, specifically can refer to above-mentioned output state is Implementation when "-Z ", this embodiment is not repeated.

It should be noted that can choose different R4 and R5 when VDD is other optional first level, obtaining level Meet high speed signal as defined in C-PHY agreement.

It should be noted that signal generation apparatus provided in this embodiment, is usually connected with C-PHY signal receiving end, generally , there is terminating resistor RL inside signal receiving end in high speed mode, VA, VB and VC that above-described embodiment refers to are in receiving end There are in the case where terminating resistor RL, level can change, such as above-mentioned VA can be declined under the influence of RL；On VC is stated under the influence of RL, can be increased, above-mentioned VB does not change generally under the influence of RL；By being adjusted in synchronism the The size or proportionate relationship of each resistance value in one level shifting circuit can make to obtain in the case where connecting terminating resistor RL Meet high speed signal as defined in C-PHY agreement to level, under normal circumstances, R1=R2=R3=R4+R5=k*RL can be enabled, wherein K is empirical value, generally can be between value 1.5~2.0, it is possible thereby to obtain higher output broadband.

As can be seen from the above-described embodiment, the present embodiment, which can not only export, meets high-speed level as defined in C-PHY agreement Within the scope of high speed signal, in addition, a kind of signal generation apparatus provided by the utility model include the first level conversion electricity Road only includes resistive element, and connection type is simple, greatlys save cost, and when in use, only need to change resistance can will not Level, which is converted to, with the high speed signal that high speed signal output interface exports meets defined high speed signal.

In addition, C-PHY interface can also include low-speed mode, the lower signal of transmission speed under low-speed mode, in general, Low speed signal speed be less than 10Mbps, for transmit status information or control signal, for example, transmitting cell-phone display screen lighten or Control instruction information is dimmed, system power dissipation can be reduced by transmitting such control instruction information by low-speed mode, in low-speed mode Lower low speed signal can be full swing signal independent, it should be noted that C-PHY agreement provides low speed signal level model It is trapped among between 0.95V~1.3V, but ideally, low speed signal fiduciary level is 1.2V.

Based on this, the present apparatus can also include: low speed signal output interface and second electrical level conversion circuit, and second electrical level turns Circuit input end is changed to be connected with low speed signal output interface.

Wherein, low speed signal output interface can connect for the available any type of speed/low speed single end signal 0 number output of FPGA Mouthful, such as the types such as LVTTL, LVCMOS circuit or SSTL, it is to be understood that any type of speed/low speed single end signal 0 number output connects Mouth can export low speed signal, and it is different that different type speed/low speed single end signal 0 output interface exports low speed signal level.

Wherein, the output end output level of second electrical level conversion circuit belongs to the low speed signal of the second default amplitude range； The second electrical level conversion circuit can be inputted the low speed signal that receives of termination and be converted into level to belong to described second default The low speed signal of amplitude range.

It is understood that the low speed signal level of different types of low speed signal output interface output is different, the second electricity Flat turn is changed the second default amplitude range belonging to circuit output end output low speed signal level and can be provided for C-PHY specification protocol Low speed signal level range, further, second electrical level conversion circuit can be inputted termination receive low speed signal conversion Meet low speed signal as defined in C-PHY specification protocol at level.

It should be noted that second electrical level conversion circuit can be for bleeder circuit or level conversion device, function The low speed signal that input terminal is received is converted into level and meets low speed signal as defined in C-PHY specification protocol, physical circuit shape Formula or the level conversion device model prior art, the present embodiment does not limit.

The utility model embodiment is introduced in conjunction with attached drawing 5, as shown in figure 5, low speed signal output interface is expressed as LP-A, wherein LP-A can be the low speed signal of VCC with output level, and optionally, second electrical level conversion circuit is level translator Part, for example, a kind of optional level conversion device is that 8 channel bi-directional logic level translator TXB0108, TXB0108 are being transmitted The level change of low speed signal is as shown in Figure 6 when low speed signal, that is, the level that TXB0108 input terminal receives LP-A output is VCC Low speed signal, output end output level belongs to the low speed signal of the second default amplitude range, for example, when the second default amplitude model It encloses for that when low speed signal level range, can be belonged to as defined in C-PHY specification protocol with output level as defined in C-PHY specification protocol The low speed signal of low speed signal level range optionally can be using output level as the low speed signal of fiduciary level 1.2V.

Based on the above embodiment, as shown in figure 5, the present apparatus can also include high low speed switching switch.

Wherein, the first input end of high low speed switching switch is connected with the output end of the first level shifting circuit, high low speed Second input terminal of switching switch is connected with the output end of second electrical level conversion circuit；The control terminal input of high low speed switching switch There is control signal.

Wherein, control signal can control the output end output of high low speed switching switch:

The level of the output end output of second electrical level conversion circuit belongs to the low speed signal of the second default amplitude range；

Or,

The level of the output end output of first level shifting circuit belongs to the high speed signal of the first default amplitude range.

It is understood that high low speed switching switch includes the electronic device that can control high low speed signal switching, control Signal processed can be the control signal that device itself generates, or control signal can be issued for other control systems, optionally A kind of high low speed switching switch is ADG918, and ADG918 is a absorption switch that there is 50 Ω termination to shunt pin, work Making principle is the prior art, and the present embodiment does not repeat them here.

A kind of optional control signal is described below:

As shown in figure 5, the FPGA of the present apparatus can also include: control signal output interface, control signal can be exported, is controlled Signal output interface processed can be the available single-ended signal output interface of FPGA, generally can choose the output of high speed single-ended signal Interface indicates with HS-EN, the different signal of the exportable level of HS-EN, and the level of output signal may include high level or low Level, the signal can be high speed signal, and optionally, when controlling signal output interface output high level, high low speed switching is opened Output high speed signal is closed, when controlling signal output interface output low level, high low speed switching switch output low speed signal is based on This, realizes high low speed signal switching.

It is aforementioned it is found that in three line transmission mode of C-PHY signal, using three signals electricity occurs for the every paths of C-PHY interface Road is based on this, and referring to attached drawing 7, a kind of signal generation apparatus provided by the utility model is introduced.Specifically, further includes: Three low speed signal output interfaces, wherein each low speed signal output interface exports low speed signal.

Optionally, each signal generating circuit further include: second electrical level conversion circuit,

Wherein, second electrical level conversion circuit input terminal is connected with a low speed signal output interface, second electrical level conversion electricity The output end output level on road belongs to the low speed signal of the second default amplitude range；Wherein, different second electrical level conversion circuits with Different low speed signal output interfaces is connected, and each second electrical level conversion circuit can be inputted the low speed signal that termination receives It is converted into the low speed signal that level belongs to the second default amplitude range.

As shown in fig. 7, three signal generating circuits are denoted as Lane A, Lane B and Lane C respectively, wherein three low speed Signal output interface is respectively speed/low speed single end signal 0 output interface LP-A, LP-B and LP-C, after each low speed signal output interface Connect a second electrical level conversion circuit, it should be noted that three second electrical level conversion circuits are identical under normal circumstances, special , it can choose different second electrical level conversion circuits.

Optionally, each signal generating circuit further includes high low speed switching switch.

Wherein, the first input end of high low speed switching switch and the high low speed switch in signal generating circuit belonging to switch The output end of first level shifting circuit is connected, belonging to the second input terminal of high low speed switching switch and the high low speed switching switch The output end of second electrical level conversion circuit in signal generating circuit is connected.

As shown in fig. 7, the first input end and the first level in Lane A of the high low speed switching switch in Lane A turn The output end for changing circuit is connected, and the second input terminal that high low speed switching switchs is defeated with the second electrical level conversion circuit in Lane A Outlet is connected；The first input end of high low speed switching switch in Lane B is defeated with the first level shifting circuit in Lane B Outlet is connected, and the second input terminal of high low speed switching switch is connected with the output end of the second electrical level conversion circuit in Lane B； The first input end of high low speed switching switch in Lane C is connected with the output end of the first level shifting circuit in Lane C, Second input terminal of high low speed switching switch is connected with the output end of the second electrical level conversion circuit in Lane C.

Optionally, the control terminal input of each high low speed switching switch has control signal, wherein control signal can control The output end output of high low speed switching switch in each signal generating circuit:

The level of the output end output of second electrical level conversion circuit belongs to the low speed signal of the second default amplitude range；

Or,

The level of the output end output of first level shifting circuit belongs to the high speed signal of the first default amplitude range.

Optionally, the sending mode of the control signal of high low speed switching switch can be identical in each signal generating circuit Can be different, a kind of control signal generation apparatus shown in Fig. 7.

Specifically, it can also include: control signal output interface, control signal can be exported, control signal output interface It can be the available any type of single-ended signal output interface of FPGA.In general, can choose the output of high speed single-ended signal Interface indicates that HS-EN can be defined as high level or low level, then the control with output level height unlike signal with HS-EN Signal can be high speed signal.

Optionally, when HS-EN exports high level, the high low speed of control signal control Lane A, Lane B and Lane C The level for the output end output that the output end for switching switch exports second electrical level conversion circuit simultaneously belongs to the second default amplitude model The low speed signal enclosed, the second default amplitude range can be low speed signal level range as defined in C-PHY interface protocol；

Or, when HS-EN exports high level, the high low speed switching of control signal control Lane A, Lane B and Lane C The level that switch while the output end for exporting the first level shifting circuit export belongs to the high speed signal of the first default amplitude range, The first default amplitude range can be high speed signal level range as defined in C-PHY interface protocol.

It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment weight Point explanation is the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

The foregoing description of the disclosed embodiments can be realized professional and technical personnel in the field or using originally practical new Type.Various modifications to these embodiments will be readily apparent to those skilled in the art, and determine herein The General Principle of justice can be realized in other embodiments without departing from the spirit or scope of the present utility model.Cause This, the present invention will not be limited to the embodiments shown herein, and is to fit to and principles disclosed herein The widest scope consistent with features of novelty.

Claims (10)

1. a kind of signal generation apparatus characterized by comprising

FPGA field programmable gate array, the FPGA include high speed signal output interface set, and the high speed signal output connects Mouth set includes at least one high speed signal output interface, each high speed signal output interface exports high speed signal；

First level shifting circuit, the input terminal of first level shifting circuit and the high speed signal output interface set phase Even, the output end output level of first level shifting circuit belongs to the high speed signal of the first default amplitude range；

Wherein, first level shifting circuit can be inputted the high speed signal that receives of termination be converted into level belong to it is described The high speed signal of first default amplitude range.

2. signal generation apparatus according to claim 1, which is characterized in that the high speed signal output interface set includes First high speed signal output interface and the second high speed signal output interface；

The input terminal of first level shifting circuit respectively with the first high speed signal output interface and the second high speed signal Output interface is connected.

3. signal generation apparatus according to claim 2, which is characterized in that first level shifting circuit includes:

First resistor, the first end of the first resistor are connected with the first high speed signal output interface, the first resistor Second end be connected respectively with the first end of the first end of second resistance, the first end of 3rd resistor and the 4th resistance；

The second resistance, the second end of the second resistance are connected with the second high speed signal output interface；

The 3rd resistor, the second end of the 3rd resistor are connected with the anode of power supply；

The second end of 4th resistance, the 4th resistance is connected with the first end of the 5th resistance, and the of the 4th resistance Two ends are the output end of first level shifting circuit；

The second end of 5th resistance, the 5th resistance is connected with the cathode of the power supply.

4. signal generation apparatus according to claim 3, which is characterized in that the first high speed signal output interface and institute It states in the second high speed signal output interface, a high speed signal of the high speed signal output interface output with the first level, one The output of high speed signal output interface has the high speed signal of second electrical level, and first level is higher than the second electrical level；

Or,

The first high speed signal output interface and the second high speed signal output interface, which export, has first level High speed signal, or, output have the second electrical level high speed signal.

5. signal generation apparatus according to claim 4, which is characterized in that including three signal generating circuits, each signal Circuit occurs to include at least: first level shifting circuit；

The FPGA further includes two high speed signal output interface set；

Wherein, the input terminal of first level shifting circuit in each signal generating circuit and a high speed signal are defeated Outgoing interface set is connected；Input terminal and the different height of first level shifting circuit in circuit occur for unlike signal Fast signal output interface set is connected.

6. signal generation apparatus according to claim 4, which is characterized in that the FPGA further include:

Low speed signal output interface, the low speed signal output interface export low speed signal；

Second electrical level conversion circuit, the second electrical level conversion circuit input terminal are connected with the low speed signal output interface, institute The level for stating the output end output of second electrical level conversion circuit belongs to the low speed signal of the second default amplitude range；

Wherein, the second electrical level conversion circuit can be inputted the low speed signal that receives of termination be converted into level belong to it is described The low speed signal of second default amplitude range.

7. signal generation apparatus according to claim 6, which is characterized in that further include:

High low speed switching switch, the output of the first input end and first level shifting circuit of the high low speed switching switch End is connected, and the second input terminal of the high low speed switching switch is connected with the output end of the second electrical level conversion circuit；It is described The control terminal input of high low speed switching switch has control signal；

The output end output level that the control signal can control the high low speed switching switch belongs to the described second default width The low speed signal or level of value range belong to the high speed signal of the first default amplitude range.

8. signal generation apparatus according to claim 7, which is characterized in that the FPGA further include:

Signal output interface is controlled, the control signal can be exported.

9. signal generation apparatus according to claim 5, which is characterized in that the FPGA further include:

Three low speed signal output interfaces, each low speed signal output interface export low speed signal；

Each signal generating circuit further include: second electrical level conversion circuit, the second electrical level conversion circuit input terminal with One low speed signal output interface is connected, and it is pre- that the level of the output end output of the second electrical level conversion circuit belongs to second If the low speed signal of amplitude range；

Wherein, different second electrical level conversion circuits are connected from different low speed signal output interfaces, and each second electrical level turns It changes circuit and can be inputted the low speed signal that receives of termination and be converted into the low speed that level belongs to the described second default amplitude range Signal.

10. signal generation apparatus according to claim 9, which is characterized in that each signal generating circuit further include:

High low speed switching switch, the high low speed switches the first input end of switch and the high low speed switching switchs affiliated signal and sends out The output end of first level shifting circuit in raw circuit is connected, and the high low speed switches the second input terminal switched and should The output end that high low speed switching switchs the second electrical level conversion circuit in affiliated signal generating circuit is connected；The high low speed The control terminal input of switching switch has control signal；

The output end output level that the control signal can control the high low speed switching switch belongs to the described second default width The low speed signal or level of value range belong to the high speed signal of the first default amplitude range.