CN209134375U - A kind of reset circuit for opening/closing - Google Patents
A kind of reset circuit for opening/closing Download PDFInfo
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- CN209134375U CN209134375U CN201920007854.0U CN201920007854U CN209134375U CN 209134375 U CN209134375 U CN 209134375U CN 201920007854 U CN201920007854 U CN 201920007854U CN 209134375 U CN209134375 U CN 209134375U
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Abstract
The utility model discloses a kind of reset circuit for opening/closing, including master chip, power circuit, reset circuit, key press detecting circuit and reset latching circuit, power circuit is master chip power supply, power supply enable signal end is wherein connect by key with cell voltage output end all the way, second tunnel is connect with the output end for resetting latching circuit, the connection of the power control terminal of third road and master chip, key press detecting circuit is respectively sent to reset circuit and master chip for generating key detection signal, reset circuit generates reset signal and is exported by reset signal output end, reset signal output end is wherein connect with the input terminal for resetting latching circuit all the way, in addition it is connect all the way with master chip.The reset circuit for opening/closing of the utility model realizes booting, shutdown and reset function by using the control of a key different conditions.Shutdown caused by latching circuit avoids device hardware from resetting is resetted by setting, circuit is few using component, reduces cost and reduces the occupancy to circuit board space.
Description
Technical field
The utility model relates to a kind of reset circuit for opening/closing, specifically, be related to one kind being capable of control switch machine, multiple
The control circuit of position.
Background technique
With the development of science and technology, wearing product continues to increasingly infuse toward miniaturization, multifunction development and people
Weight Product Experience.For dress product design in order to enhance the performance of product and the operation of simplification, switching on and shutting down and reset are pressed
The design of key reduces to the greatest extent and to accurately control the operating time of switching on and shutting down and reset key to enhance user experience.Existing
Technology in, the individually designed key of reset key, so not only increase cost and reduce hardware PCB design space, to
Family use is also very inconvenient.Switch key and reset key are used into the same key there are also some, pressed the button by timing
Duration judgement is switching on and shutting down operation or resets operation, since user controls the time pressed the button not so good, different product
Diversity ratio is larger, be easy to cause the maloperation of user in this way and seriously affects user experience.
Summary of the invention
The utility model in order to solve it is existing use same key control switch machine and reset, user to press the button when
Between be not easy the technical issues of controlling, being easy to cause maloperation.
In order to solve the above-mentioned technical problem, the utility model is achieved using following technical scheme:
A kind of reset circuit for opening/closing, including master chip, power circuit, reset circuit, key press detecting circuit and reset
Latching circuit, the power circuit receive the control of the power supply enable signal from power supply enable signal end as master chip confession
Electricity, power supply enable signal end are wherein connect by key with cell voltage output end all the way, and the second tunnel and the reset are certainly
The output end of lock circuit connects, and third road is connect with the power control terminal of the master chip, and the key press detecting circuit is connected to
Between the cell voltage output end and power supply enable signal end, for detecting the down state of the key, and generate
Key detection signal is respectively sent to the reset circuit and master chip, and the reset circuit detects signal according to the key
Duration judges whether to generate reset signal and to be exported by reset signal output end, the reset signal output end wherein one
Road is connect with the input terminal for resetting latching circuit, is in addition connect all the way with the master chip, the master chip is according to
Reset signal is resetted, and the master chip generates power supply control letter according to current on-off state and key detection signal
Number and exported by the power control terminal to power supply enable signal end.
Further, the key press detecting circuit includes a NMOS tube, and the grid of the NMOS tube is wherein connected to all the way
Between the cell voltage output end and power supply enable signal end, in addition it is connect all the way by second resistance with ground terminal, institute
The source electrode for stating NMOS tube is connect with ground terminal, drain electrode for output key detect signal, respectively with the reset circuit and master chip
Connection.
Further, the second diode is provided between the grid of the NMOS tube and power supply enable signal end.
Further, the one or two pole is provided between the power control terminal of the master chip and power supply enable signal end
Pipe.
Further, the reset circuit includes that a reset controls chip, the signal input part for resetting control chip
It is connect with the key press detecting circuit, for receiving key detection signal, the reset control chip is detected according to the key
The duration of signal judges whether to generate reset signal and be exported by reset signal output end.
Further, the reset circuit further includes 3rd resistor and third capacitor, the signal for resetting control chip
Input terminal is connect by 3rd resistor with power end, one end of the third capacitor be connected to the 3rd resistor and power end it
Between, other end connects ground terminal.
Further, the reset latching circuit includes a phase inverter, the input terminal of the phase inverter and reset electricity
The reset signal output end on road connects, and the output end of the phase inverter is connect with power supply enable signal end.
Further, third diode is provided between the output end of the phase inverter and power supply enable signal end.
Further, the front end at power supply enable signal end is additionally provided with accumulator.
Further, the accumulator includes the first capacitor being in parallel and the 4th resistance, the first capacitor and
One end of four resistance is connect with power supply enable signal end respectively, and other end connects ground terminal.
Compared with prior art, the advantages and positive effects of the utility model are as follows: the switching on and shutting down of the utility model reset electricity
Road realizes booting, shutdown and reset function by the control to a key different conditions, simplifies operation complexity.Pass through
Setting resets latching circuit and avoids shutdown caused by device hardware resets, and used component is less, reduces cost and subtracts
The small occupancy to circuit board space is especially suitable for requiring occupied space stringent small-sized wearable device.
After the detailed description of the utility model embodiment is read in conjunction with the figure, other features and advantages of the utility model
It will become clearer.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of embodiment functional-block diagram for the reset circuit for opening/closing that the utility model is proposed；
Fig. 2 is reset circuit in Fig. 1, key press detecting circuit, the schematic diagram for resetting latching circuit and accumulator；
Fig. 3 is the schematic diagram of power circuit and master chip in Fig. 1.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work
Every other embodiment obtained, fall within the protection scope of the utility model.
Embodiment one, the present embodiment propose a kind of reset circuit for opening/closing, as shown in Figure 1, including master chip, power supply electricity
Road, reset circuit, key press detecting circuit and reset latching circuit, power circuit receive the power supply from power supply enable signal end
The control of enable signal is master chip power supply, and power supply enable signal end is wherein connected by key and cell voltage output end all the way
It connects, the second tunnel is connect with the output end for resetting latching circuit, the power control terminal connection of third road and master chip, key detection electricity
Road is connected between cell voltage output end and power supply enable signal end, for detecting the down state of key, and generates key
Detection signal is respectively sent to reset circuit and master chip, and reset circuit judges whether according to the duration that key detects signal
It generates reset signal and is exported by reset signal output end, reset signal output end is wherein defeated with reset latching circuit all the way
Enter end connection, is in addition connect all the way with master chip, master chip is resetted according to reset signal, and master chip is according to current switch
Machine state and key detection signal generate power control signal and are exported by the power control terminal enabled to the power supply
Signal end.The working principle of this reset circuit for opening/closing is: key press detecting circuit is connected to power output end and the enabled letter of power supply
Between number end, the down state of key is detected when for open state, key is pressed when open state, point three kinds of situations, point
It is not key time that is pressed to be pressed the time not less than setting time t1 less than setting time t1, key and be less than setting time
T2, key are pressed the time not less than setting time t2, wherein 0 < t1 < t2.Key press detecting circuit generates after key is pressed
Key detection signal is respectively sent to reset circuit and master chip, and reset circuit and master chip respectively hold key detection signal
The continuous time carries out timing, if key is pressed, the time is less than setting time t1, and reset circuit and master chip are failure to actuate, if key
The time be pressed not less than setting time t1 and is less than setting time t2, then is judged as power-off operation at this time, reset circuit is motionless
Make, master chip by power control terminal output low level to power supply enable signal end, if key is released, cell voltage without
Normal direction power supply enable signal end exports high level, and therefore, the level at power supply enable signal end is pulled low namely power supply enable signal
It is invalid to be set to, since power circuit receives the control of the power supply enable signal from power supply enable signal end, when power supply is enabled
When signal is pulled low, stop powering for master chip, therefore system closedown.If key is pressed, the time is not less than setting time t2,
Reset circuit movement, is resetted to reset latching circuit and master chip output reset signal, master chip respectively, while being resetted certainly
Lock circuit locks reset signal, and to the effective power supply enable signal at power supply enable signal end, controlling power circuit is continuously
Master chip power supply exports control signal by power control terminal, power supply enable signal is locked in holding until master chip is completed to reset
Firmly effective status.If key is pressed when off-mode, cell voltage VBAT(3~4.2V) it is transferred to power supply enable signal
End, such power supply enable signal DCDC_EN are at high level effective status to open power circuit to master chip and power, so
Master chip exports the power control signal CC3200_PWR_CTL of high level to power supply enable signal end by power control terminal afterwards,
To lock the high level state of power supply enable signal DCDC_EN, device power-up is completed in key release.The switch of the present embodiment
Machine reset circuit is realized booting, shutdown and reset function by the control to a key different conditions, is simplified complicated for operation
Degree.Latching circuit is resetted by setting and avoids shutdown caused by device hardware resets, and then can be to avoid user misoperation, this
Component used by circuit is less, reduces cost and reduces the occupancy to circuit board space, is especially suitable for occupancy
The stringent small-sized wearable device of space requirement.
During this period since reset signal CC3200_NRST is in high level, by exporting low level after phase inverter U2,
Diode D3 cut-off resets latching circuit and does not control enable signal DCDC_EN.
It include a NMOS tube Q1, NMOS tube Q1 by detection circuit as shown in Figure 2 and Figure 3 as a preferred embodiment
Grid 1 be wherein connected to all the way between cell voltage output end VBAT and power supply enable signal end DCDC_EN, other a-road-through
It crosses second resistance R2 to connect with ground terminal, the source electrode 3 of NMOS tube Q1 is connect with ground terminal, and drain electrode 2 detects signal for output key
CC3200_DETECT is connect with reset circuit and master chip respectively.After key BT1 is pressed, cell voltage VBAT is transferred to
The grid of NMOS tube Q1 opens NMOS tube, and signal CC3200_DETECT is pulled low, namely generates effective key detection letter
Number, and it is respectively sent to master chip U11 and reset chip U1, master chip U11 and reset chip U1 start timing.
As shown in figure 3, power circuit includes a power management chip U10, receive the control of power supply enable signal DCDC_EN
System, provides operating voltage VDD for master chip U11.
Be provided between the grid and power supply enable signal end of NMOS tube Q1 the second diode D2, the second diode D2 by
NMOS tube Q1 prevents power circuit from generating abnormal current signal and passes through the enabled letter of power supply to power supply enable signal end one-way conduction
Number end DCDC_EN load lead to its damage on NMOS tube Q1.
As a same reason, the power control terminal out-put supply of master chip U11 controls signal CC3200_PWR_CTL, with power supply
First diode D1 is provided between enable signal end, first diode D1 is unidirectional to power supply enable signal end by master chip U11
Conducting prevents power circuit from generating abnormal current signal and is loaded on master chip U11 by power supply enable signal end DCDC_EN
And lead to its damage.
Reset circuit includes that a reset controls chip U1, resets the signal input part and key press detecting circuit of control chip U1
Connection resets control chip U1 according to key and detects signal CC3200_ for receiving key detection signal CC3200_DETECT
The duration of DETECT judges whether to generate reset signal CC3200_NRST and be exported by reset signal output end.When pressing
Key time that is pressed can be set as 11.25s not less than setting time t2(such as t2) when, it is effective to reset control chip U1 output
Low level reset signal CC3200_NRST, and be respectively sent to reset latching circuit and master chip, resetting latching circuit will answer
Reversely output high level is to power supply enable signal end afterwards for position signal, so that power supply enable signal end remains the effective of high level
Power supply enable signal, namely lockked effective power supply enable signal by reset latching circuit, master chip U11 receives reset letter
It number is resetted.
Reset circuit further includes 3rd resistor R3 and third capacitor C3, resets the signal input part of control chip U1 by the
Three resistance R3 are connect with power end VDD, and one end of third capacitor C3 is connected between 3rd resistor R3 and power end VDD, in addition
One end connects ground terminal.3rd resistor R3 plays the role of for the level of the input terminal of reset circuit being pulled to high level, resets electricity
For the input terminal on road for receiving key detection signal, it is effective that key detects signal low level.Reset circuit is defeated under normal condition
Outlet exports high level, is invalid reset signal, multiple when open state and when key is pressed the time not less than setting time t2
Position circuit exports low level reset signal to reset latching circuit and master chip respectively by movement.
Resetting latching circuit includes a phase inverter U2, the input terminal of phase inverter U2 and the reset signal output end of reset circuit
Connection, the output end of phase inverter U2 are connect with power supply enable signal end.Phase inverter U2 is used for low level reset signal is reversed
Output high level is to power supply enable signal end afterwards, so that power supply enable signal end remains the enabled letter of effective power supply of high level
Number.
Be provided with third diode D3 between the output end and power supply enable signal end of phase inverter U2, third diode D3 by
Phase inverter U2 prevents power circuit from generating abnormal current signal and passes through the enabled letter of power supply to power supply enable signal end one-way conduction
Number end DCDC_EN load lead to its damage on phase inverter U2.
The front end at power supply enable signal end is additionally provided with accumulator.It is multiple to reset the effective low level of control chip U1 output
Position signal CC3200_NRST to after resetting latching circuit, reset latching circuit by low level reset signal CC3200_NRST into
Row is reversed, output high level to power supply enable signal end, is used to power supply enable signal lockking high level, at this time master chip U11
It resets, while power control signal is pulled low, power supply enable signal is lockked into high level due to resetting latching circuit at this time, not shadow
Power circuit is rung for master chip power supply, is avoided and is operated caused equipment shutdown due to resetting.Simultaneously from reset signal CC3200_
NRST is pulled down to during resetting latching circuit starting, and the energy storage of accumulator prevents power supply enable signal DCDC_EN voltage
Quickly fall, avoid because reset latching circuit work delay caused by product shutdown.
Accumulator includes the first capacitor C1 and the 4th resistance R4 being in parallel, and the one of first capacitor C1 and the 4th resistance R4
End is connect with power supply enable signal end respectively, and other end connects ground terminal.Reset is pulled down to from reset signal CC3200_NRST
During latching circuit starts, the energy storage of first capacitor C1 can externally discharge, it is therefore prevented that power supply enable signal DCDC_EN voltage
Quickly fall.
When shutdown, reset chip U11 does not have output reset signal, and master chip drags down power control signal CC3200_
PWR_CTL, first diode D1 cut-off, so that master chip discharges the control to power supply enable signal DCDC_EN；Key is released simultaneously
After putting, supply voltage VBAT can not be transferred to the second diode D2, the second diode D2 cut-off, and cell voltage VBAT also discharges
Enable to power supply the control of pin DCDC_EN；First capacitor C1 and the 4th resistance R4 composition repid discharge path, such first
The electricity of capacitor C1 discharges quickly, and power supply enables pin DCDC_EN and is quickly in low level state, completes quickly shutdown, thus
It avoids that equipment is made to be in false off-mode, avoids user in the maloperation of false off-mode.
Detection key duration t1, t2 that is pressed can modify setting, and if t1 may be configured as 5s, but the unused time is greater than
The available machine time that starting key is pressed, and it is less than the time that reset key is pressed.Realize hardware reset it is key controlled when
Between t2 can set long a bit (such as 11.25s) and distinguished with the key controlled time shut down, avoid the maloperation of user,
Increase user experience.
Certainly, the above description is not intended to limit the present invention, and the utility model is also not limited to the example above,
The variations, modifications, additions or substitutions that those skilled in the art are made in the essential scope of the utility model,
It should also belong to the protection scope of the utility model.
Claims (10)
1. a kind of reset circuit for opening/closing, it is characterised in that: including master chip, power circuit, reset circuit, key press detecting circuit
And latching circuit is resetted, the control that the power circuit receives the power supply enable signal from power supply enable signal end is described
Master chip power supply, power supply enable signal end are wherein connect by key with cell voltage output end all the way, the second tunnel and institute
The output end connection for resetting latching circuit is stated, third road is connect with the power control terminal of the master chip, the key detection electricity
Road is connected between the cell voltage output end and power supply enable signal end, presses shape for detect the key
State, and generate key detection signal and be respectively sent to the reset circuit and master chip, the reset circuit is according to the key
The duration of detection signal judges whether to generate reset signal and export by reset signal output end that the reset signal is defeated
Outlet is wherein connect with the input terminal for resetting latching circuit all the way, is in addition connect all the way with the master chip, the main core
Piece is resetted according to the reset signal, and the master chip is generated according to current on-off state and key detection signal
Power control signal is simultaneously exported by the power control terminal to power supply enable signal end.
2. reset circuit for opening/closing according to claim 1, it is characterised in that: the key press detecting circuit includes a NMOS
Pipe, the grid of the NMOS tube are wherein connected to all the way between the cell voltage output end and power supply enable signal end,
In addition it is connect all the way by second resistance with ground terminal, the source electrode of the NMOS tube is connect with ground terminal, and drain electrode is examined for output key
Signal is surveyed, is connect respectively with the reset circuit and master chip.
3. reset circuit for opening/closing according to claim 2, it is characterised in that: the grid of the NMOS tube and the power supply
The second diode is provided between enable signal end.
4. reset circuit for opening/closing according to claim 1, it is characterised in that: the power control terminal of the master chip and institute
It states and is provided with first diode between power supply enable signal end.
5. reset circuit for opening/closing according to claim 1, it is characterised in that: the reset circuit includes a reset control
Chip, the signal input part for resetting control chip are connect with the key press detecting circuit, for receiving key detection signal,
The control chip that resets judges whether to generate reset signal and passes through reset according to the duration that the key detects signal
Signal output end output.
6. reset circuit for opening/closing according to claim 5, it is characterised in that: the reset circuit further includes 3rd resistor
With third capacitor, the signal input part for resetting control chip is connect by 3rd resistor with power end, the third capacitor
One end be connected between the 3rd resistor and power end, other end connect ground terminal.
7. reset circuit for opening/closing according to claim 1, it is characterised in that: the reset latching circuit includes a reverse phase
Device, the input terminal of the phase inverter are connect with the reset signal output end of the reset circuit, the output end of the phase inverter with
The connection of power supply enable signal end.
8. reset circuit for opening/closing according to claim 7, it is characterised in that: the output end of the phase inverter and the electricity
Source is provided with third diode between enable signal end.
9. reset circuit for opening/closing according to claim 1-8, it is characterised in that: power supply enable signal end
Front end be additionally provided with accumulator.
10. reset circuit for opening/closing according to claim 9, it is characterised in that: the accumulator includes being in parallel
One end of first capacitor and the 4th resistance, the first capacitor and the 4th resistance is connect with power supply enable signal end respectively,
Other end connects ground terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920007854.0U CN209134375U (en) | 2019-01-03 | 2019-01-03 | A kind of reset circuit for opening/closing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920007854.0U CN209134375U (en) | 2019-01-03 | 2019-01-03 | A kind of reset circuit for opening/closing |
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| Publication Number | Publication Date |
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| CN209134375U true CN209134375U (en) | 2019-07-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920007854.0U Active CN209134375U (en) | 2019-01-03 | 2019-01-03 | A kind of reset circuit for opening/closing |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109412568A (en) * | 2019-01-03 | 2019-03-01 | 歌尔科技有限公司 | A kind of reset circuit for opening/closing |
| CN110806792A (en) * | 2019-10-30 | 2020-02-18 | 京东方科技集团股份有限公司 | Hardware on-off circuit and electronic equipment |
| CN111474877A (en) * | 2020-03-20 | 2020-07-31 | 瓴芯电子科技(无锡)有限公司 | Load switch circuit and control method thereof |
-
2019
- 2019-01-03 CN CN201920007854.0U patent/CN209134375U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109412568A (en) * | 2019-01-03 | 2019-03-01 | 歌尔科技有限公司 | A kind of reset circuit for opening/closing |
| CN109412568B (en) * | 2019-01-03 | 2024-04-02 | 歌尔科技有限公司 | Reset circuit for switching on and switching off |
| CN110806792A (en) * | 2019-10-30 | 2020-02-18 | 京东方科技集团股份有限公司 | Hardware on-off circuit and electronic equipment |
| CN111474877A (en) * | 2020-03-20 | 2020-07-31 | 瓴芯电子科技(无锡)有限公司 | Load switch circuit and control method thereof |
| CN111474877B (en) * | 2020-03-20 | 2024-03-26 | 瓴芯电子科技(无锡)有限公司 | Load switching circuit and control method thereof |
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