CN207819870U - Integrated clock local oscillator processor - Google Patents
Integrated clock local oscillator processor Download PDFInfo
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- CN207819870U CN207819870U CN201820188709.2U CN201820188709U CN207819870U CN 207819870 U CN207819870 U CN 207819870U CN 201820188709 U CN201820188709 U CN 201820188709U CN 207819870 U CN207819870 U CN 207819870U
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- power splitter
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- local oscillator
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Abstract
The utility model is related to a kind of integrated clock local oscillator processors, belong to accelerator low level microwave technical field comprising the first power splitter, the second power splitter, frequency divider and frequency mixer；Input signal INPUT connects the input terminal of the first power splitter, output end output at least two paths of signals through first power splitter, the output signal all the way of first power splitter exports at least two paths of signals, an input terminal of the another way signal input mixer of first power splitter after frequency divider and the second power splitter；The output signal all the way of second power splitter is as clock signal clk, the another way output signal of second power splitter inputs another input terminal of the frequency mixer, the input terminal of the output termination filter of the frequency mixer, the output end output local oscillation signal LO of the filter；The utility model good in anti-interference performance avoids jitter error and greatly improves amplitude-phase stability.
Description
Technical field
The utility model is related to a kind of integrated clock local oscillator processors, belong to accelerator low level microwave technology neck
Domain.
Background technology
The amplitude-phase that scientific research accelerator installation carries out microwave signal by low level system controls, in low level system
In, local oscillation signal needs to be generated by special microwave converter plant with clock signal, and local oscillation signal is needed with clock signal
With reference signal high level of synchronization.Traditional local oscillator unit is separative element with clock generator, is carried out by different oscillators
Mutually locking is caused discreteness error larger, Bu Nengman by variation of ambient temperature and electromagnetic interference influence in actual use
Requirement of the increasing scientific research accelerator installation of foot to amplitude-phase precision.
Utility model content
The technical problem to be solved by the utility model is to provide a kind of good in anti-interference performance, avoid jitter error and
Greatly improve the integrated clock local oscillator processor of amplitude-phase stability.
A kind of integration clock local oscillator processor comprising the first power splitter, the second power splitter, frequency divider and frequency mixer；
Input signal INPUT connects the input terminal of the first power splitter, the output end output at least two paths of signals through first power splitter, institute
The output signal all the way for stating the first power splitter exports at least two paths of signals, first work(after frequency divider and the second power splitter
Divide an input terminal of the another way signal input mixer of device；The output signal all the way of second power splitter is believed as clock
Number CLK, the another way output signal of second power splitter input another input terminal of the frequency mixer, the frequency mixer
The input terminal of output termination filter, the output end output local oscillation signal LO of the filter.
Further, the utility model further includes detection module, and the output all the way of the output end of first power splitter connects
Detection module, the output end output indicator signal LED of the detection module.
Further, the directly output all the way of the output end of first power splitter, as with reference to signal RF OUTPUT.
Further, the quantity of the frequency divider is more than or equal to 1, and the input terminal and/or output end of second power splitter are equipped with respectively
The frequency divider of Self Matching.The frequency divider can be divided into the first frequency divider, the second frequency divider, third frequency divider etc. different type
Several frequency dividings the frequency divider of several frequency dividings to match is designed according to the size for the local oscillation signal LO to be exported.
Further, the utility model is mounted in the babinet with shielding shell.
Further, the detection module includes detecting circuit or the detecting circuit including being electrically connected to each other and amplifier electricity
Road.
The beneficial effects of the utility model are as follows：
The utility model is directly divided reference signal INPUT extremely using the first power splitter and frequency divider by analog form
IF frequency, then be directly superimposed upon IF frequency on reference signal INPUT in a manner of being mixed frequency mixer, by filter
Reference signal and intermediate-freuqncy signal are filtered out, local oscillation signal LO is generated；The higher harmonic components of IF frequency are filtered by another simultaneously
Wave device is filtered, and retains clock signal clk, the noise signal other than filtering out.In this way, local oscillation signal LO and clock signal clk
It is directly realized by by analog circuit, avoids the jitter error that digital locking circuit is brought, it is steady to greatly improve amplitude-phase
It is qualitative.All circuit components are integrated in the cabinet with shielding shell, realize integrated interference free performance.Phase
Than conventionally employed phase-lock mode by the mode of multiple and different frequency oscillator mutually lockings, the utility model is in stability and integrates
It improves a lot on the key performances such as property.
Description of the drawings
Fig. 1 is the structural principle block diagram of the utility model.
Fig. 2 is the structural principle block diagram of the embodiments of the present invention.
Specific implementation mode
The utility model is described further with reference to Fig. 1-Fig. 2 and specific embodiment.
As depicted in figs. 1 and 2, according to the above-mentioned deficiencies in the prior art, problem to be solved in the utility model is：It provides
A kind of new design scheme no longer by multiple oscillator lockings, but directly generates clock signal and this by reference signal
Shake signal, and union is mounted in a generator in groups, reaches higher amplitude-phase stability, realizes at integrated clock local oscillator
Manage device.
The comparative situation of traditional local oscillator unit and the present embodiment integration clock local oscillator processor is as shown in the table：
| Performance parameters | Traditional local oscillator unit | Integrated clock local oscillator processor |
| Time jitter error | About 1ps | <0.05ps |
| Phase synchronism | It is not exclusively synchronous | It is fully synchronized |
| Temperature stability | It is poor | It is good |
| Phase synchronism | It is unstable | It is fully synchronized |
| Integrated level | It is low | It is high |
The present embodiment is related to a kind of integrated clock local oscillator processor comprising the first power splitter, the second power splitter, first
Frequency divider, the second frequency divider, third frequency divider and frequency mixer；Input signal INPUT connects the input terminal of the first power splitter, through described
The output end of first power splitter exports at least two paths of signals A and B, wherein signal A is by the first frequency divider and the second work(point all the way
At least two paths of signals A1 and A2, wherein an input terminal of another way signal B input mixers are exported after device；Second work(point
The output signal A1 of device is used as clock signal clk, the output signal A2 of second power splitter to pass through after the second frequency divider
Another input terminal of the frequency mixer is inputted after third frequency divider, the output of the frequency mixer terminates the input terminal of filter,
The output end output local oscillation signal LO of the filter.
Below by taking S-band clock local oscillator as an example, each signal elaborates：
(1) 2856MHz INPUT input signals.Reference signal as the system.
(2) 105MHz CLK clock signals.By reference signal through four power splitters, nine frequency dividers, two power splitters and three frequency division
Device obtains.It is by mathematical formulae summary：2856÷9÷3≈105.78MHz
(3) 2830MHz LO local oscillation signals.Reference signal is through four power splitters, nine frequency dividers, two power splitters and ten two divided-frequencies
The intermediate-freuqncy signal that device obtains is superimposed upon in a manner of frequency mixer in reference signal, filters out intermediate-freuqncy signal by filter and benchmark is believed
Number, generate 2830MHz LO local oscillation signals.It is following mathematical formulae by above-mentioned text summary, you can be expressed as：
(4) whether LED signal indicator light, display reference signal are input to clock local oscillator generator.Reference signal is through four work(
Divide device to enter detection module, realizes that analog signal switchs to digital signal, carry out the LED signal indicator light outside controlling machine box.
(5) 2856MHz RF OUTPUT output signals are directly exported through power splitter.It is used as reference signal.Such as Fig. 1
Shown in Fig. 2, in the present embodiment, the first power splitter is four power splitters, and the second power splitter is two power splitters, and frequency divider includes the
One frequency divider, the second frequency divider and third frequency divider, wherein first frequency divider is nine frequency dividings, the second frequency divider is three points
Frequently, third frequency divider is ten two divided-frequencies, and the input of four power splitter terminates 2856MHz input signal INPUT, as this system
Reference signal, what it is through three frequency division output is the CLK clock signals of 105MHz, the output of filtered device is 2830MHz LO
Local oscillation signal；One output end of four power splitter directly connects detection module, realizes that analog signal switchs to digital signal, to control
LED signal indicator light outside cabinet processed, for showing whether reference signal is input to clock local oscillator generator；Four work(point
Device there are one output end output be 2856MHz RF OUTPUT output signals, be used as reference signal.
Above-mentioned detailed description is illustrating for the utility model possible embodiments, which is not to limit
The scope of the claims of the utility model, all equivalence enforcements or change without departing from the utility model are intended to be limited solely by the patent of this case
In protection domain.
Claims (7)
1. a kind of integration clock local oscillator processor, it is characterised in that：It includes the first power splitter, the second power splitter, frequency divider
And frequency mixer；Input signal INPUT connects the input terminal of the first power splitter, the output end output at least two through first power splitter
The output signal all the way of road signal, first power splitter exports at least two paths of signals after frequency divider and the second power splitter,
One input terminal of the another way signal input mixer of first power splitter；The output signal all the way of second power splitter
As clock signal clk, the another way output signal of second power splitter inputs another input terminal of the frequency mixer, institute
State the input terminal of the output termination filter of frequency mixer, the output end output local oscillation signal LO of the filter.
2. integration clock local oscillator processor according to claim 1, it is characterised in that：It further includes detection module, institute
The output all the way for stating the output end of the first power splitter connects detection module, the output end output indicator signal of the detection module
LED。
3. integration clock local oscillator processor according to claim 1 or 2, it is characterised in that：First power splitter
Output end directly exports all the way, as with reference to signal RF OUTPUT.
4. integration clock local oscillator processor according to claim 1, it is characterised in that：The quantity of the frequency divider is more than
Equal to 1, the input terminal and/or output end of second power splitter are equipped with respective matched frequency divider.
5. integration clock local oscillator processor according to claim 1 or 2, it is characterised in that：It, which is mounted on, has shielding
In the babinet of shell.
6. integration clock local oscillator processor according to claim 3, it is characterised in that：It, which is mounted on, has shielding shell
Babinet in.
7. integration clock local oscillator processor according to claim 2, it is characterised in that：The detection module includes detection
Circuit or detecting circuit and operational amplifier circuit including being electrically connected to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820188709.2U CN207819870U (en) | 2018-02-05 | 2018-02-05 | Integrated clock local oscillator processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820188709.2U CN207819870U (en) | 2018-02-05 | 2018-02-05 | Integrated clock local oscillator processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207819870U true CN207819870U (en) | 2018-09-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201820188709.2U Active CN207819870U (en) | 2018-02-05 | 2018-02-05 | Integrated clock local oscillator processor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109120318A (en) * | 2018-11-07 | 2019-01-01 | 上海创远仪器技术股份有限公司 | The circuit structure of local oscillator driving function is realized based on extensive MIMO technique |
-
2018
- 2018-02-05 CN CN201820188709.2U patent/CN207819870U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109120318A (en) * | 2018-11-07 | 2019-01-01 | 上海创远仪器技术股份有限公司 | The circuit structure of local oscillator driving function is realized based on extensive MIMO technique |
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