CN206610287U - A kind of LPC master-slave swap control systems based on SECO - Google Patents
A kind of LPC master-slave swap control systems based on SECO Download PDFInfo
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- CN206610287U CN206610287U CN201720160749.1U CN201720160749U CN206610287U CN 206610287 U CN206610287 U CN 206610287U CN 201720160749 U CN201720160749 U CN 201720160749U CN 206610287 U CN206610287 U CN 206610287U
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Abstract
The utility model is related to a kind of LPC master-slave swap control systems based on SECO, including CPU, PCH bridge chips, it is characterized in that, the control system also includes first switch type device, second switch type device, CPU is connected with PCH bridge chips, BMC FPGA managing chips are connected through first switch type device with PCH bridge chips, BMC FPGA managing chips are connected through second switch type device with creditable calculation modules, the control system also includes timing control unit, the timing control unit respectively with CPU, PCH bridge chips, BMC FPGA managing chips, the control end connection of creditable calculation modules, pass through SECO, realization does main equipment and does the switching of slave unit, so it is achieved that by one group of lpc bus and not only does main equipment but also do slave unit, do not conflict, wiring is simple and saves lpc bus logical resource.
Description
Technical field
The utility model belongs to server design technical field, and in particular to a kind of LPC principals and subordinates based on SECO cut
Change control system.
Background technology
Lpc bus has the characteristic of string simultaneously, some characteristics of existing universal serial bus, and has some of parallel bus simultaneously
Characteristic.In communication process, communicated with the frame signal in conventional communication protocols, synchronizing signal, answer signal, but entirely
It is again with the parallel data transmission of 4 in journey.In server field, many traditional servers are realized by BMC managing chips
Outband management and credible measurement, AST2500 managing chips are using two groups of lpc bus, respectively as main interface and from interface, realize
Interface principal and subordinate changes, and such a method increase wiring space, wastes lpc bus logical resource.And be to adapt to trusted servers to need
Ask, it is ensured that mainboard safe operation to system, it is necessary to be improved.
Utility model content
The purpose of this utility model is that design is a kind of to be based on sequential in view of the above-mentioned drawbacks of the prior art, providing
The LPC master-slave swap control systems of control, to solve above-mentioned technical problem.
To achieve these goals, the technical solution of the utility model is：
A kind of LPC master-slave swap control systems based on SECO, including CPU, PCH bridge chip, it is characterised in that should
Control system also includes first switch type device, second switch type device, and CPU is connected with PCH bridge chips, BMC-FPGA management cores
Piece is connected by first switch type device with PCH bridge chips, BMC-FPGA managing chips by second switch type device with it is credible
Computing module connect, the control system also include timing control unit, the timing control unit respectively with CPU, PCH bridge core
Piece, BMC-FPGA managing chips, the control end connection of creditable calculation modules；BMC-FPGA managing chips have 2 GPIO ports point
Not Wei the first GPIO port and the second GPIO port, the first GPIO port is connected with first switch type device, the second GPIO port
It is connected with second switch type device, PCH bridge chips, BMC-FPGA managing chips, creditable calculation modules have LPC interfaces, BMC-
The LPC interfaces of FPGA managing chips are connected with first switch type device, second switch type device respectively.
The LPC interfaces of PCH bridge chips are connected with the 3rd terminals of first switch type device, BMC-FPGA managing chips
LPC interfaces are connected with the first terminals of first switch type device and the 3rd terminals of second switch type device respectively, credible
The LPC interfaces of computing module are connected with the first terminals of second switch type device.
First GPIO port of BMC-FPGA managing chips is connected with the second terminals of first switch type device, and second
GPIO port is connected with the second terminals of second switch type device.
Preferably, CPU is connected with PCH bridge chips through DMI buses.
Preferably, creditable calculation modules are TPCM.
PCH bridge chips also include ETH interfaces, USB interface, RAID interfaces, HDD interface.
BMC-FPGA managing chips also include ROM interfaces, IIC interfaces, ETH interfaces, ddr interface, Flash interfaces.
BMC-FPGA managing chips have the IP kernel for the management function that BMC is instead of with FPGA independent developments（IP-CORE）.
Trusted servers are autonomous using FPGA (Field-Programmable Gate Array) field programmable gate array
Exploitation instead of the management function of BMC chip, and the realization of LPC master and slave functional module is realized by independent development IP-CORE,
And pass through SECO, it is possible to achieve do main equipment and do the switching of slave unit, be so achieved that by one group of lpc bus
Not only do main equipment but also done slave unit, do not conflicted, and save LPC logical resources.In order to prevent on same link, principal and subordinate cuts
After changing, the isolation of two functional links, two switching-type devices of increase and two GPIO port controls are turned on and off switching mode
Device.Sequential electric sequence for 1. 2. 3. 4. when, timing control unit is first to 1. 2. upper electricity, now BMC-FPGA managing chips
It is first upper electric with creditable calculation modules, S1 is closed by GPIO port control, S2 is opened, BMC-FPGA managing chips, which are decided, to be set
Standby, creditable calculation modules do slave unit.
After creditable calculation modules are sent to timing control unit 3. measures ok signals, timing control unit is opened 4., together
When BMC-FPGA managing chips closed by GPIO port control and S2 and open S1, at this moment BMC-FPGA managing chips are done from setting
Standby, PCH bridge chips do main equipment, are communicated.By such a process, one group of lpc bus is achieved that based on sequential
Master and slave equipment switching.
The beneficial effects of the utility model are, by SECO, and realization does main equipment and does the switching of slave unit, this
Sample is achieved that by one group of lpc bus not only to be done main equipment but also does slave unit, is not conflicted, and wiring is simple and to save LPC total
Line logical resource.
In addition, the utility model design principle is reliable, and it is simple in construction, with application prospect widely.
As can be seen here, the utility model compared with prior art, with substantive distinguishing features and progress, its beneficial effect implemented
Fruit is also obvious.
Brief description of the drawings
A kind of LPC master-slave swap control system architecture figures based on SECO that Fig. 1 provides for the utility model.
Wherein, 1-CPU, 2- PCH bridge chips, 3-BMC-FPGA managing chips, 4- creditable calculation modules, 5- SECO
Unit, 6- first switch type devices, 7- second switch type devices, the GPIO ports of 8- first, 9- BMC-FPGA managing chips
LPC interfaces, the GPIO ports of 10- second, the LPC interfaces of 11- PCH bridge chips, the LPC interfaces of 12- creditable calculation modules.
Embodiment
Below in conjunction with the accompanying drawings and the utility model is elaborated by specific embodiment, following examples are to this
The explanation of utility model, and the utility model is not limited to implementation below.
As shown in figure 1, a kind of LPC master-slave swap control systems based on SECO that the present embodiment is provided, including CPU
1st, PCH bridges core 3, first switch type device 6, second switch type device 7, CPU 1 is connected with PCH bridge chips 2, BMC-FPGA management
Chip 3 is connected by first switch type device 6 with PCH bridge chips 2, and BMC-FPGA managing chips 3 pass through second switch type device
7 are connected with creditable calculation modules 4, the control system also include timing control unit 5, the timing control unit 5 respectively with CPU
1st, the control end connection of PCH bridge chips 2, BMC-FPGA managing chips 3, creditable calculation modules 4；BMC-FPGA managing chips 3 have 2
Individual GPIO port is respectively the first GPIO port 8, the second GPIO port 10, and the first GPIO port 8 connects with first switch type device 6
Connect, the second GPIO port 10 is connected with second switch type device 7, PCH bridge chips 2, BMC-FPGA managing chips 3, trust computing
Module 4 has a LPC interfaces, respectively 9,11, the LPC interfaces 9 of 12, BMC-FPGA managing chips respectively with first switch type device
6th, second switch type device 7 is connected.
The LPC interfaces 11 of PCH bridge chips are connected with the 3rd terminals of first switch type device 6, BMC-FPGA management cores
The LPC interfaces 9 of piece connect with the first terminals of first switch type device 6 and the 3rd terminals of second switch type device 7 respectively
Connect, creditable calculation modules LPC interfaces 12 are connected with the first terminals of second switch type device 7.
First GPIO port 8 of BMC-FPGA managing chips is connected with the second terminals of first switch type device 6, and second
GPIO port 10 is connected with the second terminals of second switch type device 7.
CPU 1 is connected with PCH bridge chips 2 through DMI buses.
Creditable calculation modules are TPCM.
PCH bridge chips 2 also include ETH interfaces, USB interface, RAID interfaces, HDD interface.
BMC-FPGA managing chips 3 also include ROM interfaces, IIC interfaces, ETH interfaces, ddr interface, Flash interfaces.
Trusted servers instead of BMC management function using FPGA independent developments, be realized by independent development IP-CORE
The realization of LPC master and slave functional module, and pass through SECO, it is possible to achieve do main equipment and do the switching of slave unit, this
Sample is achieved that by one group of lpc bus not only to be done main equipment but also does slave unit, is not conflicted, and save LPC logical resources.For
Prevent on same link, after master-slave swap, the isolation of two functional links, two switching-type devices 6,7 of increase and two
GPIO port 8,10 controls to be turned on and off switching-type device.Sequential electric sequence be Fig. 1 in 1. 2. 3. 4. when, sequential control
1. unit 5 processed first gives 2. upper electricity, and now BMC-FPGA managing chips 3 and creditable calculation modules 4 are first upper electric, pass through GPIO port control
System closes S1, opens S2, and BMC-FPGA managing chips 3 do main equipment, and creditable calculation modules 4 do slave unit.
After creditable calculation modules 4 are sent to timing control unit 5 3. measures ok signals, 4. timing control unit 5 is opened
, while BMC-FPGA managing chips are closed by GPIO port control S2 and opens S1, at this moment BMC-FPGA managing chips 3 do from
Equipment, PCH bridge chips 2 do main equipment, are communicated, by such a process, and one group of lpc bus is achieved that based on sequential
Master and slave equipment switching.
Term " first ", " second ", " the 3rd " in specification and claims of the present utility model etc.（If deposited
）It is for distinguishing similar object, without for describing specific order or precedence.It should be appreciated that so use
Data can be exchanged in the appropriate case, so that embodiment of the present utility model described herein can be with except illustrating herein
Or the order beyond those of description is implemented.In addition, term " comprising " and " having " and their any deformation, it is intended that
Covering is non-exclusive to be included.
Disclosed above is only preferred embodiment of the present utility model, but the utility model is not limited to this, any
What those skilled in the art can think does not have creative change, and is made under the premise of the utility model principle is not departed from
Some improvements and modifications, should all fall in protection domain of the present utility model.
Claims (8)
1. a kind of LPC master-slave swap control systems based on SECO, including CPU, PCH bridge chip, it is characterised in that the control
System processed also includes first switch type device, second switch type device, and CPU is connected with PCH bridge chips, BMC-FPGA managing chips
It is connected by first switch type device with PCH bridge chips, BMC-FPGA managing chips are by second switch type device and credible meter
Calculate module connection, the control system also include timing control unit, the timing control unit respectively with CPU, PCH bridge chip,
The control end connection of BMC-FPGA managing chips, creditable calculation modules；BMC-FPGA managing chips have 2 GPIO ports to be respectively
First GPIO port and the second GPIO port, the first GPIO port are connected with first switch type device, the second GPIO port and
Two switching-type devices are connected, and PCH bridge chips, BMC-FPGA managing chips, creditable calculation modules have LPC interfaces, BMC-FPGA
The LPC interfaces of managing chip are connected with first switch type device, second switch type device respectively.
2. a kind of LPC master-slave swap control systems based on SECO according to claim 1, it is characterised in that PCH
The LPC interfaces of bridge chip are connected with the 3rd terminals of first switch type device, the LPC interfaces difference of BMC-FPGA managing chips
It is connected with the first terminals of first switch type device and the 3rd terminals of second switch type device, creditable calculation modules
LPC interfaces are connected with the first terminals of second switch type device.
3. a kind of LPC master-slave swap control systems based on SECO according to claim 1, it is characterised in that
First GPIO port of BMC-FPGA managing chips is connected with the second terminals of first switch type device, the second GPIO port with
The second terminals connection of second switch type device.
4. a kind of LPC master-slave swap control systems based on SECO according to claim 1, it is characterised in that CPU
It is connected with PCH bridge chips through DMI buses.
5. a kind of LPC master-slave swap control systems based on SECO according to claim 1, it is characterised in that can
Letter computing module is TPCM.
6. a kind of LPC master-slave swap control systems based on SECO according to claim 1, it is characterised in that PCH
Bridge chip also includes ETH interfaces, USB interface, RAID interfaces, HDD interface.
7. a kind of LPC master-slave swap control systems based on SECO according to claim 1, it is characterised in that
BMC-FPGA managing chips also include ROM interfaces, IIC interfaces, ETH interfaces, ddr interface, Flash interfaces.
8. a kind of LPC master-slave swap control systems based on SECO according to claim 1, it is characterised in that
BMC-FPGA managing chips include the IP-CORE for the management function that BMC is instead of with FPGA independent developments.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720160749.1U CN206610287U (en) | 2017-02-22 | 2017-02-22 | A kind of LPC master-slave swap control systems based on SECO |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720160749.1U CN206610287U (en) | 2017-02-22 | 2017-02-22 | A kind of LPC master-slave swap control systems based on SECO |
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| CN206610287U true CN206610287U (en) | 2017-11-03 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109471770A (en) * | 2018-09-11 | 2019-03-15 | 华为技术有限公司 | A kind of method for managing system and device |
| CN109902491A (en) * | 2019-02-28 | 2019-06-18 | 苏州浪潮智能科技有限公司 | A kind of safe operation management framework and server of server |
| CN112711552A (en) * | 2020-12-29 | 2021-04-27 | 深圳微步信息股份有限公司 | Server control circuit and terminal equipment |
-
2017
- 2017-02-22 CN CN201720160749.1U patent/CN206610287U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109471770A (en) * | 2018-09-11 | 2019-03-15 | 华为技术有限公司 | A kind of method for managing system and device |
| CN109902491A (en) * | 2019-02-28 | 2019-06-18 | 苏州浪潮智能科技有限公司 | A kind of safe operation management framework and server of server |
| CN112711552A (en) * | 2020-12-29 | 2021-04-27 | 深圳微步信息股份有限公司 | Server control circuit and terminal equipment |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171103 Termination date: 20190222 |
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| CF01 | Termination of patent right due to non-payment of annual fee |