CN206595986U

CN206595986U - A kind of frequency synthesizer module

Info

Publication number: CN206595986U
Application number: CN201720031863.4U
Authority: CN
Inventors: 秦安岭
Original assignee: YANGZHOU COMMUNICATION EQUIPMENT CO Ltd
Current assignee: YANGZHOU COMMUNICATION EQUIPMENT CO Ltd
Priority date: 2017-01-11
Filing date: 2017-01-11
Publication date: 2017-10-27
Anticipated expiration: 2027-01-11

Abstract

The utility model discloses a kind of frequency synthesizer module in electronic component field, including：Crystal oscillator, produces a fixed frequency signal；First phase-locked loop chip, it works in Integer N frequency dividing pattern, and built-in VCO, and the fixed reference frequency that crystal oscillator is sent exports adjustable frequency signal as reference frequency；Second phase-locked loop chip, it works in Integer N frequency dividing pattern and fractional-N divide pattern, and built-in VCO, the adjustable frequency signal that first phase-locked loop chip is exported is used as reference source, and the frequency signal needed for exporting, it is spuious to eliminate the border in the required frequency signal by finely tuning the frequency signal as reference source that the first phase-locked loop chip is exported；The output end of the crystal oscillator is connected with the input of the first phase-locked loop chip, and the output end of the first phase-locked loop chip is connected with the input of the second phase-locked loop chip, and its cost is low, size is small, applied widely, available in modular applications.

Description

A kind of frequency synthesizer module

Technical field

The present invention relates to a kind of module chip, more particularly to a kind of frequency synthesizer module.

Background technology

Modularization has become the main trend of present product, and I takes charge of product and am also constantly carrying out modularized circuit and knot Structure, with continuing to develop for product, gradually recognizes the limitation of XXX type product part of module in the past, non-universal, so By summary of experience, the design of general module is proceeded by and applied among later product.

The frequency synthesizer module operating frequency range that I is taken charge of in existing XXX type products is 1190MHz and 1290 respectively ~1360MHz, frequency coverage is narrow, phase noise≤- 95dBc@10KHz, in frequency converting time ＜ 1ms, and a product Two frequency synthesizer modules are employed, cost is higher, and volume is larger.Old module master chip uses Integer N frequency dividing lock phase Ring, output frequency stepping can only be the integral multiple of phase demodulation frequency, to improve output performance and also need to extra DDS (Direct Digitals Frequency synthesizer) circuit and external VCO (voltage controlled oscillator), limitation is larger, and new module master chip uses N points of decimal Frequency phase locked loop, frequency step is less than 10Hz, is that can further improve performance with reference to rear class table tennis process circuit, can be used as general frequency Rate Senthesizer module is used.

This module explanation by taking Hittite companies high performance wideband phaselocked loop HMC833 use as an example.Inside this phaselocked loop VCO is integrated with, the space shared by external VCO is eliminated, meets Miniaturization Design theory, reference frequency output is 25~ 6000MHz, fundamental frequency is 1500~3000MHz, and remaining frequency is obtained by built-in maximum 62 frequency divider and frequency multiplier.Internal phase demodulation The phase demodulation frequency of device reaches as high as 100MHz, and on the one hand high phase demodulation frequency can reduce phase noise, on the other hand can set The loop filter of broader bandwidth is counted, so as to suppress VCO noises and frequency locking time is changed in shortening.The power output highest of the chip Up to+9dBm, fourth gear is adjustable, stepping 3dB.

The chip is operable with Integer N frequency dividing pattern and fractional-N divide pattern, and wherein fractional-N divide employs Delta- Sigma modulation techniques, it is possible to achieve very small stepping, typical resolution is 3Hz, and introduced under fractional-N divide pattern Precise frequency pattern so that some frequencies for meeting specified conditions can obtain accurately.This phase-locked loop chip also has industry The leading extremely low phase noise in boundary and spuious, its typical case mutually makes an uproar as -110dBc/Hz, and normalization phase bottom of making an uproar is -227dBc/ Hz, spuious representative value is less than -90dBc, meets this module design requirement.It is sufficiently low spuious to save in many application scenarios Go the demand with reference to DDS.Extremely low near-end is mutually made an uproar makes system may operate in broader loop bandwidth, and broader frequency with spuious Rate saltus step.Chip size is 6x6mm, and can keep good performance at -40~+85 DEG C.

Different from integer-N PLL, the onrelevant of VCO working frequencies and phase demodulation frequency can cause fractional-N divide PLL produces spurious signal.Therefore, to produce sideband spuious for the intermodulation of VCO and phase demodulation harmonic wave.When VCO working frequency connects very much It is spuious the most serious during the integral multiple of nearly phase demodulation frequency.When VCO working frequencies are overlapped with phase demodulation harmonic wave just, do not have near Hold mixed product.As illustrated in fig. 1 and 2, interference is always occurred from the integral multiple of phase demodulation frequency.VCO frequency and nearest reference Difference frequency Δ between the harmonic wave of frequency, that is, the integral boundary produced is spuious.According to the mode of operation of frequency synthesizer, higher rank Number, the spurious signal of more low amplitude produces the integral multiple point (subharmonic) in phase demodulation frequency.Here it is close to (n+d/m) * F_pd VCO fractional strays, wherein F_pdFor phase demodulation frequency, n, d and m are integers, and d<m.We are by F_pd* d/m is referred to as integer portion Point.Denominator m is the exponent number of spuious product.M values are higher, and the spurious signal of the skew m* Δs of generation is smaller, generally, works as m>It is miscellaneous when 4 Scattered signal is just small to can not measure.Worst situation is under fractional mode, to work as d=0, and VCO frequencies are with respect to n*F_pd Skew be less than loop bandwidth when, here it is with the spuious situation of interior integral boundary.

The content of the invention

It is an object of the invention to provide a kind of frequency synthesizer module so that its cost is low, size is small, applied widely.

The object of the present invention is achieved like this：A kind of frequency synthesizer module, including：

Crystal oscillator, produces a fixed frequency signal；

First phase-locked loop chip, it works in Integer N frequency dividing pattern, and built-in VCO, the fixation that crystal oscillator is exported Frequency exports adjustable frequency signal as reference frequency；

Second phase-locked loop chip, it works in Integer N frequency dividing pattern and fractional-N divide pattern, and built-in VCO, by first The adjustable frequency signal of phase-locked loop chip output exports required frequency signal as reference source, passes through fine setting first and locks The frequency signal as reference source of phase ring core piece output, it is spuious to eliminate the border in the required frequency signal；

The output end of the crystal oscillator is connected with the input of the first phase-locked loop chip, the first phase-locked loop chip it is defeated Go out end with the input of the second phase-locked loop chip to be connected.

During present invention work, reference frequency is produced by a non-tunable crystal oscillator, by using with integer First phaselocked loop of frequency dividing pattern, can be in the second given phaselocked loop VCO output frequencies as high-quality tunable reference source On the basis of change its reference frequency so that reach eliminate integral boundary spurious signal purpose.Compared with prior art, it is of the invention Beneficial effect be：The present invention improves module output performance by using built-in VCO structures while reducing volume； The phaselocked loop that pattern is divided with decimal N is employed, frequency resolution is less than 10Hz so that its scope of application is more extensive；Together When, in order to eliminate the frequency exported under fractional-N divide pattern, to there is certain border spuious, and the present invention is using adjustable reference source On-fixed reference source so that can directly be locked and effectively suppressed second by the border spurious signal that filtering is difficult elimination Phase-locked loop chip output end, exports humorous clutter recognition performance and mitigates rear class filtering burden, improve signal defeated so as to improve module The stability gone out.

In order to further improve the filter effect of the present invention, frequency synthesizer module also includes：

First switch circuit, receives the range frequencies of the second phase-locked loop chip output, and is divided into the frequency of multiple frequency ranges Rate signal；

Later stage rattles process circuit, is provided with multigroup, and is connected in parallel, first switch circuit output is come to receive Multiple frequency ranges frequency signal, and its is handled respectively；

Second switch circuit, the frequency signal of the complete multiple frequency ranges of reception processing, and corresponding frequency band is exported as needed Frequency signal；

The input of first switch circuit is connected with the output end of the second phase-locked loop chip, the output end of first switch circuit It is connected with the input of post processing circuitry, the output end of the post processing circuitry is connected with the input of second switch circuit；

In order to be further ensured that the effect of frequency signal rear class processing, the rear class table tennis process circuit includes being linked in sequence Pre-amplification circuit, attenuator circuit, rear class amplifying circuit, filter circuit together, the input connection of the pre-amplification circuit On first switch circuit, the output end of filter circuit is connected on second switch circuit.

In order to further improve the efficiency and performance of phaselocked loop processing, first phase-locked loop chip and the second phaselocked loop Chip selects high performance wideband phase-locked loop chip, it is desirable to which the first phase-locked loop chip output frequency meets the second phase-locked loop chip Input requirements, are operated in Integer N frequency dividing pattern, and frequency programmable dividing output, built-in low phase noise VCO is normalized with interior phase Background noise≤- 220dBc/Hz, phase demodulation frequency >=40MHz, phase demodulation is spuious≤- 80dB；Second phase-locked loop chip bandwidth of operation >= 3000MHz, is operated in integer and fractional-N divide pattern, and frequency programmable dividing output, built-in low phase noise VCO, normalization band is interior Phase background noise≤- 220dBc/Hz, phase demodulation frequency >=40MHz, phase demodulation is spuious≤- 80dB and with reducing cycle slip function.

Brief description of the drawings

Fig. 1 is phase-locked loop chip HMC833 internal frame diagrams in the prior art.

Fig. 2 is fractional stray schematic diagram in the prior art.

Fig. 3 is modular structure schematic diagram of the present invention.

Fig. 4 is circuit theory diagrams one of the present invention.

Fig. 5 is circuit theory diagrams two of the present invention.

Embodiment

A kind of frequency synthesizer module as in Figure 3-5, it is characterised in that including：

Crystal oscillator, produces a fixed frequency signal；

First phase-locked loop chip, built-in VCO is worked in Integer N frequency dividing pattern, it is to avoid be operated in fractional-N divide mould The spuious influence late-class circuit brought under formula, the fixed frequency that crystal oscillator is sent exports adjustable as reference frequency Frequency signal；

Post processing electric circuit, is provided with multigroup, and is connected in parallel, to receive from first switch circuit separate it is many The frequency signal of individual frequency range, and respectively being handled its, what the post-processing circuit included being linked in sequence together pre- puts Big circuit, attenuator circuit, rear class amplifying circuit, filter circuit, the input of the pre-amplification circuit are connected to first switch electricity Lu Shang, the output end of filter circuit is connected on second switch circuit；

The output end of the crystal oscillator is connected with the input of the first phase-locked loop chip, the first phase-locked loop chip it is defeated Go out end with the input of the second phase-locked loop chip to be connected；The output end of the input of first switch circuit and the second phase-locked loop chip It is connected, the output end of first switch circuit is connected with the input of post-processing circuit, the output end of the post-processing circuit It is connected with the input of second switch circuit, first phase-locked loop chip and the second phase-locked loop chip are public from Hittite Take charge of high performance wideband phaselocked loop HMC833.

Utility model works process comprises the following steps：

1) crystal oscillator produces a fixed reference frequency signal；

2) the adjustable fixed frequency of fixed reference frequency signal output that the first phase-locked loop chip is produced according to crystal oscillator Rate signal, the first phase-locked loop chip is simultaneously worked under integral frequency divisioil pattern and fractional frequency division pattern；

3) frequency signal for exporting the first phase-locked loop chip leads to as the reference frequency signal source of the second phase-locked loop chip Cross the fixed frequency signal of fine setting the first phase-locked loop chip output so that the second phase-locked loop chip exports one and filtered out target The frequency signal of spuious stabilization, the second phase-locked loop chip simultaneously works in Integer N frequency dividing pattern and fractional-N divide pattern Under；

4) frequency signal for exporting the second phaselocked loop carries out table tennis processing through first switch circuit；

5) frequency signal after table tennis is handled carries out pre-amplification, decay, amplification, filtering process successively；

6) by frequency signal after treatment through second switch circuit output.

The data of frequency synthesizer controls are divided into 5 bytes, and data divide two parts again：

Part I：

Calculation formula is as follows：

f_out1× 20=80 × N_int1Formula 1

N_int2=f_out2/(f_out1/ 2) formula 2

Wherein：

f_out1For the output frequency of the first phase-locked loop chip；

f_out2For the output frequency of the second phase-locked loop chip；

N_int1For the integer frequency ratio of the first phase-locked loop chip；

N_int2For the integer frequency ratio of the second phase-locked loop chip.

N is obtained according to above formula_int1Value；

Part II：

Continue to obtain N by formula 2_int2Value, and by N_int2Bring into below equation, calculate corresponding integral boundary The spuious difference between dominant frequency, by finely tuning f_out1It is that the spuious filtering in border can be achieved to coordinate loop bandwidth；

| Δ 1 |=| f_out2- N_int2×(f_out1/ 2) | formula 3

| Δ 2 |=| f_out2- (N_int2+0.5)×(f_out1/ 2) | formula 4

| Δ 3 |=| f_out2- (N_int2+1)×(f_out1/ 2) | formula 5

f_out2=(f_out1/2)×(N_int2+N_frac) formula 6

N_frac×2²⁴=Reg04h formula 7

Wherein：

| Δ | it is the spuious difference between dominant frequency of integral boundary；

N_fracFor the fractional frequency division ratio of the second phase-locked loop chip；

Reg04h is the corresponding title register value in phaselocked loop.

When | Δ |>During 2 or Δ 2=0 or Δ 3=0, Nint2 and Reg04h value is calculated as follows.Data format is Nint2 (1 byte)+Reg04h (3 byte) (sending data successively in units of 1 byte).

When | Δ 1 | when=0, Reg04h (3 byte) is all 0x00.

With reference to instantiation, the present invention will be further described.

The reference frequency of crystal oscillator output is set as 80MHz, the output frequency for controlling the first phaselocked loop is f_out1= 80MHz, the output frequency of the second phaselocked loop is：f_out2=2400.2MHz, the phase demodulation frequency F of the second phase-locked loop chip_pd= 40MHz, the integer frequency ratio N of the second phase-locked loop chip_int2(2400.2MHz/40MHz)=60, the second phase-locked loop chip it is small Number frequency dividing ratio N_frac=(2400.2MHz/40MHz)=0.2, sets loop bandwidth=150kHz.

The spuious Δ 1=f of 1 rank integral boundary_out2-N_int2*F_pdIt is after=2400.2-60*40=0.2MHz, output frequency division 100kHz。

The spuious Δ 2=f of 2 rank integral boundaries_out2-(N_int2+0.5)*F_pd=2400.2-60.5*40=19.8MHz, output It is 9.9MHz after frequency dividing.

The spuious Δ 3=f of 3 rank integral boundaries_out2-(N_int2+1)*F_pd=2400.2-61*40=39.8MHz, output frequency division It is 19.9MHz afterwards.

Using the frequency parameter before adjustable reference source technology as it appears from the above, 1 rank integral boundary miscellaneous to be scattered in loop bandwidth attached Closely, frequency shift (FS) 100kHz, 2 ranks and 3 ranks are miscellaneous is scattered in band outside and farther out are not considered.

The output frequency of the first phase-locked loop chip is finely tuned, it is f to make its output frequency_out1=81.6MHz, phase demodulation frequency F_pd= 40.8MHz, the integer frequency ratio N of the second phase-locked loop chip_int2=(2400.2MHz/40.8MHz)=58, the second phaselocked loop core The fractional frequency division of piece compares N_frac=(2400.2MHz/40.8MHz)=33.8, loop bandwidth=150kHz.

1 rank integral boundary is spuious=F_out-N_int2*F_pdIt is after=2400.2-58*40.8=33.8MHz, output frequency division 16.9MHz。

2 rank integral boundaries are spuious=F_out-(N_int2+0.5)*F_pd=2400.2-58.5*40.8=13.4MHz, output point It is 6.7MHz after frequency.

3 rank integral boundaries are spuious=F_out-(N_int2+1)*F_pdIt is after=2400.2-59*40.8=7MHz, output frequency division 3.5MHz。

Using the frequency parameter after adjustable reference source technology as it appears from the above, 1 rank, 2 ranks and 3 ranks it is miscellaneous be scattered in band it is outer and compared with Far, it is spuious to disappear；By two PLL of reasonable disposition, tunable reference source technology while the performance such as maintain necessary phase to make an uproar, 50dB spurious reduction even can be realized.

The invention is not limited in above-described embodiment, on the basis of technical scheme disclosed by the invention, the skill of this area Art personnel are according to disclosed technology contents, it is not necessary to which performing creative labour just can make one to some of which technical characteristic A little to replace and deform, these are replaced and deformed within the scope of the present invention.

Claims

1. a kind of frequency synthesizer module, it is characterised in that including：

Crystal oscillator, produces a fixed frequency signal；

First phase-locked loop chip, it works in Integer N frequency dividing pattern, and built-in VCO, the fixed reference that crystal oscillator is sent Frequency exports adjustable frequency signal as reference frequency；

Second phase-locked loop chip, it works in Integer N frequency dividing pattern and fractional-N divide pattern, and built-in VCO, phase is locked by first The adjustable frequency signal of ring core piece output exports required frequency signal as reference source, by finely tuning the first phaselocked loop The frequency signal as reference source of chip output, it is spuious to eliminate the border in the required frequency signal；

The output end of the crystal oscillator is connected with the input of the first phase-locked loop chip, the output end of the first phase-locked loop chip It is connected with the input of the second phase-locked loop chip.

2. a kind of frequency synthesizer module according to claim 1, it is characterised in that also include：

First switch circuit, receives the range frequencies of the second phase-locked loop chip output, and is divided into the frequency letter of multiple frequency ranges Number；

Later stage rattles process circuit, is provided with multigroup, and is connected in parallel, to receive from many of first switch circuit output The frequency signal of individual frequency range, and respectively handled its；

Second switch circuit, the frequency signal of the complete multiple frequency ranges of reception processing, and the frequency of corresponding frequency band is exported as needed Signal；

The input of first switch circuit is connected with the output end of the second phase-locked loop chip, and the output end of first switch circuit is with after The input of process circuit is connected, and the output end of the post processing circuitry is connected with the input of second switch circuit.

3. a kind of frequency synthesizer module according to claim 2, it is characterised in that the later stage table tennis process circuit bag Pre-amplification circuit, attenuator circuit, rear class amplifying circuit, the filter circuit being linked in sequence together are included, the pre-amplification circuit Input is connected on first switch circuit, and the output end of filter circuit is connected on second switch circuit.

4. a kind of frequency synthesizer module according to any one of claim 1-3, it is characterised in that the first lock phase Ring core piece and the second phase-locked loop chip select high performance wideband phase-locked loop chip, it is desirable to which the first phase-locked loop chip output frequency is expired The input requirements of the second phase-locked loop chip of foot, are operated in Integer N frequency dividing pattern, frequency programmable dividing output, built-in low phase noise VCO, normalization is with interior phase background noise≤- 220dBc/Hz, phase demodulation frequency >=40MHz, and phase demodulation is spuious≤- 80dB；Second lock Phase ring core piece bandwidth of operation >=3000MHz, is operated in integer and fractional-N divide pattern, frequency programmable dividing output, built-in low phase position Noise VCO, normalization is with interior phase background noise≤- 220dBc/Hz, phase demodulation frequency >=40MHz, phase demodulation is spuious≤- 80dB simultaneously With reduction cycle slip function.