CN206442403U - A kind of vehicle communication experiment porch - Google Patents

Abstract

The utility model discloses a kind of vehicle communication experiment porch, this platform compatibility IEEE802.11p standards, and possess the function of real-time experimental data collection and on-line analysis, including data acquisition unit, media access controller, physical-layer modem, radio circuit, ADC/DAC circuits, arm processor etc., is realized using SoC (" ARM+FPGA ") framework.The utility model can be used in terms of vehicular communication system proof of algorithm and channel measurement, has the advantages that small volume, is easy to carry, is easy to Function Extension.

Description

A kind of vehicle communication experiment porch

Technical field

The utility model belongs to the communications field, more particularly to a kind of vehicle communication experiment porch.

Background technology

At present, the information between vehicle, which is exchanged, needs to face communication environments complex under outdoor high-speed mobile environment, such as The quick time-varying of communication environments and the caused network topology structure change of traffic flow Biomass dynamics change caused by vehicle high-speed movement Deng, therefore physical layer (Physical Layer, PHY) base band signal process algorithm and medium access control (Media Access Control, MAC) layer channel access mechanisms in terms of should optimize design for vehicle communication environment.Current IEEE 802.11p standards are vehicle communication technology de facto standards, but it has to be solved the problem of still suffer from many, such as quick time-varying Vehicle communication channel estimation what track and traffic current density it is larger when congestion control and broadcast storm avoid.Due to height Dynamic outdoor communication environment and traffic scene, computer based emulation is difficult accurately to show related algorithm and mechanism Actual performance, they need to be estimated and verify under real outdoor communication environment.

Three kinds, i.e. business DSRC platforms can be substantially divided into, be based on by being presently available for carrying out the experiment porch of vehicle communication The experiment porch of 802.11a chipsets and the experiment porch based on software radio.The business DSRC of compatible 802.11p standards is put down Platform is big all in test phase at present, is only used in some large-scale scientific research projects.On the one hand, communicated in these commercial products Related algorithm and parameter configuration is not allow user to change, therefore is also not used in terms of verifying and assessing the communication technology New results.On the other hand, these commercial products are typically to be designed for current IEEE 802.11p standards, and they are difficult Immediately following the process of standardization.Some researchers approximately realize DSRC agreements using business 802.11a chipsets, but 802.11a Crucial transceiver algorithm in chipset optimizes both for static indoor application, and complicated outdoor propagation environment can make Obtain the hydraulic performance decline of these chipsets.The correlation time of vehicle communication channel is shorter, and the head of packet and afterbody are generally by face Face entirely different channel circumstance, receiver needs the constantly change of tracking estimation channel during reception.But it is most 802.11a chips are all using the channel estimation obtained according to long preambles symbol come balanced all OFDM data symbols, this obviously meeting Cause the decline of systematic function.DSRC terminals are realized using SDR systems in addition, also there is researcher.SDR platforms are generally by hardware With software two subsystems composition.Data exchange between its software and hardware subsystem generally uses Ethernet, USB or PCI Completed Deng interface.Consider from PHY layer, limited transmission bandwidth, which limits some, between software and hardware subsystem needs mass data The use of the signal processing algorithm of exchange；From the point of view of MAC layer, some Medium Access Control operations must several microseconds when Interior to complete and need accurate timing, the implementation based on SDR will cause the decline of dispatching efficiency.In addition, software without Line level platform needs to carry out signal of communication processing by processing platforms such as notebook computer or desktop computers, and usual volume is larger, takes Band inconvenience.

In summary, above-mentioned three kinds existing vehicle communication platforms, are not particularly suited in complicated outdoor propagation environment Carry out the related scientific experiment of vehicle communication.

The content of the invention

The utility model is not particularly suited for entering in complicated outdoor propagation environment to solve existing vehicle communication platform The problem of row vehicle communication related scientific experiment and a kind of vehicle communication experiment porch is provided.

The utility model is adopted the technical scheme that to solve technical problem present in known technology：A kind of vehicle leads to Believe experiment porch, including PHY, MAC, data acquisition unit, hardware interface, drive circuit, RF, ADC/DAC converter, radio frequency electrical Road, DDR chips, GPS module and arm processor, wherein arm processor pass through high speed Avalon bus on chips and hardware interface It is connected；MAC, PHY, drive circuit are connected with hardware interface and data acquisition unit simultaneously；Peripheral DDR chips are adopted with data simultaneously Storage is connected with arm processor；ADC/DAC chips are connected with drive circuit and RF chips simultaneously；RF chips and radio-frequency antenna phase Even；GPS module is connected with hardware interface.

Further, the PHY, MAC, drive circuit, data acquisition unit, hardware interface are integrated in SoC chip Fpga logic resource in 5CSXFC6D6F31C6N is built on hardware circuit.

Further, the two-way ADC is AD conversion chip AD9254, and two-way DAC is DAC5672 chips, 5.8GHz radio frequencies Circuit is MAX2829 chips, and arm processor is the ARM9 processors in SoC chip 5CSXFC6D6F31C6N.

The utility model has the advantages and positive effects of：The utility model can be used in vehicular communication system algorithm In terms of checking and channel measurement, there is small volume, be easy to carry, be easy to Function Extension.

The utility model for the scientific research personnel of vehicle communication technical field provide one kind be convenient for Data acquisition and issuance, The tool of the verification of PHY and MAC algorithms, propagation channel measurement and analysis and outfield experiments management, fills up gaps in market.

Brief description of the drawings

Fig. 1 is the structural representation for the vehicle communication experiment porch that the utility model embodiment is provided；

Fig. 2 is that the PHY entities that the utility model embodiment is provided realize block diagram；

Fig. 3 is that the MAC that the utility model embodiment is provided realizes block diagram；

Fig. 4 is the data acquisition module block diagram that the utility model embodiment is provided；

In figure：1st, DDR chips；2nd, SoC chip 5CSXFC6D6F31C6N；3rd, data acquisition unit；4th, MAC circuit；5、PHY Circuit；6th, drive circuit；7th, hardware interface；8th, the FPGA circuitry in SoC chip；9th, the arm processor in SoC chip；10、 (AD9254 and DAC5672 chips are respectively adopted) in ADC/DAC；11st, radio frequency chip (using MAX2829 chips)；12nd, 5.8GHz is penetrated Frequency antenna；13rd, GPS location and time service module.

Embodiment

For invention, features and effects of the present utility model can be further appreciated that, following examples are hereby enumerated, and coordinate Accompanying drawing describes in detail as follows.

Structure of the present utility model is described in detail below in conjunction with the accompanying drawings.

As shown in figure 1, the vehicle communication experiment porch that the utility model embodiment is provided, including SoC chip 2, AD/DA turn Change chipset 10, radio frequency chip 11, DDR chips 1 and radio-frequency antenna to constitute, wherein SoC chip 2 is by FPGA circuitry 8 and ARM processing Device 9 is constituted；

Hardware logic electric circuit is built based on the FPGA circuitry 8 in the SoC chip 2, realized：Data acquisition unit 3, MAC Circuit 4, PHY circuit 5, drive circuit 6, hardware interface 7；

The hardware interface 7 is used to complete DMA transfer, the read-write capability of control information, with the MAC circuit 4, PHY electrical Road 5, drive module 6 and data acquisition unit 3 are connected, all submodules in full powers control FPGA circuitry 8, in DMA transfer process It is middle that the information such as vehicle real-time geographical locations and GPS time services (being obtained by GPS module 13) is inserted into data flow；

The data acquisition unit 3 is connected with the MAC circuit 4, PHY circuit 5, drive circuit 6, in the control of hardware interface 7 System is lower to obtain the real-time running state and data for connecting submodule, and the data obtained is sent into ARM by hardware interface module 7 Processor 9；

The PHY of the utility model embodiment realizes that its block diagram is as shown in Figure 2 using fpga chip.Whole PHY entities include Sending module, receiving module, four parts of PHY control modules and hardware interface.Sending module is responsible for transmission bit and flows to complex radical The coding and modulating transformation of band signal, the demodulation that receiving module is used to receive complex baseband signal to reception bit stream are decoded, firmly Part interface is used to drive peripheral ADC/DAC and radio frequency chip, PHY controllers complete to send and receive the control of process, PHY with The communication interface and data acquisition control of MAC layer.

In terms of channel estimation method, the utility model employs the mechanism of decoding feedback.Received for each OFDM symbol, receiving terminal first decoded according to demodulation after data bit stream reconstruction transmitting terminal baseband signal, then according to should The baseband signal of reconstruct reevaluates channel response, and the channel equalization by the channel response estimated for next OFDM symbol Process.Estimation is tracked by the iteration of OFDM symbol one by one, PHY of the present utility model realizes used channel estimation mechanism energy The vehicle communication channel response of the quick time-varying of enough dynamic tracking estimations, effectively improves the reliability of data transfer.

In terms of dual-mode antenna configuration, the utility model employs single transmitting antenna and the space diversity of double reception antenna connects The mode strengthening system reliability of receipts, while the processing mode of single-shot list receipts can also be configured to by high-level interface.In addition, being System instability problem caused by cross clock domain design is avoided, whole PHY all submodules have been used uniformly 80MHz's Clock signal drives.

Hardware MAC of the present utility model realized using fpga chip, including CSMA/CD random backs, physics and virtual Carrier sense mechanism, automatic ACK/CTS are replied, the assembling of two steps and four step handshake mechanisms and data frame and disassemble several parts, Fig. 3 gives MAC and realizes block diagram.The utility model employs the mode that data and control passage are separated, it by control passage, Three parts of data channel and interface unit are constituted.Control passage is responsible for being controlled the flow sent and received, and data are led to Road is used for according to fixed parameter generation management and data frame or the parameter according to the data-flow analysis associated frame received, interface Unit realizes standard interlayer access interface specified in IEEE802.11p standards.

Data channel major function is disassembling for the assembling of completion mac frame.According to IEEE 802.11p standards, a MAC Frame is made up of multiple different domains.Frame Control domains indicate that the type of frame, Duration/ID domains are detectd for virtual carrier Listen, the address field of 46 bytes saves source/destination address and the network address, the CRC check field that FCS domains are 4 bytes, often Individual mac frame can carry the payload of 0-2312 bytes in Frame Body domains.Because multiple processing procedures are (such as in MAC protocol Send, receive, keep out of the way) it is required for being related to the associative operation of frame, the utility model is independent so as to shape by this partial function Into the data channel shown in Fig. 3.In the transmission process of mac frame, the parameter group that data channel is provided according to control passage Fill corresponding frame, and it is sent to in addition PHY transmission after CRC check code by the data-interface between MAC and PHY In buffering area.During reception, data channel analyzes the relevant parameter of receiving frame according to the byte stream received, and by its Pass to control passage processing.Data channel is not related to the function of any Row control.

Control passage is mainly used in completing to send the control for receiving flow.Control of keeping out of the way in Fig. 3 completes CSMA/CA's Random back function, its major function is included：(1) received signal power provided according to physical layer indicates to complete physical carrier Intercept；(2) virtual carrier sensing in wireless network communication is completed according to the Duration/ID domains of receiving frame；(3) according to physics and virtual carrier sensing in wireless network communication As a result stochastic backoff process is performed.Sending controller is used to be controlled the transmission process of mac frame.When upper strata has mac frame to need When sending, controller is sent：(1) start random back and wait and keep out of the way end；(2) RTS/CTS is performed as needed to shake hands； (3) above-mentioned mac frame is sent；(4) DATA/ACK is performed as needed to shake hands or start retransmission processes；Controller is received according to data The reception process for the receiving frame state modulator mac frame that passage is provided, including automatic ACK transmissions and CTS transmissions etc..

In order to obtain the real-time running state inside hardware system in processor system, make system debug and test Work is more efficient, and the utility model devises special data acquisition module by the real-time letter of key modules inside hardware system Number collection out and be saved in the internal memory of processor system.In practice process, the module can either facilitate in debugging process With quickly locate guilty culprit, also can in test process be used for real-time testing data offline preservation.Data acquisition module Block is made up of multiple collecting units, acquisition controller and the several parts of data filtering units.Collecting unit is embedded in PHY and MAC In entity, realize relatively simple, its design frame chart is as shown in Figure 4.

CPU can select signal to be collected as needed, in order to gather the signal of multiple submodule, this reality simultaneously Unified addressing has been carried out with the new critical data signal to PHY, MAC and drive circuit, and the collection of data acquisition unit is total Line is divided into multiple packets, and every group can be individually arranged to gather different submodule block signals.Gathered in the utility model total Line width is 64, eight packets is divide into altogether, the signal of every group of collection can be configured by register group S0-S7 (being shown in Table 1), is schemed Gathered data selecting module completes the function in 4.

The embedded logic analyzer module register of table 1 is described

MAC and PHY signals in whole system run time also can not need not be gathered and handle in view of processor subsystem, The utility model specifies collection by the condition (such as when rising edge occurs in certain signal wire) for specifying signal to be collected to possess Carved at the beginning of process, the trigger condition detection module in Fig. 4 by detecting whether output signal possesses the condition specified in real time To decide whether to start collection.Trigger collection condition is configured by four PSW C0-C3, and each condition can be separately configured It judges numbering (Cn [14 of the signal wire in data acquisition bus:8]) and its decision condition (Cn [7:0]), the Rule of judgment of support Including rise/fall edge, high/low level etc..In addition, in order that condition can be carried out in a different manner by obtaining four decision conditions Combination, the utility model provides COMB registers to store the truth table of its conditional combination mode.The Chief Signal Boatswain of single acquisition Degree is configured by LENG registers.In addition, low speed gathered data stream can be exported to arm processor, the data flow of high speed is exported Shown to logic analyser.

CPU and FPGA hardware circuit carry out data exchange, hardware interface mould by hardware interface module in the utility model Block is realized using fpga chip, for completing the functions such as DMA transfer, the read-write of control information.Between CPU and fpga logic circuit The information of exchange can be divided into data flow and control information.Data flow includes the collection output of mac frame and data acquisition module, Because data volume is big and requires to complete the transmission of data flow in relatively low switching delay, the utility model by the way of DMA.Control Information processed include arm processor to the configuration information of correlation module in hardware and they pass to arm processor performance unite Count information etc..Control information data volume is smaller, and the information for reading or writing all is stored in the corresponding register of hardware system. The utility model has carried out unified addressing to all addressable registers, and the exchange of control information specifies address by read-write Register is completed.

For the ease of this vehicular communication system important performance indexes of measurement propagation delay time, the utility model is in hardware interface In be that the data flow of each exchange inserts it and sends and receives temporal information.When propagation delay time is transmitted comprising PHY end to end Prolong, MAC transmission delays and processing delay etc..PHY propagation delay times are relevant with modulation used and coded system, MAC transmission delays Depending on back off algorithm, keep out of the way the real-time parameters such as window size and number of retransmissions, processing delay is with itself algorithm complex, upper strata The many factors such as the process scheduling of operating system are relevant.Due in terms of the operating system process scheduling, arm processor is very Hardly possible carries out accurate latency measurement.In order to which to measuring and analyzing, work offer is convenient, the utility model is by hardware interface in hair The mac frame for sending and receiving and time and the vehicle real-time geographic position that its transmission and (or) reception are inserted in the data collected Confidence ceases.For the measurement clock of each node in synchronizing network, phase-locked loop of the utility model in fpga chip is employed A local measurement clock is generated, the GPS clock signal then provided by GPS time service modules periodically corrects local clock Signal.

Described above is only, to preferred embodiment of the present utility model, not to make any formal to the utility model Limitation, it is every according to technical spirit of the present utility model to any simple modification made for any of the above embodiments, equivalent variations with Modification, is belonged in the range of technical solutions of the utility model.

Claims (3)

1. a kind of vehicle communication experiment porch, it is characterised in that including PHY, MAC, data acquisition unit, hardware interface, driving electricity Road, RF, ADC/DAC converter, radio circuit, DDR chips, GPS module and arm processor, wherein arm processor pass through height Fast Avalon bus on chips are connected with hardware interface；MAC, PHY, drive circuit simultaneously with hardware interface and data acquisition unit phase Even；Peripheral DDR chips are connected with data acquisition unit and arm processor simultaneously；ADC/DAC chips simultaneously with drive circuit and RF cores Piece is connected；RF chips are connected with radio-frequency antenna；GPS module is connected with hardware interface.

2. vehicle communication experiment porch as claimed in claim 1, it is characterised in that the PHY, MAC, drive circuit, data are adopted The fpga logic resource that storage, hardware interface are integrated in SoC chip 5CSXFC6D6F31C6N is built on hardware circuit.

3. vehicle communication experiment porch as claimed in claim 1, it is characterised in that the ADC of the ADC/DAC converters turns for AD Chip AD9254 is changed, two-way DAC is DAC5672 chips, and 5.8GHz radio circuits are MAX2829 chips, and arm processor is SoC ARM9 processors in chip 5CSXFC6D6F31C6N.