CN206209066U - For chip testing and the device of programming - Google Patents
For chip testing and the device of programming Download PDFInfo
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- CN206209066U CN206209066U CN201621116876.3U CN201621116876U CN206209066U CN 206209066 U CN206209066 U CN 206209066U CN 201621116876 U CN201621116876 U CN 201621116876U CN 206209066 U CN206209066 U CN 206209066U
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- chip
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- pin
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Abstract
Present disclose provides the device for chip testing and programming, cost reduction, and user can simply confirm device and chip whether good contact.The device includes mainboard, is formed with mainboard：The first placement region corresponding with the main body of chip, around the first placement region and multiple first pins corresponding with multiple pins difference of chip, multiple first contacts outside the first placement region, and a plurality of first wire, every first wire is by first pin and first contact portion.When chip is placed in the first placement region, multiple pins of chip are in contact with multiple first pins respectively.
Description
Technical field
The embodiment of the present disclosure is related to the device for chip testing and programming.
Background technology
The test bench or programming seat of chip are mainly used for for software writing substantial amounts of core largely using in the electronics industry
In piece, and software development and functional test are carried out before plate-making.But existing test or programming seat price are higher, such as pin
The price of the programming seat of square shaped flat package (QFP) chip is general to arrive thousands of units hundreds of, and cost is too high for exploitation,
Therefore do not use largely on stream.
Existing programming seat also has an important shortcoming, that is, user cannot confirm, programming seat whether and be put into
Chip good contact.
The content of the invention
Present disclose provides the device for chip testing and programming, manufacturing process, reduces cost can be simplified, and make
User can simply confirm device and chip whether good contact.
There is provided a kind of for chip testing and the device of programming, including mainboard, it is formed with mainboard：With the main body of chip
Corresponding first placement region, around the first placement region and multiple first pins corresponding with multiple pins difference of chip,
Multiple first contacts outside the first placement region, and a plurality of first wire, every first wire is by first pin
With first contact portion.When chip is placed in the first placement region, multiple pins of chip are respectively with multiple first
Pin is in contact.
According to embodiment, the first placement region, the first pin, the first contact and the first wire are formed in the first table of mainboard
Face, is also formed with multiple second pins on the first surface of mainboard, and multiple second pins are right respectively with multiple pins of chip
Should, each second pin is neighbouring with corresponding first pin but does not contact, and when chip is placed on the first rest area
When on domain, each pin of chip is contacted respectively with corresponding first pin and second pin.Outside the first placement region, master
Multiple second contacts and a plurality of second wire are formed with the second surface relative with first surface of plate, every second wire will
One the second contact is connected with a second pin.
At least two first location holes are also formed with according to embodiment, on mainboard, described device also includes：Pressing plate, pressing plate
On be formed with least two second location holes corresponding with the first location hole of mainboard, and at least two alignment pins, for inserting
Enter in the first and second location holes.When chip is placed in the first placement region of mainboard and covers pressing plate, first determines
Position hole and the second location hole align respectively, and are inserted into the first and second location holes by alignment pin, by chip positioning first
Placement region.
According to embodiment, it is also formed with pressing plate：The second placement region corresponding with the main body of chip, places around second
Region and multiple 3rd pins corresponding with multiple pins difference of chip, the outside the second placement region the multiple 3rd touches
Point, and a plurality of privates, every privates is by the 3rd pin and the 3rd contact portion.When chip is placed on
When in the second placement region, multiple pins of chip are in contact with multiple 3rd pins respectively.
According to embodiment, described device also includes：Fixture, be placed in the first placement region of mainboard when chip and
When covering pressing plate, mainboard and pressing plate and chip sandwiched therebetween are fixed using fixture.
According to embodiment, the second placement region is formed to accommodate the recessed of chip or opening.
According to embodiment, described device also includes location-plate, and being formed with location-plate can accommodate the opening of chip, and
At least two the 3rd location hole corresponding with least two first location holes of mainboard.When chip is placed on the first placement of mainboard
On region and when covering location-plate, the first location hole and the 3rd location hole are alignd respectively, and chip is contained in the opening of location-plate,
And first and the 3rd location hole are inserted into by alignment pin, by chip positioning in the first placement region.
Compared to existing programming seat, the said apparatus of the disclosure at least have the following advantages that.
Each pin of existing programming seat is accurate plating Au probe or spring leaf, and pin is more, and processing cost is bigger.
The device of the disclosure can using printed circuit board (PCB) (PCB) process chemical attack technology, one-shot forming, no matter how many pin,
Processing cost can keep constant, and without precise machining equipment and technique.
Existing programming seat needs special mould, it is necessary to be directed to every kind of chip, custom precision mould and special material, cost
It is very high.The device of the disclosure uses conventional PCB process technologies, it is not necessary to special dies, and cost is greatly lowered.
For existing programming seat, special equipment and well-trained worker assembles are needed in factory, either up-front investment
With later stage operation, cannot all avoid the costs such as training.The device of the disclosure is without complicated assembling equipment and well-trained work
People, commonly manually, without equipment investment, without training, can greatly reduce cost to assemble rapidly.
Pin number is more in existing programming seat, not corresponding with chip pin, it is difficult to be confirmed whether good with the chip being put into
Good contact.The device of the disclosure can utilize pin and contact on mainboard and/or pressing plate, easily verify that whether be put into
Chip good contact.
Brief description of the drawings
From the following description of the embodiment of refer to the attached drawing, the further feature and advantage of the embodiment of the present disclosure will be clear
Understand.
Fig. 1 is shown according to the embodiment of the present disclosure for chip testing and the schematic diagram of the device of programming；
Fig. 2 shows that chip is installed to the schematic diagram tested with programmer；
Fig. 3 shows the schematic diagram of test and programmer including pressing plate；
Fig. 4 shows that chip is installed to the schematic diagram tested with programmer；
Fig. 5 shows the schematic diagram of the pressing plate according to another embodiment of the disclosure；
Fig. 6 shows the chip and test and programmer no good contact installed according to the confirmation of the embodiment of the present disclosure
Schematic diagram；
Fig. 7 shows the schematic diagram according to the test of another embodiment of the disclosure and the mainboard of programmer；
Fig. 8 shows the schematic diagram at the back side of mainboard shown in Fig. 7；
Fig. 9 shows the schematic diagram of test and programmer including location-plate；And
Figure 10 shows that the chip of the confirmation installation according to another embodiment of the disclosure is no with test and programmer good
The schematic diagram of contact.
Specific embodiment
In the disclosure, various embodiments and its accompanying drawing are explanation, be should not be construed in any way as limitation is open
Scope.It will be understood by those skilled in the art that the principle of the disclosure can be realized with any appropriately configured or structure.Hereafter
In, the exemplary embodiment of the disclosure is described with reference to the accompanying drawings.In the following description, the detailed of known function or configuration will be omitted
Description, reason is the purport that it will unnecessarily obscure the disclosure.Additionally, terms used herein is the work(according to the disclosure
Can define.Therefore, these terms can change with the intention or practice of user or user.Therefore, it is necessary to be based on herein
Description understand terms used herein.
Fig. 1 shows device (hereinafter referred test and the volume for chip testing and programming according to the embodiment of the present disclosure
Range device) schematic diagram.As shown in figure 1, the test and programmer include mainboard 1, the main body with chip 2 is formed with mainboard
Corresponding first placement region 10, such as shape and size in region 10 are corresponding with the shape and size of chip 2.The side of being of chip 2
The chip of shape flat package (QFP), in the disclosure as an example, being 32 QFP chips of pin.The disclosure is not limited to this
Chip, but go for the chip of various encapsulation.Be also formed with mainboard 1 around the first placement region 10 and with chip 2
Multiple pins distinguish corresponding multiple first pins 12, multiple first contacts 16 outside the first placement region 10, and
With first contact 16 be connected one the first pin 12 by a plurality of first wire 14, every first wire 14.When chip 2 is placed
When in the first placement region 10, multiple pins of chip are in contact with multiple first pins 12 respectively, as shown in Figure 2.Now,
Chip 2 can be tested and programmed by being connected to the first contact 16.Furthermore, it is possible to connect chip using such as universal meter
Pin and the first contact 16 to test break-make, detect the chip and test and the no good contact of programmer installed.Compared to
Existing programming seat, the test of the disclosure and programmer that mode is detected and confirmed is simple and easy to apply.
Fig. 3 shows the schematic diagram of test and programmer including pressing plate 3.As shown in figure 3, except mainboard 1, the test
Also include the alignment pin 4 of pressing plate 3 and at least two with programmer, for further positioning or fixed chip 2.In the embodiment
In, at least two first location holes 18 are formed with mainboard 1, for example it is formed on mainboard 1 outside first placement region 10, two
Location hole 18 is relative to one another on the diagonal corner of mainboard 1.The first location hole 18 pairs with mainboard 1 is formed with pressing plate 3
At least two second location holes 38 answered.Two alignment pins 4 are inserted into the first and second location holes, with positioning chip 2.May be used also
So that using the keeper of other forms, such as the location hole and alignment pin of other shapes, other numbers, the disclosure are not limited to the reality
Apply example.When chip 2 is placed in the first placement region 10 of mainboard 1 and covers pressing plate 3, the first location hole 18 and second is fixed
Position hole 38 is alignd respectively, and is inserted into the first and second location holes by alignment pin 4, and chip 2 is positioned at into the first placement region
10.Can be formed according to embodiment, on pressing plate 3 can accommodate the recessed of chip 2 or opening, as shown in figure 4, chip 2 is received
In the opening of pressing plate 2, so contribute to further positioning chip 2.
Fig. 5 shows the schematic diagram of the pressing plate according to another embodiment of the disclosure.Different from pressing plate 3, shape is gone back on pressing plate 3 '
Corresponding second placement region 30 of main body of Cheng Youyu chips 2, divides around the second placement region 30 and with multiple pins of chip 2
Not corresponding multiple 3rd pins 32, multiple 3rd contacts 36 outside the second placement region 30, and a plurality of privates
34, with the 3rd contact 36 be connected the 3rd pin 32 by every privates 34.When chip 2 is placed on the second rest area
When on domain 30, multiple pins of chip 2 are in contact with multiple 3rd pins 32 respectively.The second placement region 30 is shown in Fig. 5
Be formed as that shape and size are corresponding with chip 2, the recessed of chip 2 can be accommodated or be open.When being tested or being programmed, can
So that chip 2 to be first put into the second placement region 30 of pressing plate 3 ', alignment pin 4 is inserted into, then covers mainboard 1 so that alignment pin 4
The first and second location holes are inserted into, so as to chip 2 is accurate fixed and positioned.
According to the embodiment of the present disclosure, the test and programmer can also include fixture, when chip is placed on mainboard
In first placement region and when covering pressing plate, mainboard and pressing plate and chip sandwiched therebetween are fixed using fixture.Should
Fixture for example can be screw, by being screwed in the corresponding screw on mainboard and pressing plate, chip be fixed.The fixture may be used also
To be such as clip, mainboard and pressing plate are clamped.The disclosure is not limited to these examples, and is available with any appropriate consolidating
Determine mode.
Fig. 6 shows the chip 2 and test and the no good contact of programmer installed according to the confirmation of the embodiment of the present disclosure
Schematic diagram.The test of Fig. 6 and programmer include mainboard 1 and pressing plate 3 '.When chip 2 is installed, the pin of chip 2 should
Contacted respectively with the first pin 12 of mainboard 1 and the 3rd pin 32 of pressing plate 3 '.So, it is connected to the first contact using universal meter
16 and the 3rd contact 36 test break-make, the chip and test and programmer no good contact of installation can be detected.Compared to
Existing programming seat, the test of the disclosure and programmer that mode is detected and confirmed is simple and easy to apply.
Fig. 7 shows the schematic diagram according to the test of another embodiment of the disclosure and the mainboard 1 ' of programmer.In Fig. 7
The first placement region 10 ' corresponding with the main body of chip is formed with mainboard 1 ', around the first placement region 10 ' and with chip
Multiple pins distinguish corresponding multiple first pins 12 ', multiple first contacts 16 ' outside the first placement region 10 ', and
With first contact 16 ' be connected one the first pin 12 ' by a plurality of first wire 14 ', every first wire 14 '.First puts
Put the first surface that region 10 ', the first pin 12 ', the first contact 16 ' and the first wire 14 ' are formed in mainboard 1 ', for example for
The front of chip placement.Be also formed with multiple second pins 74 on the first surface of mainboard 1 ', multiple second pins 74 also around
First placement region 10 ', the multiple pins with chip are corresponding respectively, each second pin 74 and corresponding first pin
12 ' is neighbouring but do not contact, and when chip is placed on 10 ' in the first placement region, each pin of chip and corresponding the
One pin 12 ' and second pin 74 are contacted respectively.Additionally, outside the first placement region 10 ', mainboard 1 ' with first surface phase
To second surface (such as back side) on be also formed with multiple second contacts 72 and a plurality of second wire 70, as shown in figure 8, every
With a second pin 74 be connected for one the second contact 72 by the second wire 70.
The chip of such as Quad Flat No Lead package (QFN) can be placed using the mainboard 1 ' shown in Fig. 7 and 8,
As an example, being 16 QFN chips of pin in the disclosure.As shown in figure 9, first the putting that mainboard 1 ' can be placed on of chip 2 '
Put on region 10 ', the pin of chip 2 ' should be with the first pin 12 ' of mainboard 1 ' and the good contact of second pin 74.In order to true
Recognize whether good contact, be connected to the first contact 16 ' and the second contact 72 using universal meter, it becomes possible to detection install chip with
Test and the no good contact of programmer.Compared to existing programming seat, the test of the disclosure and being detected and confirmed for programmer
Mode is simple and easy to apply.
Additionally, as shown in figure 9, the test and programmer can also include location-plate 5, being formed with location-plate 5 can
Accommodate the opening of chip, and at least two the 3rd location hole corresponding with least two first location holes of mainboard.Work as chip
When being placed in the first placement region of mainboard and covering location-plate, the first location hole and the 3rd location hole align respectively, chip
It is contained in the opening of location-plate, and first and the 3rd location hole is inserted into by alignment pin, chip positioning is placed first
Region.
Figure 10 shows that the chip of the confirmation installation according to another embodiment of the disclosure is no with test and programmer good
The schematic diagram of contact.Test and programmer in Figure 10 include mainboard 1 ', location-plate 5, pressing plate 3 and the spiral shell as fixture
Nail 6.Chip 2 ' is placed into the first placement region 10 ' of mainboard 1 ' first, then covers upper location-plate 5, and plug alignment pin.
Then, pressing plate 3 is covered so that alignment pin is inserted into the corresponding location hole of mainboard 1 ', location-plate 5, pressing plate 3.Finally, in order to enter
One step is fixed, and is screwed into screw 6.After installing, in order to be confirmed whether good contact, the first contact is connected to using universal meter
16 ' and second contact 72 test break-make so that detection chip 2 ' and mainboard 1 ' whether good contact.Compared to existing programming
Seat, the installation of chip and the test of the disclosure and programmer that mode is detected and confirmed is simple and easy to apply.
The structure of existing programming seat is that have a gold-plated accurate flexible stylet or spring leaf below each chip pin,
It is connected to below programming seat, multiple probes or spring leaf are precisely fixed on programming seat shell body, then will by mechanical structure
Chip is fixed on probe or spring leaf.This structure is not easy to use, be also not susceptible to be detected and confirmed whether good contact.With
Difference, the test and programmer according to the embodiment of the present disclosure be easy to use, intuitively can simply be detected and confirmed whether
Good contact.
The structure of existing programming seat is that have a gold-plated accurate flexible stylet or spring below each chip pin
Piece, is connected to below programming seat；Multiple probes or spring leaf are precisely fixed on programming seat shell body；Then mechanical structure is passed through
Chip is fixed on probe or spring leaf.Thus, pin is more, and probe and spring leaf are also more, and processing cost is higher.Compare
In existing programming seat, the test of the disclosure and programmer can use pcb board technique, disposably manufacture mainboard, pressing plate and determine
Position plate, and with pcb board contact substitute probe, one-shot forming, no matter pin how much, cost is fixed.So, using conventional
PCB process technologies, it is not necessary to special dies, without complicated assembling equipment and well-trained workman, without equipment investment,
Without training, cost is greatly reduced.
Above-described embodiment and advantage are only that example should not be considered as limiting the disclosure.The teaching of the disclosure is readily applied to it
The device and equipment of his type.Additionally, the description of exemplary embodiment be intended to it is illustrative, rather than in order to limit claim
Scope, and those skilled in the art will be clear that various replacements, improvement and change.
Claims (7)
1. it is a kind of for chip testing and programming device, including：
Mainboard, is formed with mainboard
The first placement region corresponding with the main body of chip,
Around the first placement region and multiple first pins corresponding with multiple pins difference of chip,
Multiple first contacts outside the first placement region, and
A plurality of first wire, every first wire by first pin and first contact portion,
Wherein when chip is placed in the first placement region, multiple pins of chip are in contact with multiple first pins respectively.
2. device according to claim 1, wherein the first placement region, multiple first pins, the first contact and first are led
Line is formed in the first surface of mainboard,
Multiple second pins are also formed with the first surface of mainboard, multiple second pins are right respectively with multiple pins of chip
Should, each second pin is neighbouring with corresponding first pin but does not contact, and when chip is placed on the first rest area
When on domain, each pin of chip is contacted respectively with corresponding first pin and second pin,
Multiple second contacts and many are formed with outside the first placement region, on the second surface relative with first surface of mainboard
With a second pin be connected for one the second contact by the wire of bar second, every second wire.
3. device according to claim 1, is wherein also formed with least two first location holes on mainboard,
Described device also includes：
Pressing plate, is formed with least two second location holes corresponding with the first location hole of mainboard on pressing plate, and
At least two alignment pins, for being inserted into the first and second location holes,
When chip is placed in the first placement region of mainboard and covers pressing plate, the first location hole and the second location hole are distinguished
Alignment, and the first and second location holes are inserted into by alignment pin, by chip positioning in the first placement region.
4. device according to claim 3, is also formed with its center platen：
The second placement region corresponding with the main body of chip,
Around the second placement region and multiple 3rd pins corresponding with multiple pins difference of chip,
Multiple 3rd contacts outside the second placement region, and
A plurality of privates, every privates by the 3rd pin and the 3rd contact portion,
Wherein when chip is placed in the second placement region, multiple pins of chip are in contact with multiple 3rd pins respectively.
5. device according to claim 3, also includes：
Fixture, when chip is placed in the first placement region of mainboard and covers pressing plate, using fixture by mainboard and
Pressing plate and chip sandwiched therebetween are fixed.
6. device according to claim 4, wherein the second placement region is formed to accommodate the recessed of chip or opening.
7. device according to claim 1 and 2, also includes：
Location-plate, is formed with location-plate
The opening of chip can be accommodated, and
At least two the 3rd location hole corresponding with least two first location holes of mainboard；
When chip is placed in the first placement region of mainboard and covers location-plate, the first location hole and the 3rd location hole are distinguished
Alignment, chip is contained in the opening of location-plate, and is inserted into first and the 3rd location hole by alignment pin, and chip positioning is existed
First placement region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621116876.3U CN206209066U (en) | 2016-10-12 | 2016-10-12 | For chip testing and the device of programming |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621116876.3U CN206209066U (en) | 2016-10-12 | 2016-10-12 | For chip testing and the device of programming |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206209066U true CN206209066U (en) | 2017-05-31 |
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ID=58760971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621116876.3U Active CN206209066U (en) | 2016-10-12 | 2016-10-12 | For chip testing and the device of programming |
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| CN (1) | CN206209066U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018068627A1 (en) * | 2016-10-12 | 2018-04-19 | 肖敏 | Apparatus for chip testing and programming, and manufacturing method therefor |
-
2016
- 2016-10-12 CN CN201621116876.3U patent/CN206209066U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018068627A1 (en) * | 2016-10-12 | 2018-04-19 | 肖敏 | Apparatus for chip testing and programming, and manufacturing method therefor |
| CN107942223A (en) * | 2016-10-12 | 2018-04-20 | 肖敏 | Device and its manufacture method for chip testing and programming |
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