CN205864458U - A kind of counter modulation phaselocked loop carrier synchronization circuitry - Google Patents
A kind of counter modulation phaselocked loop carrier synchronization circuitry Download PDFInfo
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- CN205864458U CN205864458U CN201620712168.XU CN201620712168U CN205864458U CN 205864458 U CN205864458 U CN 205864458U CN 201620712168 U CN201620712168 U CN 201620712168U CN 205864458 U CN205864458 U CN 205864458U
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Abstract
The utility model discloses a kind of counter modulation phaselocked loop carrier synchronization circuitry, comprising: phase-locked loop circuit, demodulator circuit, phase-shift circuit and counter modulation unit, wherein, input signal is divided into two-way, one tunnel is input to phase-locked loop circuit, and another road is input to demodulator circuit；One tunnel input signal is divided into two-way the first output signal through phase-locked loop circuit, one tunnel is input to demodulator circuit, exporting the second output signal after one tunnel input signal and road the first output signal demodulated circuit demodulation, another road first output signal exports the 3rd output signal after phase-shift circuit；Second output signal and the 3rd output signal export the 4th output signal after counter modulation unit counter modulation；4th output signal is input in phase-locked loop circuit.Counter modulation phaselocked loop carrier synchronization circuitry of the present utility model, circuit design the most easily realizes, and is affected less by peripheral components, distributed capacitor etc., and it is short that carrier synchronization sets up the time, synchronizes maintenance ability strong.
Description
Technical field
This utility model relates to space technology field, particularly to a kind of counter modulation phaselocked loop carrier synchronization circuitry.
Background technology
The carrier wave of digital modulation or subcarrier signal, the form of the phase-shift keyed signal that many employing anti-interferences are stronger.Press
According to signal detection theory, may be constructed, with phaselocked loop, the phase-shift keyed signal Optimal coherent detection device that average error rate is minimum.Phase
Than amplitude-shift keying (ASK).Frequency shift keying (FSK), has the advantages that capacity of resisting disturbance is strong.Therefore, current spacecraft is surveyed with ground
The communication of control station uses phase-shift keyed signal more.
Phase-shift keyed signal carrier synchronization is set up the time by spacecraft and maintenance ability has the high requirement of comparison, as want
Step of the seeking common ground time of setting up is not more than 128bit, maintains ability not less than 32bit.
Utility model content
This utility model, for above-mentioned problems of the prior art, proposes a kind of counter modulation phaselocked loop carrier synchronization electricity
Road, circuit design the most easily realizes, and its track band, capture zone performance parameter are affected relatively by peripheral components, distributed capacitor etc.
Little, it is short that carrier synchronization sets up the time, synchronizes maintenance ability strong.
For solving above-mentioned technical problem, this utility model is achieved by the following technical solution:
This utility model provides a kind of counter modulation phaselocked loop carrier synchronization circuitry, comprising: phase-locked loop circuit, demodulation electricity
Road, phase-shift circuit and counter modulation unit, wherein,
Described input signal is divided into two-way, and input signal described in a road is input to described phase-locked loop circuit, and another road inputs
Signal is input to described demodulator circuit；
Input signal described in one tunnel is divided into two-way the first output signal through described phase-locked loop circuit, and described in a road, first is defeated
Going out signal and be input to described demodulator circuit, described in input signal described in a road and a road, the first output signal is through described demodulation
Exporting the second output signal after circuit demodulation, it is defeated that the first output signal described in another road exports the 3rd after described phase-shift circuit
Go out signal；
Described second output signal and described 3rd output signal export after described counter modulation unit counter modulation
Four output signals；
Described 4th output signal is input in described phase-locked loop circuit.
It is preferred that described phase-locked loop circuit includes: phase discriminator, loop filter and the voltage controlled oscillator being sequentially connected with,
Described phase discriminator is the input of described phase-locked loop circuit, and described voltage controlled oscillator is the outfan of described phase-locked loop circuit.
It is preferred that described phase-locked loop circuit is phase-locked loop intergrated circuit CD4046.
It is preferred that described input signal is binary phase shift keying signal (BPSK), BPSK coherent demodulation technology is anti-interference
Ability is strong.
It is preferred that described phase-shift circuit isPhase-shift circuit.
Compared to prior art, this utility model has the advantage that
(1) the counter modulation phaselocked loop carrier synchronization circuitry that this utility model provides, simple circuit easily realizes, and track band, catches
Obtain band performance parameter and affected by peripheral components, distributed capacitor etc. little, phase-shift keyed signal carrier synchronization set up the time short, synchronize
Maintenance ability is long, synchronize set up the time less than 4bit, synchronize maintenance ability can reach more than 640bit；
(2) in counter modulation phaselocked loop carrier synchronization circuitry of the present utility model between phase-locked loop circuit and counter modulation unit
AddPhase-shift circuit, for eliminating phase-locked loop circuit selfPhase contrast, carrier synchronization performance is more preferable.
Certainly, implement arbitrary product of the present utility model to it is not absolutely required to reach all the above advantage simultaneously.
Accompanying drawing explanation
Below in conjunction with the accompanying drawings embodiment of the present utility model is described further:
Fig. 1 is the schematic diagram of counter modulation phaselocked loop carrier synchronization circuitry of the present utility model；
Fig. 2 is the schematic diagram of counter modulation phaselocked loop carrier synchronization circuitry of the present utility model；
Fig. 3 is embodiment of the present utility modelThe schematic diagram of phase-shift circuit；
Fig. 4 is embodiment of the present utility modelThe sequential chart of phase-shift circuit；
Fig. 5 is the schematic diagram of the demodulator circuit of embodiment of the present utility model；
Fig. 6 is the sequential chart of the demodulator circuit of embodiment of the present utility model.
Label declaration: 1-phase-locked loop circuit, 2-phase-shift circuit, 3-demodulator circuit, 4-counter modulation unit；11-phase discriminator,
12-loop filter, 13-voltage controlled oscillator.
Detailed description of the invention
Elaborating embodiment of the present utility model below, the present embodiment is being front with technical solutions of the utility model
Put and implement, give detailed embodiment and concrete operating process, but protection domain of the present utility model does not limits
In following embodiment.
In conjunction with Fig. 1-Fig. 5, counter modulation phaselocked loop carrier synchronization circuitry of the present utility model is described in detail, such as Fig. 1
It show its schematic diagram, comprising: phase-locked loop circuit 1, phase-shift circuit 2, demodulator circuit 3 and counter modulation unit 4, input signal
U1 (t) is divided into two-way, and a road is input in phase-locked loop circuit 1, and a road input signal and road first output signal are through solving
Exporting the second output signal U 3 (t) after adjusting circuit 3 demodulation, an other road is input in demodulator circuit 3, and phase-locked loop circuit 1 exports
First via output signal U 2 (t), the first output signal U 2 (t) is divided into two-way, and a road is input to demodulator circuit 3, and another road inputs
ArrivePhase-shift circuit 2, another road is input to demodulator circuit 3, and phase-shift circuit 2 is used for eliminating the phase contrast of phase-locked loop circuit 1 self,
Export the 3rd output signal U 4 (t)；Second output signal U 3 (t) and the 3rd output signal U 4 (t) are input in counter modulation unit 4
Export the 4th output signal U 5 (t) after counter modulation, be then input in phase-locked loop circuit 1.
In the present embodiment, phase-locked loop circuit 1 includes phase discriminator 11, loop filter 12 and the VCO being sequentially connected with
Device (VCO) 13, phase discriminator 11 is the input of input signal and the 4th output signal, and voltage controlled oscillator 13 is the first output signal
Outfan.
Being illustrated in figure 2 the schematic diagram of the carrier synchronization circuitry of the present embodiment, in the present embodiment, phase-locked loop circuit 1 uses
Phase-locked loop intergrated circuit CD4046, counter modulation unit 4 is XOR gate, as it can be seen, input signal is bpsk signal, by phaselocked loop
After the output signal of the voltage controlled oscillator 13 of circuit 1 and the output signal of demodulator circuit 3 carry out XOR, send phase-locked loop circuit 1
Relatively end COMP IN carries out feedback ratio relatively, thus realizes the counter modulation of phase-locked loop circuit 1, can be obtained by debugging R1* and R2*
Taking the parameter of track band, debugging R3* and R4* can obtain the parameter of capture zone.The schematic diagram of the phase-shift circuit 2 of the present embodiment is such as
Shown in Fig. 3, the phase-shift circuit of the present embodiment isPhase-shift circuit, is used for eliminating phaselocked loopPhase contrast, frequency is the signal of 2CP
Obtain signal CP, signal CP after d type flip flop two divided-frequency and obtain signal CPX with 2CP XOR, then CPX is signal CP phase shift's
Signal, its phase shift sequential is as shown in Figure 4.The schematic diagram of the demodulator circuit 3 of the present embodiment is as it is shown in figure 5, CP is the relevant of extraction
Carrier wave, it is with modulated signal BPSK with frequency homophase, and analog switch gates low level signal and BPSK letter under the control of CP respectively
Number, thus produce signal A, gate low level when CP is high level, gate bpsk signal when CP is low level.Signal A with
Signal B carries out computing and obtains signal C, C=2A-B, and C signal filters out two frequency multiplication compositions of subcarrier, then after low pass
The bit rate square-wave signal D after a shaping, the pcm stream that machine demodulates is produced by amplitude limiter circuit；The ripple of the signal of each point
Shape is as shown in Figure 6.The carrier synchronization performance of the phaselocked loop carrier synchronization circuitry of the present embodiment is when test carrier synchronization is set up
Between less than 4bit, carrier synchronization maintains ability can reach more than 640bit.
Below in conjunction with concrete formula, its principle is described, if input signal bpsk signal is:
U1 (t)=m (t) sin (ω0t+θ1)；
Wherein, m (t) is modulation function, takes ± 1, ω0For carrier frequency, θ1For carrier wave initial phase；
U2 (t) is the coherent carrier extracted, then:
U2 (t)=sin (ω0t+θ2)；
Then:
U3 (t)=U1 (t) U2 (t)=Kdm(t)cos(θ1-θ2)=± Kdcos(θ1-θ2)；
Ignore second harmonic term, KdFor demodulator gain, through amplitude limit, (θ1-θ2) just take at Isosorbide-5-Nitrae quadrant, 2,3 quadrants
Take negative.
U2 (t) phase shiftThen:
U4 (t)=cos (ω0t+θ2)；
U5 (t)=U3 (t) U4 (t)=± Kdm(t)cos(ω0t+θ2)；
U6 (t)=U1 (t) U5 (t)=± Kdm2(t)sin(θ1-θ2)=± Kdsin(θ1-θ2)；
Ignore second harmonic term, (θ1-θ2) just take at Isosorbide-5-Nitrae quadrant, 2,3 quadrants take negative.
As the above analysis, loop error control voltage U6 (t) be change in polarity with signal modulation function m (t) without
Closing, it is only in accordance with phase contrast (θ1-θ2) change control VCO frequency.The coherent carrier that U2 (t) position is extracted, U3 (t) is exactly
Demodulation modulated signal m (t) out, therefore can use Design of PLL carrier synchronization circuitry according to this principle.But at BPSK
In signal, carrier component is suppressed, it is impossible to directly extract with reference to phase from phase-modulated signal with phaselocked loop or narrow band filter
Position carrier wave, first changes self simultaneously and existsPhase contrast, therefore, the present embodiment, while design phaselocked loop, devises corresponding
Phaselocked loop auxiliary circuit, by demodulator circuit 3 and counter modulation unit 4, phase-modulated signal is carried out Nonlinear Processing, eliminates
Phase-modulated information recovers the parameter containing reference phase information, is then purified, and produces the necessary ginseng of relevant detection
Examine phase carrier U5 (t), thus realize carrier synchronization；Devise simultaneouslyPhase-shift circuit 2, to eliminate phaselocked loop selfPhase place
Difference.
In the counter modulation phaselocked loop carrier synchronization circuitry of the present embodiment, input signal is carried out instead by demodulation signal out
Modulation, both offsets the modulation received in signal, can reduce the modulation degree of signal, recovers portion of carriers component, by phaselocked loop
This carrier component of circuit extraction, the coherent carrier extracted, in addition to for output, is supplied to the most again coherent demodulation and is used；Due to
The error control voltage of phase-locked loop circuit 1 is unrelated with the change in polarity of signal demodulation function, and it is only in accordance with phase contrast (θ1-θ2)
Change controls the frequency of voltage controlled oscillator, thus realizes carrier synchronization, carrier synchronization superior performance.
Disclosed herein is only preferred embodiment of the present utility model, and this specification is chosen and specifically described these and implements
Example, is to preferably explain principle of the present utility model and actual application, is not to restriction of the present utility model.Any
The modifications and variations that skilled person is done in the range of description, all should fall in the range of this utility model is protected.
Claims (5)
1. a counter modulation phaselocked loop carrier synchronization circuitry, it is characterised in that including: phase-locked loop circuit, demodulator circuit, phase shift electricity
Road and counter modulation unit, wherein,
Input signal is divided into two-way, and input signal described in a road is input to described phase-locked loop circuit, another road input signal input
To described demodulator circuit；
Input signal described in one tunnel is divided into two-way the first output signal through described phase-locked loop circuit, the first output letter described in a road
Number being input to described demodulator circuit, described in input signal described in a road and a road, the first output signal is through described demodulator circuit
Exporting the second output signal after demodulation, the first output signal described in another road exports the 3rd output letter after described phase-shift circuit
Number；
It is defeated that described second output signal and described 3rd output signal export the 4th after described counter modulation unit counter modulation
Go out signal；
Described 4th output signal is input in described phase-locked loop circuit.
Counter modulation phaselocked loop carrier synchronization circuitry the most according to claim 1, it is characterised in that described phase-locked loop circuit bag
Including: phase discriminator, loop filter and the voltage controlled oscillator being sequentially connected with, described phase discriminator is the input of described phase-locked loop circuit
End, described voltage controlled oscillator is the outfan of described phase-locked loop circuit.
Counter modulation phaselocked loop carrier synchronization circuitry the most according to claim 1, it is characterised in that described phase-locked loop circuit is
Phase-locked loop intergrated circuit CD4046.
Counter modulation phaselocked loop carrier synchronization circuitry the most according to claim 1, it is characterised in that described input signal is two
System phase-shift keyed signal.
Counter modulation phaselocked loop carrier synchronization circuitry the most according to claim 1, it is characterised in that described phase-shift circuit is
Phase-shift circuit.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106907999A (en) * | 2017-05-04 | 2017-06-30 | 合肥工业大学 | A kind of grating sensor displacement measurement system based on phase-modulation |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106907999A (en) * | 2017-05-04 | 2017-06-30 | 合肥工业大学 | A kind of grating sensor displacement measurement system based on phase-modulation |
| CN106907999B (en) * | 2017-05-04 | 2019-11-15 | 合肥工业大学 | A kind of grating sensor displacement measurement system based on phase-modulation |
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