CN205304755U - A asymmetric time -delay device that is used for asynchronous circuit four -phase position agreement of shaking hands - Google Patents
A asymmetric time -delay device that is used for asynchronous circuit four -phase position agreement of shaking hands Download PDFInfo
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- CN205304755U CN205304755U CN201521001680.5U CN201521001680U CN205304755U CN 205304755 U CN205304755 U CN 205304755U CN 201521001680 U CN201521001680 U CN 201521001680U CN 205304755 U CN205304755 U CN 205304755U
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Abstract
The utility model discloses a can be used to asynchronous circuit four -phase position shake hands the agreement asymmetric delay circuit device. The device contains time delay logic circuit and feedback control circuit, wherein the feedback control circuit contains the first input end, second input and third input, the symmetrical control signal of first input end and input is connected, the second input is connected with time delay logic circuit's output, the output feedback connection of third input and asymmetric time -delay device, the feedback control circuit is according to the input of first input end and second input and the feedback input of third input, produce an asymmetric control signal at the output. The utility model discloses when reliably realizing asymmetric time delay function, can make the fast reaction to the follow -up data processing request of asynchronous circuit to asymmetric delay characteristic's inefficacy has been avoided.
Description
Technical field
The invention belongs to the super large-scale integration of Microelectronics and Solid State Electronics, relate to a kind of asymmetric time-delay mechanism, especially a kind of asymmetric time-delay mechanism for asynchronous circuit four phase place Handshake Protocol.
Background technology
In modern integrated circuits design, generally adopt the asynchronous circuit eliminating global clock signal. Asynchronous circuit utilizes data to send the Handshake Protocol between level and data receiver stage, relieves the restriction to circuit performance of the global clock signal such that it is able to plays every level one data and processes the peak performance of circuit.
Fig. 1 is simple asynchronous circuit structural representation, wherein CaAnd CbFor combinational circuit, for realizing the calculation function of this level production line. RaAnd RbRepresent depositor, for depositing the operation result of this level production line. CaAnd RaThe first order of composition streamline, CbAnd RbThe second level of composition streamline. The control unit of ctrl_a and ctrl_b respectively first order streamline and second level streamline. Control unit can accept request signal that previous stage streamline sends and provide feedback signal, produces to drive the local clock pulses of depositor at the corresponding levels simultaneously, and sends request signal to rear stage streamline and accept the feedback signal of rear stage streamline.
Asynchronous circuit generally adopts four phase place Handshake Protocols, utilizes level height to represent request signal, it is easy to the design of circuit realizes. The process of four phase place Handshake Protocols controls, as in figure 2 it is shown, req signal represents certain one-level, the request signal that module sends, and ack represents the feedback signal that this control module receives.
Such as circuit shown in Fig. 1, after first order pipeline control unit ctrl_a receives the req request signal that previous stage streamline is sent, produces local clock pulses and the data received is stored in depositor RaIn, and ack feedback signal is set to 1, it was shown that this request is received, and produces req request signal simultaneously and gives second level streamline. Second level pipeline control unit ctrl_b receives req request signal, if RbBe in idle condition, then crtl_b will produce this locality signal clk_b all the time immediately and data are latched in RbIn.Previous stage streamline receives ack feedback signal and then req request signal is set to 0, and req signal is resetted, and ack feedback signal is set to 0 by first order streamline accordingly, and ack signal is resetted.
In this asynchronous circuit, RaThe data of output arrive RbInput before, combinational circuit C can be first passed aroundbCarry out a series of computing, and combination logic CbTime delay can not ignore. Therefore, in four phase place Handshake Protocols, when request signal is become high level from low level, it was shown that have new request signal to produce, now need to adopt delay unit to combinational logic circuit CbCarry out time delay coupling; And when request signal is changed into low level by high level, show whole handshake is resetted, now circuit only has and control part work, and data operation part is without any effective work, therefore, request signal is become low level process without carrying out time delay coupling from high level. It is to say, delay unit needs the rising edge of input signal is carried out time delay, the trailing edge for signal then quickly can transmit without time delay, namely realizes asymmetric time delay. A kind of conventional asymmetric delay unit disclosed in patent documentation CN1855080A. As it is shown on figure 3, wherein A is input signal, Y is output signal. Input signal A is divided into two-way, and a road is directly connected to an input I1 of two inputs " with door ", and another road signal is connected to another input I0 of two inputs " with door " again after then first passing around delay unit dly1. As shown in Figure 4, by regulating the time delay t1 of dly1 unit, it is possible to regulating this circuit time delay t1+t2 to the rising edge of input signal A, the time delay to trailing edge is t2. Namely the transmission delay of this circuit rising edge and trailing edge for inputting signal A is asymmetric.
But, in asynchronous circuit, it is necessary to accelerate the signal reseting procedure in Handshake Protocol, after data sending terminal receives the ack signal reset message that data receiver returns, it should new request can be sent immediately, thus improving the efficiency of signal processing. In this case, as shown in Figure 4, due to t3 < t1 time delay between second rising edge of a-signal and first trailing edge, namely before second rising edge arrives, signal b in circuit is not up to steady statue, therefore circuit also loses the long delay characteristic to second rising edge of a-signal, and the asymmetric property of this delay unit will disappear. Therefore, existing this delay unit is not used to the four phase place Handshake Protocols realizing asynchronous circuit.
Summary of the invention
Problem existing during in view of current asymmetric delay circuit for asynchronous circuit four phase place Handshake Protocol, the present invention proposes a kind of new asymmetric time-delay mechanism, while realizing asymmetric delay function, the follow-up data of asynchronous circuit can be processed request and make fast reaction, thus solving the problem that general asymmetric delay circuit time-delay characteristics lost efficacy.
The present invention provides a kind of asymmetric time-delay mechanism for asynchronous circuit four phase place Handshake Protocol, it is characterized in that, described asymmetric time-delay mechanism comprises relay logic and feedback control circuit, and wherein, the input of described relay logic is connected with the symmetric control signals of input; Described feedback control circuit comprises first input end, the second input and the 3rd input, described first input end is connected with the symmetric control signals of input, described second input is connected with the outfan of described relay logic, the outfan feedback link of described 3rd input and described asymmetric time-delay mechanism, the feed back input of the input according to first input end and the second input of the described feedback control circuit and the 3rd input, produces an asymmetrical control signal at outfan.
Wherein, the rising edge of asymmetrical control signal of described asymmetric time-delay mechanism output, and the time delay between the rising edge of the symmetric control signals of input be t1; The trailing edge of asymmetrical control signal of described asymmetric time-delay mechanism output, and the time delay between the trailing edge of the symmetric control signals of input be t2, wherein t2 < t1.
Wherein, after trailing edge occurs in the asymmetrical control signal of output, the time delay between trailing edge and the next rising edge of the symmetric control signals of input is t3, wherein t3 < t1.
Wherein, described relay logic comprises multiple delay unit, and each described delay unit is selected from any one unit following or its combination: buffer, reverser or transmission gate.
Wherein, described feedback control circuit includes a reverser (dly2), three inputs input or door (dly5) with door (dly4) and one two with door (dly3), two inputs, the outfan of the input of described phase inverter (dly2) and described relay logic (dly1) is connected with each other, as described second input of described feedback control circuit, described three inputs are connected with each other with the outfan of described reverser (dly2) with first input (I0) of door (dly3), described three inputs are connected with each other with the outfan of described relay logic (dly1) with second input (I1) of door (dly3), described three inputs are connected with each other with described two first input inputted with door (dly4) with the 3rd input (I2) of door (dly3), it is connected with each other with the input of described relay logic (dly1) simultaneously, described first input end as described feedback control circuit, described two inputs and second input of door (dly4) input with described two or the outfan of door (dly5) is connected with each other, as described 3rd input of described feedback control circuit, first input of described two inputs or door (dly5) is connected with each other with described three outfans inputted with door (dly3), second input of described two inputs or door (dly5) is connected with each other with described two outfans inputted with door dly4, the outfan of described two inputs or door (dly5) is the outfan of described feedback control circuit, and output is for the asymmetrical control signal of asynchronous circuit.
Wherein, described feedback control circuit includes the first reverser (dly2), three inputs and door (dly3), first liang of input and door (dly4), first liang of input or door (dly5), the second reverser (dly7), second liang of input and door (dly8) and second liang of input or door (dly9), the input of described first phase inverter (dly2) and the outfan of described relay logic (dly1) are connected with each other, as described second input of described feedback control circuit, described three inputs and first input (I0) of door (dly3) input with described second liang or the outfan of door (dly9) is connected with each other, described three inputs are connected with each other with the outfan of described relay logic (dly1) with second input (I1) of door (dly3), described three inputs are connected with each other with described first liang of first input inputted with door (dly4) with the 3rd input (I2) of door (dly3), and be connected with each other with the input of described relay logic (dly1) simultaneously, described first input end as described feedback control circuit, described first liang of input and second input of door (dly4) input with described first liang or the outfan of door (dly5) is connected with each other, as described 3rd input of described feedback control circuit,Described second liang of input and first input of door (dly8) input with described second liang or the outfan of door (dly9) is connected with each other, and described first liang of input is connected with each other with the outfan of described second reverser (dly7) with second input of door (dly8); First input of described second liang of input or door (dly9) is connected with each other with described second liang of outfan inputted with door (dly8), and described second liang of input or second input of door (dly9) are connected with each other with the outfan of described first reverser (dly2); First input of described first liang of input or door (dly5) is connected with each other with described three outfans inputted with door (dly3), second input of described first liang of input or door (dly5) is connected with each other with described first liang of outfan inputted with door (dly4), the outfan of described first liang of input or door (dly5) is the outfan of described feedback control circuit, and output is for the asymmetrical control signal of asynchronous circuit.
Accompanying drawing explanation
Fig. 1 is the basic structure schematic diagram of existing asynchronous circuit;
Fig. 2 is the schematic diagram of existing asynchronous circuit four phase place Handshake Protocol;
Fig. 3 is the simple asymmetric delay unit principle model schematic diagram of existing one;
Fig. 4 is the working waveform figure of existing asymmetric delay unit;
Fig. 5 is the asymmetric time delay circuit unit electrical block diagram for asynchronous circuit four phase place Handshake Protocol of first embodiment of the invention;
Fig. 6 is the working waveform figure of the asymmetric time delay circuit unit of first embodiment of the invention;
Fig. 7 is the asymmetric time delay circuit unit electrical block diagram for asynchronous circuit four phase place Handshake Protocol of second embodiment of the invention.
Detailed description of the invention
The first embodiment of a kind of novel asymmetric delay circuit device that can be used for asynchronous circuit four phase place Handshake Protocol that the present invention proposes, particular circuit configurations is as shown in Figure 5. This circuit introduces feedback loop on the basis of the circuit shown in Fig. 3, it is possible to solve the problem that the circuit shown in Fig. 3 cannot directly apply to four phase protocols.
In this circuit, a reverser (dly2 unit), three inputs and door (dly3 unit), two inputs and door (dly4 unit) and one two input or door (dly5 unit) constitute feedback control circuit.
In circuit, dly0 unit is isolation buffers, and main purpose is the port isolation of the internal constraint of circuit Yu circuit to be opened, and conveniently arranges constraint when automatic Synthesis for this circuit. Dly1 is the adjustable delay unit of time delay, is made up of one or more buffers. The input of dly1 unit comes from the output of dly0 unit. Dly2 unit is a phase inverter, for being negated by the digital signal of input. The input of dly2 unit comes from the output of dly1 unit. Dly3 unit be one three input and door, its three inputs I0, I1, I2 respectively with the output of dly2 unit, the output of dly1 unit, dly0 unit output be connected. Dly4 unit be one two input with door, two input I0, I1 are connected with the output of the output of dly0 unit, dly5 unit respectively. Dly5 unit is one two input or door, and two input I0, I1 are connected with the output of the output of dly3 unit, dly4 unit respectively.
The work process of this circuit is as follows, inputting signal A and output signal Y during original state is all low level, therefore the input I1 of dly4 unit is also low level, and the inverting function of dly2 unit makes signal d (the I0 input of dly3 unit) be high level.If now input signal A becomes high level, after the time delay of dly0 unit, signal b becomes high level, the I0 input of dly4 unit and the I2 input of dly3 unit is made to become high level, but owing to the I1 of dly4 unit is low level, so dly4 unit is output as low level, dly3 unit also output low level. Signal b is after the delay of dly1 unit, and the I1 input of dly3 unit also becomes high level, and now three inputs of dly3 unit will all become high level, causes that dly3 unit output f becomes high level, thus signal Y exports high level. Once output signal Y becomes high level, the I1 end of dly4 unit will become high level, make dly4 unit output e become high level. When the rising edge of a-signal is delivered to the I0 end of dly3 unit through dly2 unit, I0 input will become low level, so that the output f of dly3 unit becomes low level. But now the output e of dly4 unit has changed into high level, therefore output signal Y will keep high level. If now input signal A becomes low level, the I0 end of dly4 unit and the I2 end of dly3 unit will become low level after the delay through dly0 unit, cause dly3 unit and the equal output low level of dly4 unit, so that output Y becomes low level. From analyzing above, the delay postponing many dly1 unit when retardation ratio during this delay cell transmission rising edge transmits trailing edge, that is the delay having only to change dly1 unit just can regulate the delay cell delay to signal rising edge according to demand, and keeps this unit that the delay of signal trailing edge is constant.
The shortcoming that the introducing of dly2 unit can effectively solve circuit shown in Fig. 3. If after input signal Y is become low level from high level, input signal A quickly becomes high level, now due to the delay action of dly1 unit, a upper trailing edge of input signal A does not also pass to the I1 end of dly3 unit, namely signal c remains as high level, here it is circuit shown in Fig. 3 cannot the reason of normal operation. And due to the existence of dly2 rp unit in this circuit, the I0 input making dly3 unit is 0, therefore dly3 unit will keep output low level, and namely the rapid increase of a-signal will not cause the rapid increase of output signal Y. Until a upper trailing edge of a-signal is transferred to the I0 end of dly3 unit through dly1 unit and dly2 rp unit, I0 end is made to become high level, then second rising edge of signal A is sent to the I1 end of dly3 unit through dly1 unit, and the output Y of delay unit just can be made to uprise. Therefore, this circuit overcomes the shortcoming of circuit shown in Fig. 3, and each rising edge of input signal A is required for just to be sent to output signal Y through dly1 unit. Fig. 6 illustrates the work wave of this circuit.
Second embodiment of the asymmetric delay circuit device that can be used for asynchronous circuit four phase place Handshake Protocol that the present invention proposes, particular circuit configurations is as shown in Figure 7.
In this circuit, the first reverser (dly2 unit), three inputs and door (dly3 unit), first liang of input and door (dly4 unit), first liang of input or door (dly5 unit), the second reverser (dly7 unit), second liang of input and door (dly8 unit) and second liang of input or door (dly9 unit) constitute feedback control circuit.
In circuit, dly0 unit is isolation buffers, and main purpose is the port isolation of the internal constraint of circuit Yu circuit to be opened, and conveniently arranges constraint when automatic Synthesis for this circuit.Dly1 is the adjustable delay unit of time delay, is made up of one or more buffers, or by one or more pairs of phase inverters to forming. The input of dly1 unit comes from the output of Dly0 unit. Dly2 unit is a phase inverter, for being negated by the digital signal of input. The input of Dly2 unit comes from the output of Dly1 unit. Dly3 unit be one three input and door, its three inputs I0, I1, I2 respectively with the output of dly9 unit, the output of dly1 unit, dly0 unit output be connected. Dly4 unit be one two input with door, two input I0, I1 are connected with the output of the output of dly0 unit, dly5 unit respectively. Dly5 unit is one two input or door, and two input I0, I1 are connected with the output of the output of dly3 unit, dly4 unit respectively. Dly7 unit is a phase inverter, and its input comes from the output of dly5 unit. Dly8 unit be one two input with door, two input I0, I1 are connected with the output of the output of dly9 unit, dly7 unit respectively. Dly9 unit is one two input or door, and two input I0, I1 are connected with the output of the output of dly8 unit, dly2 unit respectively.
In a second embodiment, the output signal d of dly2 unit is not directly accessed the I0 end of dly3 unit, but accesses the I0 end of dly3 unit by producing signal k after two input disjunction gates. The signal of another input I0 of disjunction gate comes from the output of dly8 unit, and the input of dly8 unit is then the feedback feedback with k signal of Y-signal respectively. This arrangement avoid Y-signal when just becoming high level, if the time delay of dly2 is comparatively short, d signal can quickly become low level, thus f signal becomes low level situation. If now Y-signal fails to be locked in dly4 unit, Y-signal will become low level again. After introducing dly9 unit, when d signal becomes low level, if now Y-signal is still low level, then k signal will keep high level, thus maintaining signal f is high level, until Y-signal becomes high level, the low level signal of dly2 unit output just can arrive the I0 end of dly3 unit through dly9 unit. Further, since signal Y will be greater than the signal Y time delay through dly4 unit through the time delay of dly8 and dly9 unit, it is hereby ensured that the high level of Y-signal has stably been latched in dly4 unit to dly3 unit through dly8 and dly9 transmission.
Claims (6)
1. the asymmetric time-delay mechanism for asynchronous circuit four phase place Handshake Protocol, it is characterized in that, described asymmetric time-delay mechanism comprises relay logic and feedback control circuit, and wherein, the input of described relay logic is connected with the symmetric control signals of input; Described feedback control circuit comprises first input end, the second input and the 3rd input, described first input end is connected with the symmetric control signals of input, described second input is connected with the outfan of described relay logic, the outfan feedback link of described 3rd input and described asymmetric time-delay mechanism, the feed back input of the input according to first input end and the second input of the described feedback control circuit and the 3rd input, produces an asymmetrical control signal at outfan.
2. asymmetric time-delay mechanism according to claim 1, wherein signal is t1 by the propagation delay time of described relay logic, and the time delay between the rising edge of the rising edge of the asymmetrical control signal of described asymmetric time-delay mechanism output and the symmetric control signals of input is t1+t2;Time delay between the trailing edge of the trailing edge of the asymmetrical control signal of described asymmetric time-delay mechanism output and the symmetric control signals of input is t2, wherein t2 < t1.
3. asymmetric time-delay mechanism according to claim 2, after there is trailing edge in the asymmetrical control signal of wherein said asymmetric time-delay mechanism output, time delay between trailing edge and the next rising edge of the symmetric control signals of input is t3, wherein t3 < t1.
4. asymmetric time-delay mechanism according to claim 1, wherein said relay logic comprises multiple delay unit, and each described delay unit is selected from any one unit following or its combination: buffer, reverser or transmission gate.
5. asymmetric time-delay mechanism according to claim 1, wherein said feedback control circuit includes a reverser (dly2), three inputs input or door (dly5) with door (dly4) and one two with door (dly3), two inputs, the outfan of the input of described phase inverter (dly2) and described relay logic (dly1) is connected with each other, as described second input of described feedback control circuit, described three inputs are connected with each other with the outfan of described reverser (dly2) with first input (I0) of door (dly3), described three inputs are connected with each other with the outfan of described relay logic (dly1) with second input (I1) of door (dly3), described three inputs are connected with each other with described two first input inputted with door (dly4) with the 3rd input (I2) of door (dly3), it is connected with each other with the input of described relay logic (dly1) simultaneously, described first input end as described feedback control circuit, described two inputs and second input of door (dly4) input with described two or the outfan of door (dly5) is connected with each other, as described 3rd input of described feedback control circuit, first input of described two inputs or door (dly5) is connected with each other with described three outfans inputted with door (dly3), second input of described two inputs or door (dly5) is connected with each other with described two outfans inputted with door dly4, the outfan of described two inputs or door (dly5) is the outfan of described feedback control circuit, and output is for the asymmetrical control signal of asynchronous circuit.
6. asymmetric time-delay mechanism according to claim 1, wherein said feedback control circuit includes the first reverser (dly2), three inputs and door (dly3), first liang of input and door (dly4), first liang of input or door (dly5), the second reverser (dly7), second liang of input and door (dly8) and second liang of input or door (dly9), the input of described first phase inverter (dly2) and the outfan of described relay logic (dly1) are connected with each other, as described second input of described feedback control circuit, described three inputs and first input (I0) of door (dly3) input with described second liang or the outfan of door (dly9) is connected with each other, described three inputs are connected with each other with the outfan of described relay logic (dly1) with second input (I1) of door (dly3), described three inputs are connected with each other with described first liang of first input inputted with door (dly4) with the 3rd input (I2) of door (dly3), and be connected with each other with the input of described relay logic (dly1) simultaneously, described first input end as described feedback control circuit, described first liang of input and second input of door (dly4) input with described first liang or the outfan of door (dly5) is connected with each other, as described 3rd input of described feedback control circuit,Described second liang of input and first input of door (dly8) input with described second liang or the outfan of door (dly9) is connected with each other, and described first liang of input is connected with each other with the outfan of described second reverser (dly7) with second input of door (dly8); First input of described second liang of input or door (dly9) is connected with each other with described second liang of outfan inputted with door (dly8), and described second liang of input or second input of door (dly9) are connected with each other with the outfan of described first reverser (dly2); First input of described first liang of input or door (dly5) is connected with each other with described three outfans inputted with door (dly3), second input of described first liang of input or door (dly5) is connected with each other with described first liang of outfan inputted with door (dly4), the outfan of described first liang of input or door (dly5) is the outfan of described feedback control circuit, and output is for the asymmetrical control signal of asynchronous circuit.
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| CN201521001680.5U CN205304755U (en) | 2015-12-07 | 2015-12-07 | A asymmetric time -delay device that is used for asynchronous circuit four -phase position agreement of shaking hands |
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| CN201521001680.5U CN205304755U (en) | 2015-12-07 | 2015-12-07 | A asymmetric time -delay device that is used for asynchronous circuit four -phase position agreement of shaking hands |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105306022A (en) * | 2015-12-07 | 2016-02-03 | 北京理工大学 | Asymmetric time-delay apparatus used for asynchronous circuit four-phase handshake protocol |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105306022A (en) * | 2015-12-07 | 2016-02-03 | 北京理工大学 | Asymmetric time-delay apparatus used for asynchronous circuit four-phase handshake protocol |
| CN105306022B (en) * | 2015-12-07 | 2018-06-12 | 北京理工大学 | A kind of asymmetric time-delay mechanism for four phase Handshake Protocol of asynchronous circuit |
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Granted publication date: 20160608 Effective date of abandoning: 20180612 |