CN205263743U - Controllable reset circuit of bandwidth is released in step to asynchronous reseing - Google Patents
Controllable reset circuit of bandwidth is released in step to asynchronous reseing Download PDFInfo
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- CN205263743U CN205263743U CN201521082937.4U CN201521082937U CN205263743U CN 205263743 U CN205263743 U CN 205263743U CN 201521082937 U CN201521082937 U CN 201521082937U CN 205263743 U CN205263743 U CN 205263743U
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Abstract
The utility model discloses the controllable reset circuits of asynchronous reset synchronous release bandwidth, belong to the technical field of digital integrated electronic circuit. Reset circuit includes: delay counter circuit and output control circuit, and delay counter circuit includes N delay counter submodules. When the input of exterior asynchronous reset signal is low level, the reset signal for being output to internal system, which makes an immediate response, becomes low level, i.e., carries out reset operation to internal system; Become high level when exterior asynchronous reset signal is inputted from low level, i.e. release reset signal when, internal system need by
Synchronous release resets operation after a rising edge clock. The utility model has effectively filtered the release of short time external reset signal, enhances the reliability of reset signal, combines the reset mode of asynchronous reset, synchronous release.
Description
Technical field
The utility model discloses asynchronous reset and synchronously discharge the controlled reset circuit of bandwidth, belong to digital integrated electronic circuitTechnical field.
Background technology
In ASIC design, reset is a basic and important problem always, is conventionally divided into synchronous reset and asynchronousReset. Synchronous reset refers to that reset signal resets to trigger will wait for next clock effectively along arrival time, asynchronous multiplePosition does not need the arrival of waiting for the effective edge of next clock directly trigger to be resetted.
Synchronous reset and asynchronous reset respectively have pluses and minuses: synchronous reset is easily comprehensive, is convenient to Time-Series analysis, can reduce metastableThe probability that state occurs, but must be greater than a clock cycle effective period of synchronous reset signal, just can be sampled and carry out againPosition, and because the trigger in most cell library only has asynchronous reset port, adopt synchronous reset can expend moreLogical resource in addition, easily goes wrong when asynchronous reset signal discharges, even can produce metastable state; Asynchronous reset is notNeed clock, more save logical resource, but the complexity of asynchronous reset Time-Series analysis will be higher than synchronous reset.
So, in conjunction with both advantages, the nowadays synchronous reset discharging of most of ASIC design recommendation asynchronous resetMode. Granted publication number is that the patent of CN100549909C discloses a kind of asynchronous reset circuit and its implementation, employingThe input termination high level of two-stage trigger series connection and first order trigger, after reset signal discharges through on two clocksAfter rising edge, be input to the interior reset signal of system just with clock signal together synchronously release, synchronously discharge the trigger that bandwidth is connected in seriesThe restriction of number, if need to increase the synchronous bandwidth that discharges, can only increase the number of flip-flops in series, certainly will cause more moneySource waste.
Utility model content
Technical problem to be solved in the utility model is the deficiency for above-mentioned background technology, provides asynchronous reset sameStep discharges the controlled reset circuit of bandwidth, has realized asynchronous reset and has synchronously discharged the controlled of bandwidth, has solved in prior art differentThe technical problem of the restriction of the trigger number that the synchronous release bandwidth of step reset circuit is connected in series.
The utility model adopts following technical scheme for realizing above-mentioned utility model object:
Asynchronous reset synchronously discharges the controlled reset circuit of bandwidth, comprising: delay counter circuit and output control circuit,Described delay counter circuit comprises N position delay counter submodule, wherein,
The first input end of every delay counter submodule connects data output end separately, every delay counter submoduleThe clock port welding system clock signal of piece, the reseting port welding system external asynchronous of every delay counter submodule resets and believesNumber, the output of the second input termination output control circuit of the 1st delay counter submodule, the 2nd to N position time delay meterThe second input of number device submodule is connected with the carry signal output of its last position delay counter submodule respectively, outputThe data output end of the every delay counter submodule of input termination of control circuit, N is integer.
Synchronously discharge the further prioritization scheme of the controlled reset circuit of bandwidth as described asynchronous reset, the 1st time delayCounter submodule serve as reasons with or door and with the counting circuit of the d type flip flop composition of asynchronous reset port, wherein,
First input end same or door is connected as the first input end of this submodule and the data output end of d type flip flop,The second input same or door is connected with the output of output control circuit as the second input of this submodule, same or doorThe data input pin of output and d type flip flop also connects the carry signal output as this submodule, the clock signal of d type flip flopInput is as the clock port receiving system clock signal of this submodule, and the asynchronous reset end of d type flip flop is as this submoduleReseting port receiving system external asynchronous reset signal, the data output end of d type flip flop is connected with the input of control circuit.
Further, described asynchronous reset synchronously discharges in the controlled reset circuit of bandwidth, and the 2nd to the time delay of N-1 positionThe circuit structure of counter submodule is identical, includes described counting circuit and by phase inverter and or the carry electricity that forms of doorRoad, wherein, the input of phase inverter is connected with the data output end of d type flip flop, or input of door and phase inverter is defeatedGo out end connect, or door another input be connected with the data input pin of d type flip flop, or output as the 2nd extremelyThe carry signal output of arbitrary submodule in the delay counter submodule of N-1 position.
Further, described asynchronous reset synchronously discharges in the controlled reset circuit of bandwidth, N position delay counterModule is identical with the 1st delay counter submodular circuits structure.
Further, described asynchronous reset synchronously discharges in the controlled reset circuit of bandwidth, and output control circuit is that N is defeatedEnter AND circuit.
Synchronously discharge the further prioritization scheme of the controlled reset circuit of bandwidth as described asynchronous reset, the value of NBe 3.
The utility model adopts technique scheme, has following beneficial effect:
(1) the synchronous release circuit of asynchronous reset that the utility model relates to, has effectively filtered short time external reset signalDischarge, strengthened the reliability of reset signal;
(2) delay counter circuit can pass through the figure place N of extend flip-flop, make asynchronous reset signal discharge after throughAfter individual system clock rising edge, synchronously discharge, realize asynchronous reset and synchronously discharge the controlled of bandwidth.
Brief description of the drawings
Fig. 1 is the block diagram of the utility model reset circuit.
Fig. 2 realizes the synchronous reset circuit that discharges reset operation after 7 rising edge clocks in specific embodiment.
Fig. 3 is the simulation waveform schematic diagram of circuit shown in Fig. 2.
Number in the figure explanation: 101 for delay counter circuit, 102 for output control circuit, 103 be the first d type flip flop,104 be the second d type flip flop, 105 be 3d flip-flop, 106 be first with or door, 107 be second with or door, 108 be the 3rd withOr door, 109 is that two inputs or door, 110 are that phase inverter, 111 is three value and gate.
Detailed description of the invention
Below in conjunction with accompanying drawing, the technical scheme of utility model is elaborated.
The asynchronous reset that the utility model relates to synchronously discharges the controlled reset circuit of bandwidth as shown in Figure 1, comprising: time delayCounter circuit and output control circuit, described delay counter circuit comprises N position delay counter submodule, N is integer.The first input end of every delay counter submodule connects data output end separately, the clock of every delay counter submodulePort welding system clock signal, the reseting port welding system external asynchronous reset signal of every delay counter submodule, the 1stThe output of the second input termination output control circuit of delay counter submodule, the 2nd to N position delay counter submoduleThe second input of piece is connected with the carry signal output of its last position delay counter submodule respectively, output control circuitThe data output end of the every delay counter submodule of input termination. Output control circuit is N input AND circuit, can basisThe number of delay counter submodule realizes with multiple AND circuits.
The 1st delay counter submodule serve as reasons with or door and with the counting of the d type flip flop composition of asynchronous reset portCircuit. With or the first input end of door be connected as the first input end of this submodule and the data output end of d type flip flop, together orThe second input of door is connected with the output of output control circuit as the second input of this submodule, together or outputThe data input pin of end and d type flip flop also connects the carry signal output as this submodule, the clock signal input of d type flip flopEnd is as the clock port receiving system clock signal of this submodule, asynchronous reset end the answering as this submodule of d type flip flopBit port receiving system external asynchronous reset signal, the data output end of d type flip flop is connected with the input of control circuit.
The 2nd identical to the circuit structure of N-1 position delay counter submodule, includes and realize the 1st time delay countingThe counting circuit of device submodule and by phase inverter and or the circuits for carrying-over that forms of door. The input of phase inverter and d type flip flopData output end connects, or an input of door is connected with the output of phase inverter, or another input and D triggeringThe data input pin of device connects, or the output of door as the 2nd to arbitrary submodule in the delay counter submodule of N-1 positionCarry signal output.
N position delay counter submodule is identical with the 1st delay counter submodular circuits structure, because of highest order withoutCarry operation, so N position delay counter submodule can save circuits for carrying-over and carry signal output port.
In the time that N value is 3, reset circuit can be in synchronous release reset operation after 7 rising edge clocks, this resetCircuit as shown in Figure 2, delay counter circuit 101 and output control circuit 102, delay counter circuit 101 is with low by threeD type flip flop (the first d type flip flop 103, the second d type flip flop 104,3d flip-flop that level reset terminal, rising edge clock trigger105), and three two inputs with or door (first with or door 106, second with or door 107, the 3rd with or door 108), one two defeatedEnter or door 109 and a phase inverter 110 form. The data input pin of the first d type flip flop 103 and first with or door 106 outputEnd is connected, and the clock end of the first d type flip flop 103 is connected with system clock clk, outside the reset terminal and system of the first d type flip flop 103The asynchronous reset signal rst_async_n of portion is connected, the data output end of the first d type flip flop 103 with first with or 106 oneInput is connected, first with or door another input of 106 and the synchronous reset signal rst_sync_n that outputs to internal systemBe connected, the data input pin of the second d type flip flop 104 with second with or door 107 output be connected, the second d type flip flop 104 timeZhong Duanyu system clock clk is connected, the reset terminal of the second d type flip flop 104 and system external asynchronous reset signal rst_async_nBe connected, the data output end of the second d type flip flop 104 with second with or input of 107 and the input of phase inverter 110Be connected, second another input same or door 107 output same with first or door 106 is connected, 3d flip-flop 105Data input pin output same with the 3rd or door 108 is connected, the data output end of 3d flip-flop 105 and the 3rd same or doorAn input of 108 is connected, and the clock end of 3d flip-flop 105 is connected with system clock clk, 3d flip-flop 105Reset terminal is connected with system external asynchronous reset signal rst_async_n, and the 3rd another input and two same or door 108 is inputtedOr door 109 output is connected, the output of phase inverter 110 is connected with an input of two inputs or door 109, two input orAnother input of door 109 output same with second or door 107 is connected.
Output control circuit 102 is made up of a three value and gate 111. The input of three value and gate 111 respectively with prolongThe data output end of three d type flip flops in hour counter circuit 101 is connected; The output of three value and gate 111 and time delay meterThe first input same or door 106 in number device circuit 101 is connected, and to internal system output synchronous reset signal rst_sync_n。
Below in conjunction with the operation principle of reset circuit shown in the simulation waveform key diagram 2 of Fig. 3. System external asynchronous resets and believesNumber rst_async_n input time delay counter circuit 101, when system external asynchronous reset signal rst_async_n inputs from lowLevel becomes high level and discharges while reset, and the first d type flip flop 103, the second d type flip flop 104 and 3d flip-flop 105 are output asLow level, in the time that next first systematic clock clk rising edge arrives, the first d type flip flop 103 outputs become high level; TheWhen two system clock clk rising edges arrive, the first d type flip flop 103 outputs become low level, the second d type flip flop 104 outputs becomeFor high level, 3d flip-flop 105 keep low level; When the 3rd system clock clk rising edge arrives, the first d type flip flop103 outputs become high level, the second d type flip flop 104 outputs keep high level, 3d flip-flop 105 outputs to keep low level;When four systems clock clk rising edge arrives, the first d type flip flop 103 outputs become low level, the second d type flip flop 104 is exportedKeep low level, 3d flip-flop 105 outputs to keep high level; When the 5th system clock clk rising edge arrives, a D touchesHair device 103 outputs become high level, the second d type flip flop 104 outputs keep low level, 3d flip-flop 105 outputs to keep high electricityFlat; When the 6th system clock clk rising edge arrives, the first d type flip flop 103 outputs keep high level, the second d type flip flop 104Output becomes high level, 3d flip-flop 105 outputs become low level; When the 7th system clock clk rising edge arrives, theOne d type flip flop 103 outputs keep high level, the second d type flip flop 104 outputs to keep high level, 3d flip-flop 105 outputs to becomeFor high level, now because input and the first d type flip flop 103, the second d type flip flop 104, the 3rd D of three value and gate 111 touchThe data output end of hair device 105 is connected, and the output of three value and gate 111 input same with first or door 106 is connected,The output of three value and gate 111 will become high level, and remain height always, until system external asynchronous reset signal rst_Async_n input becomes low level again, and now internal system synchronous reset signal rst_sync_n will become height from low levelLevel, thus reset signal discharged.
In the time that system external asynchronous reset signal rst_async_n input becomes high level release reset from low level,Next before the 7th clock cycle, system external asynchronous reset signal rst_async_n inputs again step-down level againWhen reset, because the first d type flip flop 103, the second d type flip flop 104,3d flip-flop 105 are by asynchronous set, three value and gate111 output is that internal system synchronous reset signal rst_sync_n will be continuously low level, and does not discharge reset. This practicalityNovel filtration has fallen asynchronous reset signal too short deenergized period, has strengthened the synchronous stability discharging of asynchronous reset.
Circuit simulation waveform is as Fig. 3, and time point a place asynchronous reset is too short synchronous release time, and system external asynchronous resetsThe release signal of signal rst_async_n is filtered, and internal system synchronous reset signal rst_sync_n is not released; Reference diagram3, time point b place asynchronous reset exceedes 6 clock cycle, system external asynchronous reset signal rst_async_ synchronous release timeThe release signal of n can not be filtered, and internal system synchronous reset signal rst_sync_n is at the 7th system clock clk rising edgeBy accurate and stable release.
Visible, when system external asynchronous reset signal is input as low level, output to the reset signal of internal system immediatelyResponse becomes low level, internal system is carried out to reset operation; When the input of system external asynchronous reset signal is become by low levelFor high level, while discharging reset signal, internal system need to synchronously discharge reset operation after 7 rising edge clocks.
The rest may be inferred, will realize for the delay counter circuit of N position trigger compositionSame after individual rising edge clockStep discharges reset signal. Visible, delay counter circuit can pass through the figure place N of extend flip-flop, makes asynchronous reset signalAfter release throughAfter individual system clock rising edge, synchronously discharge, realize asynchronous reset and synchronously discharge the controlled of bandwidth.
Claims (6)
1. asynchronous reset synchronously discharges the controlled reset circuit of bandwidth, it is characterized in that, comprising: delay counter circuit and outputControl circuit, described delay counter circuit comprises N position delay counter submodule, wherein,
The first input end of every delay counter submodule connects data output end separately, every delay counter submoduleClock port welding system clock signal, the reseting port welding system external asynchronous reset signal of every delay counter submodule,The output of the second input termination output control circuit of the 1st delay counter submodule, counts to the time delay of N position for the 2ndThe second input of device submodule is connected with the carry signal output of its last position delay counter submodule respectively, output controlThe data output end of the every delay counter submodule of input termination of circuit processed, N is integer.
2. asynchronous reset according to claim 1 synchronously discharges the controlled reset circuit of bandwidth, it is characterized in that: the 1stDelay counter submodule serve as reasons with or door and with the counting circuit of the d type flip flop composition of asynchronous reset port, wherein,
With or the first input end of door be connected as the first input end of this submodule and the data output end of d type flip flop, together orThe second input of door is connected with the output of output control circuit as the second input of this submodule, together or outputThe data input pin of end and d type flip flop also connects the carry signal output as this submodule, the clock signal input of d type flip flopEnd is as the clock port receiving system clock signal of this submodule, asynchronous reset end the answering as this submodule of d type flip flopBit port receiving system external asynchronous reset signal, the data output end of d type flip flop is connected with the input of control circuit.
3. asynchronous reset according to claim 2 synchronously discharges the controlled reset circuit of bandwidth, it is characterized in that: the 2ndCircuit structure to N-1 position delay counter submodule is identical, include described counting circuit and by phase inverter and or doorThe circuits for carrying-over of composition, wherein, the input of phase inverter is connected with the data output end of d type flip flop, or an input of doorBe connected with the output of phase inverter, or door another input be connected with the data input pin of d type flip flop, or outputAs the 2nd the carry signal output to arbitrary submodule in the delay counter submodule of N-1 position.
4. asynchronous reset according to claim 3 synchronously discharges the controlled reset circuit of bandwidth, it is characterized in that: N positionDelay counter submodule is identical with the 1st delay counter submodular circuits structure.
5. synchronously discharge the controlled reset circuit of bandwidth, its spy according to the asynchronous reset described in any one in claim 1 to 4Levy and be: described output control circuit is N input AND circuit.
6. asynchronous reset according to claim 3 synchronously discharges the controlled reset circuit of bandwidth, it is characterized in that: N getsValue is 3.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521082937.4U CN205263743U (en) | 2015-12-22 | 2015-12-22 | Controllable reset circuit of bandwidth is released in step to asynchronous reseing |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201521082937.4U CN205263743U (en) | 2015-12-22 | 2015-12-22 | Controllable reset circuit of bandwidth is released in step to asynchronous reseing |
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| CN205263743U true CN205263743U (en) | 2016-05-25 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105425926A (en) * | 2015-12-22 | 2016-03-23 | 无锡芯响电子科技有限公司 | Controllable-bandwidth reset circuit capable of achieving asynchronous reset and synchronous release |
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2015
- 2015-12-22 CN CN201521082937.4U patent/CN205263743U/en not_active Withdrawn - After Issue
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105425926A (en) * | 2015-12-22 | 2016-03-23 | 无锡芯响电子科技有限公司 | Controllable-bandwidth reset circuit capable of achieving asynchronous reset and synchronous release |
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Granted publication date: 20160525 Effective date of abandoning: 20181102 |