CN205068388U - Receive DPHY serial signal's two frequency dividing circuit - Google Patents
Receive DPHY serial signal's two frequency dividing circuit Download PDFInfo
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- CN205068388U CN205068388U CN201520835522.3U CN201520835522U CN205068388U CN 205068388 U CN205068388 U CN 205068388U CN 201520835522 U CN201520835522 U CN 201520835522U CN 205068388 U CN205068388 U CN 205068388U
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Abstract
The utility model provides a receive DPHY serial signal's two frequency dividing circuit receives DPHY's output signal to to next frequency division processing, include: a DPHY receiver, the ware is forwardded to two difference registers and four at least difference, the clock signal phase place of two difference registers is opposite, a data signal output of two difference registers is respectively with rather than the data signal input phase -reversing connection that corresponds, other data signal outputs of two difference registers are connected respectively and with the data signal input that the ware was transmitted to other at least four difference. Utilize the DPHY receiver, two difference registers and four at least difference are forwardded the ware and are carried out two frequency division processing to DPHY's output signal to improved the speed that FPGA received DPHY serial data, can satisfy various verification platforms to the requirement of DPHY speed, and realize simple, safe and reliable.
Description
Technical field
The utility model relates to integrated circuit fields, especially a kind of frequency-halving circuit receiving DPHY serial signal.
Background technology
MIPI (MobileIndustryProcessorInterface, mobile Industry Processor Interface) DPHY standard is the agreement communicated for Mobile solution proposed by MIPI alliance.Due to serial transmission, bandwidth is high, and transmission and reception are simple, and it is widely used in the various mobile devices such as imageing sensor.Along with the continuous lifting (flank speed commercial at present reaches 2.5Gbps) of transfer rate (datarate), send and receive all in the face of acid test, especially for FPGA receiving end.
The common practice that current FPGA receives DPHY data is with LVDS (Low-VoltageDifferentialSignaling low-voltage differential signal) interface, serial clock or enter FPGAPLL (PhaseLockedLogic, phaselocked loop), PLL exports sampling clock and goes to drive LVDS sampling interface serial data, or Direct Sampling input serial data.But the LVDS interface of FPGA is subject to the restriction of physics and technique, the data that serial rate is no more than 1.6Gbps can only be received.The utility model provides a kind of circuit DPHY serial data and serial clock being carried out two divided-frequency, will significantly improve the speed of the DPHY serial data that FPGA receives.
Utility model content
The purpose of this utility model is to provide a kind of frequency-halving circuit receiving DPHY serial signal, to improve the speed of the DPHY serial data that FPGA receives.
In order to achieve the above object, the utility model provides a kind of frequency-halving circuit receiving DPHY serial signal, it is characterized in that, comprises a DPHY receiver, two difference registers and at least four difference transponders;
The input end of described DPHY receiver receives the serial output signal of DPHY and isolates differential data signals, the differential data signals output terminal of described DPHY receiver exports described differential data signals and is connected with the data signal input of described two difference registers respectively, and the clock signal output terminal of described DPHY receiver connects with the clock signal input terminal of described two difference registers respectively and makes the clock signal phase of described two difference registers contrary;
A data signal output in multiple data signal output of each difference register and corresponding with it anti-phase connection of data signal input, and using the clock signal output terminal of this data signal output as described difference register, this data signal output is connected with the data signal input of one of them difference transponder simultaneously, and other data signal output of each difference register are connected with the data signal input of other difference transponders respectively.
Preferably, in the frequency-halving circuit of above-mentioned reception DPHY serial signal, the connection wire of the differential data signals output terminal of described DPHY receiver and the data signal input of described two difference registers has a first node, and described first node is arranged near described difference register.
Preferably, in the frequency-halving circuit of above-mentioned reception DPHY serial signal, also comprise one first resistance and one second resistance; One end of described first resistance is connected with described first node, and the other end is connected with pull-up voltage on one first; One end of described second resistance is connected with described first node, and the other end is held with ground and is connected.
Preferably, in the frequency-halving circuit of above-mentioned reception DPHY serial signal, a data signal output in described two difference registers and the wire of the anti-phase connection of the data signal input corresponding with it have a Section Point, and described Section Point is arranged near the data signal input of described difference register.
Preferably, in the frequency-halving circuit of above-mentioned reception DPHY serial signal, also comprise one the 3rd resistance and one the 4th resistance; One end of described 3rd resistance is connected with described Section Point, and the other end is connected with pull-up voltage on one second; One end of described 4th resistance is connected with described Section Point, and the other end is held with ground and is connected.
Preferably, in the frequency-halving circuit of above-mentioned reception DPHY serial signal, also comprise one the 7th resistance, one end of described 7th resistance is connected with described Section Point, and the other end is connected with pull-up voltage on the 4th.
Preferably, in the frequency-halving circuit of above-mentioned reception DPHY serial signal, on the described 4th, pull-up voltage can the power supply of Absorption Current provide by one.
Preferably, in the frequency-halving circuit of above-mentioned reception DPHY serial signal, the wire that the data signal output of described two difference registers is connected with the data signal input of described at least four difference transponders has one the 3rd node, and described 3rd node is arranged near described difference transponder.
Preferably, in the frequency-halving circuit of above-mentioned reception DPHY serial signal, also comprise one the 5th resistance and one the 6th resistance; One end of described 5th resistance is connected with described 3rd node, and the other end is connected with pull-up voltage on the 3rd; One end of described 6th resistance is connected with described 3rd node, and the other end is held with ground and is connected.
Preferably, in the frequency-halving circuit of above-mentioned reception DPHY serial signal, also comprise one the 8th resistance, one end of described 8th resistance is connected with described 3rd node, the other end is connected with pull-up voltage on the 5th, and on the described 5th, pull-up voltage can the power supply of Absorption Current provide by one.
In the frequency-halving circuit of the reception DPHY serial signal provided at the utility model, utilize a DPHY receiver, two difference registers and at least four difference transponders carry out two divided-frequency process to the output signal of DPHY, comprise and all two divided-frequency process has been carried out to the data output signal of described DPHY and clock output signal, thus improve the speed that FPGA receives DPHY serial data, the requirement of various verification platform to described DPHY speed can be met, and realize simple, safe and reliable.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of frequency-halving circuit in the utility model embodiment one;
Fig. 2 is the structural representation of DPHY receiver in the utility model embodiment one;
Fig. 3 is the structural representation of the first difference register in the utility model embodiment one;
Fig. 4 is the structural representation of the second difference register in the utility model embodiment one;
Fig. 5 is differential data signals output terminal DHP0_M, DHN0_M of DPHY receiver in the utility model embodiment one and the connection layout of the first difference register and the second difference register;
Fig. 6 is the clock signal output terminal of DPHY receiver in the utility model embodiment one and the connection layout of the first difference register and the second difference register;
Fig. 7 is data signal output DHP0_SP, DHN0_SP of the first difference register in the utility model embodiment one and the connection layout of a difference transponder;
Fig. 8 is the sequential chart of frequency-halving circuit in the utility model embodiment one;
Fig. 9 is the structural representation of the first difference register in the utility model embodiment two;
Figure 10 is the structural representation of the second difference register in the utility model embodiment two;
Figure 11 is data signal output DHP0_SP, DHN0_SP of the first difference register in the utility model embodiment two and the connection layout of a difference transponder;
In figure: 100-DPHY receiver; 201-first difference register; 202-second difference register; 300-difference transponder.
Embodiment
Below in conjunction with schematic diagram, embodiment of the present utility model is described in detail.According to following description and in conjunction with claims, advantage of the present utility model and feature will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, aid illustration the utility model embodiment lucidly.
Embodiment one
Embodiments provide a kind of frequency-halving circuit receiving DPHY serial signal, for receiving the serial output signal of DPHY, described frequency-halving circuit carries out two divided-frequency to the serial output signal of described DPHY, comprise the two divided-frequency of serial data and serial clock, and then the serial data after two divided-frequency and serial clock are sent to fpga chip.
Concrete, as shown in Figure 1, comprising: a DPHY receiver, two difference registers and at least four difference transponders; Described DPHY receiver is for receiving the serial output signal of described DPHY, differential data signals and single-ended signal is isolated from described serial output signal, described differential data signals exports from the differential data signals output terminal of described DPHY receiver, and described single-ended signal is directly connected with fpga chip.Certainly, in other embodiments of the present utility model, described single-ended signal by twin voltage LVCMOS transceiver detection out, and then can also be sent to described fpga chip.
It is a LVDS differential signal that the serial data signal of described DPHY and serial clock signal export with p, n two signal wires respectively, and that is, each output terminal of described DPHY all has two bars circuits, and each signal input part of the described DPHY receiver be connected with the output terminal of described DPHY also has two bars circuits.And described DPHY has multiple data signal output and a clock signal output terminal, therefore, described DPHY receiver also has multiple data signal input and a clock signal input terminal.Such as, as shown in Figure 2, the data-signal that described DPHY receiver has 4 data signal input to export for receiving described DPHY, be respectively DHP0, DHN0, DHP1, DHN1, DHP2, DHN2 and DHP3, DHN3, and the clock signal that 1 clock signal input terminal CHP, CHN export for receiving described DPHY.The differential signal outputs of the described DPHY receiver corresponding with these signal input parts is respectively: 4 data signal output: DHP0_M, DHN0_M, DHP1_M, DHN1_M, DHP2_M, DHN2_M and DHP3_M, DHN3_M, and 1 clock signal output terminal CHP_M, CHN_M.In the present embodiment, described DPHY receiver adopts MC20901 chip, in other embodiments of the present utility model, also can use other chips, as long as single-ended signal and differential signal can be carried out being separated and realize the conversion of voltage standard.The 1.2V large-signal that described DPHY exports can be separated by described DPHY receiver, can certainly be detected by common single-ended twin voltage signal transceiver and be exported, such as SN74AVC2T45 chip.
The differential data signals output terminal of described DPHY receiver is connected with the data signal input of described two difference registers respectively, the clock signal output terminal of described DPHY receiver is connected with the clock signal input terminal of described two difference registers respectively, and makes the clock signal input terminal phase place of described two difference registers contrary.
Concrete, in the utility model embodiment, comprise two difference registers, be respectively the first difference register and the second difference register, while each data signal output of described DPHY receiver is that the data signal input of described first difference register connects, also be connected with the data signal input of described second difference register, thus make the data output signal two divided-frequency of described DPHY receiver, namely obtain the data output signal of two divided-frequency.In the present embodiment, described two difference registers are SY10EP451L chip.Equally, in other embodiments of the present utility model, described difference register comprises and is not limited to described SY10EP451L chip, as long as function is identical.
Connect example, DHP0_M, DHN0_M, DHP1_M, DHN1_M, DHP2_M, DHN2_M and DHP3_M, DHN3_M are connected with the data signal input of described first difference register and described second difference register respectively.
Preferably, connection between described DPHY receiver and described two difference registers adopts four resistor network modes, to realize by the conversion of LVDS to LVPECL (LowVoltagePositiveEmitter-CoupleLogic), that is, four resistance are provided with between described DPHY receiver and described two difference registers, the output signal (comprising data-signal and clock signal) of described DPHY receiver is just being connected with the input end (comprising data signal input and clock signal input terminal) of described two difference registers after described four resistor networks.That is, described DPHY receiver each output terminal (comprising data signal output and clock signal output terminal) and each input end of described two difference registers between (comprising data signal input and clock signal input terminal) be provided with four resistance.Concrete, each output terminal (comprising data signal input and clock signal input terminal) of described DPHY receiver and the connection wire of each input end (comprising data signal input and clock signal input terminal) of described two difference registers there is a first node A, and described first node A is arranged near described two difference registers, one first resistance R
1one end be connected with described first node, the other end is connected with pull-up voltage on one first, one second resistance R
2one end be connected with described first node, the other end is connected to ground.And cable run distance between the data signal input of described first node and the difference register corresponding with it is equal.
Connect example, as shown in Figure 5, for output terminal DHP0_M, a DHN0_M of described DPHY receiver, the wire that the data signal input of described DHP0_M, DHN0_M and described first difference register and the second difference register is connected there is described first node (A
0, A '
0), described first resistance R
10one end and described first node A
0connect, pull-up voltage V on the other end and described first
10connect, described second resistance R
20one end and described first node A
0connect, the other end is connected to ground.Described first resistance R '
10one end and described first node A '
0connect, pull-up voltage V ' on the other end and described first
10connect, described second resistance R '
20one end and described first node A '
0connect, the other end is connected to ground.In like manner as shown in Figure 6, the wire that the clock signal input terminal of described CHP_M, CHN_M and described first difference register and described second difference register is connected there is described first node (A
c, A '
c), described first resistance R
1Cone end and described first node A
cconnect, pull-up voltage V on the other end and described first
cconnect, described second resistance R
2Cone end and described first node A
cconnect, the other end is connected to ground.Described first resistance R '
1Cone end and described first node A '
cconnect, pull-up voltage V ' on the other end and described first
cconnect, described second resistance R '
2Cone end and described first node A '
cconnect, the other end is connected to ground.
Connect example, as shown in Figure 3 and Figure 4, the output terminal of described first difference register corresponding with DHP0_M, DHN0_M is DHP0_SP, DHN0_SP, and the output terminal of described second difference register is DHP0_SN, DHN0_SN.The output terminal of described first difference register corresponding with DHP1_M, DHN1_M is DHP1_SP, DHN1_SP, and the output terminal of described second difference register is DHP1_SN, DHN1_SN.The output terminal of described first difference register corresponding with DHP2_M, DHN2_M is DHP2_SP, DHN2_SP, and the output terminal of described second difference register is DHP2_SN, DHN2_SN.The output terminal of described first difference register corresponding with DHP3_M, DHN3_M is DHP3_SP, DHN3_SP, and the output terminal of described second difference register is DHP3_SN, DHN3_SN.
Further, as shown in Figure 6, the clock input signal of described first difference register and the clock input signal of described second difference register anti-phase.Concrete, connect example, when described CHP_M is through described first node (A
c) afterwards with being just connected of the clock signal input terminal of described first difference register, described CHN_M through described first node (A '
c) when being connected with the clock signal input terminal of described first difference register anti-phase afterwards, then, described CHP_M is through described first node (A
c) be connected with the anti-phase of clock signal input terminal of described second difference register afterwards, and described CHN_M through described first node (A '
c) afterwards with being just connected of the clock signal input terminal of described second difference register.In like manner, when described CHP_M is through described first node (A
c) be connected with the anti-phase of clock signal input terminal of described first difference register afterwards, described CHN_M through described first node (A '
c) afterwards with being just connected of the clock signal input terminal of described first difference register time, then, described CHP_M is through described first node (A
c) afterwards with being just connected of the clock signal input terminal of described second difference register, and described CHN_M through described first node (A '
c) be connected with the anti-phase of clock signal input terminal of described second difference register afterwards.Thus make the rate reduction of the data of described DPHY receiver half.Simultaneously, phase shift between the data-signal exported due to described DPHY and clock signal is 90 ° of phase shifts, in order to make the sample window of described difference register maximize, the clock signal of described difference register thus can be utilized directly to sample to its data-signal.
Further, the number of the data signal input of described first difference register and described second difference register is greater than the number of the differential data signals output terminal of described DPHY receiver, by a data signal output of described first difference register and described second difference register and the anti-phase connection of the data signal input corresponding with it, and using the clock signal output terminal of data signal output described in this as this difference register described, thus make the clock signal two divided-frequency of described DPHY receiver, and obtain the clock signal of two divided-frequency.
Concrete, as shown in Figure 3, the positive of the clock signal output terminal of described first difference register exports (CHP_SP) and the anti-phase input corresponding with this clock signal output terminal connects, the anti-phase output (CHN_SP) of this clock signal output terminal and the positive corresponding with this clock signal output terminal input connect, thus form the frequency-halving circuit of serial clock.The positive of the clock signal output terminal of described second difference register exports (CHP_SN) and the anti-phase input corresponding with this clock signal output terminal connects, the anti-phase output (CHN_SN) of this clock signal output terminal and the positive corresponding with this clock signal output terminal input connect, thus form the frequency-halving circuit of serial clock.
Preferably, the frequency-halving circuit of the described serial clock level conversion that adopts four resistor network modes to realize between LVPECL to general differential signal.Namely the wire be connected with clock signal output terminal and the input end corresponding with it of described second difference register at described first difference register has a Section Point, and described Section Point is arranged near described input end.One end of one the 3rd resistance is connected with described Section Point, and the other end is connected with pull-up voltage on one second, and one end of one the 4th resistance is connected with described Section Point, and the other end is connected to ground.And cable run distance between the data signal input of described Section Point and the difference register corresponding with it is equal.
As shown in Figure 3, for described first difference register, the anti-phase connection of its clock signal output terminal CHP_SP and input end corresponding to it, and described Section Point B is had on connection wire
1, described 3rd resistance R
31one end and described Section Point B
1connect, pull-up voltage V on the other end and described second
21connect, described 4th resistance R
41one end and described Section Point B
1connect, the other end is connected to ground.The anti-phase connection of clock signal output terminal CHN_SP and input end corresponding to it, and described Section Point B ' is had on connection wire
1, described 3rd resistance R '
31one end and described Section Point B '
1connect, pull-up voltage V ' on the other end and described second
21connect, described 4th resistance R '
41one end and described Section Point B '
1connect, the other end is connected to ground.
As shown in Figure 4, for described second difference register, the anti-phase connection of its clock signal output terminal CHP_SN and input end corresponding to it, and described Section Point B is had on connection wire
2, described 3rd resistance R
32one end and described Section Point B
2connect, pull-up voltage V on the other end and described second
22connect, described 4th resistance R
41one end and described Section Point B
1connect, the other end is connected to ground.The anti-phase connection of clock signal output terminal CHN_SN and input end corresponding to it, and described Section Point B ' is had on connection wire
2, described 3rd resistance R '
32one end and described Section Point B '
2connect, pull-up voltage V ' on the other end and described second
22connect, described 4th resistance R '
42one end and described Section Point B '
2connect, the other end is connected to ground.
Described first difference register is connected with the input end of a difference transponder with each signal output part (comprising data signal output and clock signal output terminal) of described second difference register.The level conversion that four resistor network modes realize between LVPECL to general differential signal is adopted between each signal output part (comprising data signal output and clock signal output terminal) of described first difference register and described second difference register and the input end of a difference transponder, namely the wire be connected with the input end of described difference transponder at each data signal output described there is one the 3rd node M, one end of one the 5th resistance is connected with described 3rd node, the other end is connected with pull-up voltage on the 3rd, one end of one the 6th resistance is connected with described 3rd node, the other end is connected to ground.Described 3rd node on each data signal output of described two difference registers is equal with the cable run distance between the difference transponder corresponding with it.
In the present embodiment, described difference transponder is SN65LVDS100 chip.In other embodiments of the present utility model, described difference transponder is not limited to described SN65LVDS100 chip, as long as identical with its function.
Connect example, for data signal output DHP0_SP, DHN0_SP of described first difference register, as shown in Figure 7, be DHP0_SP2, DHN0_SP2 with the output terminal corresponding to described DHP0_SP, DHN0_SP in described difference transponder, the wire that described DHP0_SP, DHN0_SP are connected with described difference transponder has described 3rd node (M
1, M '
1).For described DHP0_SP, described 5th resistance R
51one end and described 3rd node M
1connect, pull-up voltage V on the other end and the described 3rd
31connect, described 6th resistance R
61one end and described 3rd node M
1connect, the other end is connected to ground.For described DHN0_SP, described 5th resistance R '
51one end and described 3rd node M '
1connect, the other end also with the described 3rd on pull-up voltage V '
31connect, described 6th resistance R '
61one end and described 3rd node M '
1connect, the other end is connected to ground.
In the present embodiment, the resistance of described first resistance, the 4th resistance and the 6th resistance is equal, and the resistance of described second resistance, the 3rd resistance and the 5th resistance is equal.On described first, in pull-up voltage, second, in pull-up voltage and the 3rd, the value of pull-up voltage is equal.
The output terminal of the described difference transponder be connected with the data signal output of described first difference register and described second difference register is directly connected with the data input pin of FPGA, and the output terminal of the described difference transponder be connected with the clock signal output terminal of the first difference register and described second difference register is directly connected with the input end of clock of described FPGA.In order to ensure maximum receptivity, the output terminal of all described difference transponders is equal to the cable run distance of the input end of FPGA.
So far, the output signal of described DPHY is after the frequency-halving circuit that described the utility model embodiment provides, and a road serial clock signal will be split up into two-way serial clock, and every road serial data signal is also split up into two-way serial data signal.Concrete sequential chart as shown in Figure 8, in figure, DHP is the serial data that described DPHY exports, CHP is the serial clock that described DPHY exports, DHP_SP is the two divided-frequency data that described first difference register exports, CHP_SP is the two divided-frequency clock that described first difference register exports, and DHP_SN is the two divided-frequency data that described second difference register exports, and CHP_SN is the two divided-frequency clock that described second difference basis exports.
Two kinds of modes of DPHY signal are received according to current FPGA, if the serial data of the serial clock Direct Sampling two divided-frequency with two divided-frequency, in order to make the sample window of FPGA maximize, needing in FPGA inside to use CHP_SN to the DHP_SP that samples, sampling DHP_SN with CHP_SP; If the serial clock after two divided-frequency is first through PLL, then go to drive LVDS interface with the clock that PLL exports, then only need the serial clock of a road two divided-frequency, the then phase place of dynamic conditioning PLL, can sample correct serial data.
Embodiment two
In the present embodiment, the frequency-halving circuit of described serial clock adopts two resistor network mode, and the described Section Point namely in embodiment one, one end of one the 7th resistance is connected with described Section Point, and the other end is connected with pull-up voltage on the 4th.
Concrete, for described first difference register, as shown in Figure 8, the anti-phase connection of its clock signal output terminal CHP_SP and input end corresponding to it, and described Section Point B is had on connection wire
1, described 7th resistance R
71one end and described Section Point B
1connect, pull-up voltage V on the other end and the described 4th
41connect.The anti-phase connection of its clock signal output terminal CHN_SP and input end corresponding to it, and described Section Point B ' is had on connection wire
1, described 7th resistance R '
71one end and described Section Point B '
1connect, pull-up voltage V ' on the other end and the described 4th
41connect.
For described second difference register, as shown in Figure 9, the anti-phase connection of its clock signal output terminal CHP_SN and input end corresponding to it, and described Section Point B is had on connection wire
2, described 7th resistance R
72one end and described Section Point B
2connect, pull-up voltage V on the other end and the described 4th
42connect.The anti-phase connection of its clock signal output terminal CHN_SN and input end corresponding to it, and described Section Point B ' is had on connection wire
2, described 7th resistance R '
72one end and described Section Point B '
2connect, pull-up voltage V ' on the other end and the described 4th
42connect.
Also the level conversion that two resistor network mode realizes between LVPECL to general differential signal is adopted between each signal output part (comprising data signal output and clock signal output terminal) and the input end of a difference transponder of described first difference register and described second difference register.Namely described 3rd node in above-described embodiment one, one the 8th resistance R
8one end be connected with described 3rd node, the other end is connected with pull-up voltage on the 5th.
Concrete, as shown in figure 11, for data signal output DHP0_SP, DHN0_SP of described first difference register, be DHP0_SP2, DHN0_SP2 with the output terminal corresponding to described DHP0_SP, DHN0_SP in described difference transponder, the wire that described DHP0_SP, DHN0_SP are connected with described difference transponder has described 3rd node (M
1, M '
1).For described DHP0_SP, described 8th resistance R
81one end and described 3rd node M
1connect, pull-up voltage V on the other end and the described 5th
51connect.For described DHN0_SP, described 8th resistance R '
81one end and described 3rd node M '
1connect, the other end also with the described 5th on pull-up voltage V '
51connect.
The resistance of described 7th resistance and the 8th resistance is equal, and on the described 4th, in pull-up voltage and the 5th, the value of pull-up voltage is equal.
Further, pull-up voltage-2.0V on pull-up voltage=described 3rd on the described 4th.The resistance equivalence in parallel of the resistance of described 7th resistance and described 3rd resistance and the 4th resistance.
In embodiments of the invention one and embodiment two, on the described 3rd, the value of pull-up voltage (V3) is 3.3V, and that is in pull-up voltage and the 5th, the value of pull-up voltage is 1.3V on the described 4th.
Due to the export structure that described first difference register and the second difference register are emitter open circuit, a current reflux path must be had, therefore, provide the power supply of pull-up voltage in pull-up voltage and the 5th on the described 4th must can Absorption Current.That is, described power supply demand fulfillment two conditions, can Absorption Current and can ensure that output voltage meets the demand of upper pull-up voltage in two resistor network, and in the present embodiment, namely will meet output voltage is 1.3V.
Further, in the present embodiment, described power supply selects LT3015 power supply chip, and the ground using 3.3V as described LT3015 power supply chip, thus avoid the requirement adopting negative voltage as described LT3015 power supply chip input voltage.Certainly, in other embodiments of the present utility model, described power supply can also select other power supply chips, as long as it meets above-mentioned two conditions, does not repeat them here.
Other parts are all identical with embodiment one, do not repeat them here.
To sum up, in the frequency-halving circuit of the reception DPHY serial signal provided in the utility model embodiment, utilize a DPHY receiver, two difference registers and at least four difference transponders carry out two divided-frequency process to the output signal of DPHY, comprise and all two divided-frequency process has been carried out to the data output signal of described DPHY and clock output signal, thus improve the speed that FPGA receives DPHY serial data, the requirement of various verification platform to described DPHY speed can be met, and realize simple, safe and reliable.
Above are only preferred embodiment of the present utility model, any restriction is not played to the utility model.Any person of ordinary skill in the field; not departing from the scope of the technical solution of the utility model; the technical scheme disclose the utility model and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from the technical solution of the utility model, still belong within protection domain of the present utility model.
Claims (10)
1. receive a frequency-halving circuit for DPHY serial signal, it is characterized in that, comprise a DPHY receiver, two difference registers and at least four difference transponders;
The input end of described DPHY receiver receives the serial output signal of DPHY and isolates differential data signals, the differential data signals output terminal of described DPHY receiver exports described differential data signals and is connected with the data signal input of described two difference registers respectively, and the clock signal output terminal of described DPHY receiver connects with the clock signal input terminal of described two difference registers respectively and makes the clock signal phase of described two difference registers contrary;
A data signal output in multiple data signal output of each difference register and corresponding with it anti-phase connection of data signal input, and using the clock signal output terminal of this data signal output as described difference register, this data signal output is connected with the data signal input of one of them difference transponder simultaneously, and other data signal output of each difference register are connected with the data signal input of other difference transponders respectively.
2. the frequency-halving circuit of reception DPHY serial signal according to claim 1, it is characterized in that, the connection wire of the differential data signals output terminal of described DPHY receiver and the data signal input of described two difference registers has a first node, and described first node is arranged near described difference register.
3. the frequency-halving circuit of reception DPHY serial signal according to claim 2, is characterized in that, also comprise one first resistance and one second resistance; One end of described first resistance is connected with described first node, and the other end is connected with pull-up voltage on one first; One end of described second resistance is connected with described first node, and the other end is held with ground and is connected.
4. the frequency-halving circuit of reception DPHY serial signal according to claim 1, it is characterized in that, a data signal output in described two difference registers and the wire of the anti-phase connection of the data signal input corresponding with it have a Section Point, and described Section Point is arranged near the data signal input of described difference register.
5. the frequency-halving circuit of reception DPHY serial signal according to claim 4, is characterized in that, also comprise one the 3rd resistance and one the 4th resistance; One end of described 3rd resistance is connected with described Section Point, and the other end is connected with pull-up voltage on one second; One end of described 4th resistance is connected with described Section Point, and the other end is held with ground and is connected.
6. the frequency-halving circuit of reception DPHY serial signal according to claim 4, it is characterized in that, also comprise one the 7th resistance, one end of described 7th resistance is connected with described Section Point, and the other end is connected with pull-up voltage on the 4th.
7. the frequency-halving circuit of reception DPHY serial signal according to claim 6, is characterized in that, on the described 4th, pull-up voltage can the power supply of Absorption Current provide by one.
8. the frequency-halving circuit of reception DPHY serial signal according to claim 1, it is characterized in that, the wire that the data signal output of described two difference registers is connected with the data signal input of described at least four difference transponders has one the 3rd node, and described 3rd node is arranged near described difference transponder.
9. the frequency-halving circuit of reception DPHY serial signal according to claim 8, is characterized in that, also comprise one the 5th resistance and one the 6th resistance; One end of described 5th resistance is connected with described 3rd node, and the other end is connected with pull-up voltage on the 3rd; One end of described 6th resistance is connected with described 3rd node, and the other end is held with ground and is connected.
10. the frequency-halving circuit of reception DPHY serial signal according to claim 8, it is characterized in that, also comprise one the 8th resistance, one end of described 8th resistance is connected with described 3rd node, the other end is connected with pull-up voltage on the 5th, and on the described 5th, pull-up voltage can the power supply of Absorption Current provide by one.
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| CN201520835522.3U CN205068388U (en) | 2015-10-26 | 2015-10-26 | Receive DPHY serial signal's two frequency dividing circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US11687483B1 (en) | 2021-12-05 | 2023-06-27 | Western Digital Technologies, Inc. | Embedded physical layers with passive interfacing for configurable integrated circuits |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US11687483B1 (en) | 2021-12-05 | 2023-06-27 | Western Digital Technologies, Inc. | Embedded physical layers with passive interfacing for configurable integrated circuits |
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