CN204904266U

CN204904266U - Encryption device

Info

Publication number: CN204904266U
Application number: CN201520620853.5U
Authority: CN
Inventors: 高建华; 杨莉莉
Original assignee: Beijing L&s Lancom Platform Tech Co Ltd
Current assignee: Beijing L&s Lancom Platform Tech Co Ltd
Priority date: 2015-08-17
Filing date: 2015-08-17
Publication date: 2015-12-23
Anticipated expiration: 2025-08-17

Abstract

The utility model discloses an encryption device. Wherein, the device includes: the conversion chip, control chip and the encryption chip of being connected with this control chip, wherein, should change the chip for conversion between control serial data and the parallel data, this control chip is connected with this conversion chip for the parallel data who obtains the conversion converts the data to the data format that should encrypt the chip into, and perhaps, will encrypt chip encrypted most likely is this parallel data to the data format's that should encrypt the chip data conversion, this encrypts the chip for data to the data format that this encryption chip is corresponding after this control chip conversion are encrypted. The utility model provides a communication is complicated between current encryption device and the main chip just occupies the technical problem that system resource is big.

Description

Encryption device

Technical field

The utility model relates to field of encryption, in particular to a kind of encryption device.

Background technology

At present, society enters the epoch that are information-based and networking comprehensively, and increasing user carrys out obtaining information by network, process information, transmission of information.Along with the continuous enhancing of network demand, the danger of safety in network hidden danger becomes clear day by day.How protecting network and information security, has become the focus of concern.Data encrypting and deciphering technology, as an important component part of network security, plays very important role wherein, it involve data integrality, confidentiality, can differentiate and non-repudiation.

The general hardware encryption card that adopts is encrypted the communication data between equipment now, and with protecting network and information security, cryptographic algorithm can only complete data encrypting and deciphering operation in card.Existing encrypted card mainly comprises following 3 kinds: 1, PCI (PeripheralComponentInterconnect, peripheral component interconnect standard) encrypted card, but the processor that the interface of this encrypted card often and is now furnished with pci interface is fewer and feweri, and versatility is not high; 2, PCI-E encrypted card, but the interface chip cost of this encrypted card is higher, too increases the difficulty of software development; 3, USB (UniversalSerialBus, USB (universal serial bus)) encrypted card, but the transfer rate of the interface chip of this encrypted card is limited, and cost is higher, simultaneously because the USB interface of master chip is generally complete in external equipment, system core resource can be taken.

For above-mentioned problem, at present effective solution is not yet proposed.

Utility model content

The utility model embodiment provides a kind of encryption device, at least to solve existing encryption device and complicated and that occupying system resources the is large technical matters that communicates between master chip.

According to an aspect of the utility model embodiment, provide a kind of encryption device, comprising:

Conversion chip, control chip and the encryption chip be connected with described control chip; Wherein, described conversion chip, for controlling the conversion between serial data and parallel data; Described control chip, be connected with described conversion chip, for the parallel data be converted to being converted to the data of the data layout of corresponding described encryption chip, or, the data of the data layout of the described encryption chip of correspondence after described encryption chip encryption are converted to described parallel data; Described encryption chip, for being encrypted the data of data layout corresponding to the described encryption chip after the conversion of described control chip.

Further, described conversion chip, is converted to described parallel data for the described serial data sent by master chip.

Further, described conversion chip, for being converted to described serial data by the described parallel data after described control chip conversion.

Further, described encryption device also comprises: level transferring chip, and described level transferring chip is connected between described control chip and described encryption chip, for controlling the level conversion between described control chip and described encryption chip.

Further, described conversion chip is 88E1111 chip.

Further, described control chip is on-site programmable gate array FPGA chip.

Further, described fpga chip is EP3C10E144C8N chip.

Further, described level transferring chip comprises 74ALVCH164245ID chip and 74LVC1T45DBV chip.

Further, described level transferring chip, for when the transmission direction of the data received is unidirectional, by the level conversion described in 74LVC1T45DBV chip controls between control chip and described encryption chip; When the transmission direction of the data received is two-way, by the level conversion described in 74ALVCH164245ID chip controls between control chip and described encryption chip.

In the utility model embodiment, conversion chip, control chip and the encryption chip be connected with this control chip; Wherein, this conversion chip, for controlling the conversion between serial data and parallel data; This control chip, be connected with this conversion chip, for the parallel data be converted to being converted to should the data of data layout of encryption chip, or, after this encryption chip is encrypted to the data of data layout of encryption chip being converted to this parallel data; This encryption chip, for being encrypted the data of data layout corresponding to this encryption chip after the conversion of this control chip.Like this, realize the conversion between serial data and parallel data by conversion chip, thus solve existing encryption device and complicated and that occupying system resources the is large technical matters that communicates between master chip.

Accompanying drawing explanation

Accompanying drawing described herein is used to provide further understanding of the present utility model, and form a application's part, schematic description and description of the present utility model, for explaining the utility model, is not formed improper restriction of the present utility model.In the accompanying drawings:

Fig. 1 is the schematic diagram of a kind of optional encryption device according to the utility model embodiment;

Fig. 2 is the schematic diagram according to the optional encryption device of the another kind of the utility model embodiment;

Fig. 3 is the pin figure of a kind of optional 88E1111 chip according to the utility model embodiment;

Fig. 4 is the pin connection diagram of a kind of optional 88E1111 chip according to the utility model embodiment and fpga chip;

Fig. 5 is the pin figure of a kind of optional 74ALVCH164245ID chip according to the utility model embodiment;

Fig. 6 is the pin figure of a kind of optional 74LVC1T45DBV chip according to the utility model embodiment.

Embodiment

The utility model scheme is understood better in order to make those skilled in the art person, below in conjunction with the accompanying drawing in the utility model embodiment, technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the embodiment of the utility model part, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all should belong to the scope of the utility model protection.

It should be noted that, term " first ", " second " etc. in instructions of the present utility model and claims and above-mentioned accompanying drawing are for distinguishing similar object, and need not be used for describing specific order or precedence.Should be appreciated that the data used like this can be exchanged in the appropriate case, so as embodiment of the present utility model described herein can with except here diagram or describe those except order implement.In addition, term " comprises " and " having " and their any distortion, intention is to cover not exclusive comprising, such as, contain those steps or unit that the process of series of steps or unit, method, system, product or equipment is not necessarily limited to clearly list, but can comprise clearly do not list or for intrinsic other step of these processes, method, product or equipment or unit.

A kind of encryption device that Fig. 1 provides for the utility model embodiment, as shown in Figure 1, in the utility model embodiment, this encryption device can be hardware encryption card, this encryption device comprises: conversion chip 101, control chip 102 and the encryption chip 103 be connected with this control chip 102; Wherein,

This conversion chip 101, for controlling the conversion between serial data and parallel data;

This control chip 102, be connected with this conversion chip 101, for the parallel data be converted to being converted to should the data of data layout of encryption chip, or, after this encryption chip 103 is encrypted to the data of data layout of encryption chip being converted to this parallel data;

This encryption chip 103, for being encrypted the data of data layout corresponding to this encryption chip after the conversion of this control chip 102.

Like this, realize the conversion between serial data and parallel data by conversion chip, thus solve existing encryption device and complicated and that occupying system resources the is large technical matters that communicates between master chip.

Alternatively, this conversion chip 101, is converted to this parallel data for this serial data sent by master chip.

Wherein, this master chip can be CN7010 chip.

In the utility model embodiment, for the serial data received from master chip, this serial data is converted to parallel data by this conversion chip.

Alternatively, this conversion chip 101, is converted to this serial data for this parallel data after being changed by this control chip.

In the utility model embodiment, for the parallel data received from control chip, this parallel data is converted to serial data by this conversion chip.

Alternatively, as shown in Figure 2, this encryption device also comprises: level transferring chip 104, and this level transferring chip 104 is connected between this control chip 102 and this encryption chip 103, for controlling the level conversion between this control chip 102 and this encryption chip 103.

It should be noted that, because encryption chip just can reach maximum frequency of operation under particular level (as 5V) electric power thus supplied, and the level of the interface of control chip not necessarily supports this particular level, if encryption chip is directly connected with this control chip, control chip will be caused locked or burn, therefore, by connecting level transferring chip between encryption chip and control chip, control the level conversion between this control chip and this encryption chip, make the level of the interface of control chip and the level match of encryption chip work, thus prevent from causing control chip locked or burn because encryption chip and control chip are directly connected.

In the utility model embodiment, serial data is passed through serial SGMII (SerialGigabitMediumIndependent by master chip, serial gigabit media are independent) interface transfers to the conversion chip of encryption device, this serial data is converted to parallel data by this conversion chip, and by GMII (GigabitMediumIndependent, gigabit media are independent) interface transfers to control chip, this parallel data is converted to should the data of data layout of encryption chip by this control chip, and by level transferring chip be the level of coupling encryption chip by the level conversion of the interface of control chip, and the data after being changed by control chip according to the level of this coupling encryption chip transfer to encryption chip, after encryption chip completes encryption to data again, by level transferring chip, current level is converted to the level of the interface of control chip, and the data after encryption are transferred to control chip by level transferring chip, data after this encryption are converted to parallel data by this control chip, and transfer to conversion chip by gmii interface, this parallel data is converted to serial data by this conversion chip, and pass through SGMII interface by this serial data transmission to master chip.Like this, realize the conversion between serial data and parallel data by conversion chip, thus the data achieved easily between master chip and this encryption device are transmitted, simple.

Alternatively, this conversion chip can be 88E1111 chip, and this control chip is FPGA (FieldProgrammableGateArray, field programmable gate array) chip, in the utility model embodiment, this fpga chip is EP3C10E144C8N chip.

As shown in Figure 3, Fig. 3 is the pin figure of this 88E1111 chip, the signal that master chip comes be connected to the high-speed serial signals interface S_IN of 88E1111 chip ±, S_0UT ±; The signal of gmii interface is connected to the I/O pin of fpga chip; Management (Management) interface signal MDIO, MDC are also connected to FPGA; Configuration (Config) interface signal is connected to the interfaces such as VCC, VSS, LED according to relevant mapping relations, configures accordingly hardware parameter.88E1111 chip is completely according to IEEE802.3 protocols work.The signal TX_CLX of gmii interface is tranmitting data register, and TX_EN, for sending enable signal, when TX_EN is effective, transmits data TXD [7] to TXD [0] to 88E1111 chip at the rising edge of TX_CLK, completes transmit operation.RX_CLK is receive clock, and RX_DV receives data enable signal, and when RX_DV is effective, FPGA receives data RXD [7] to RXD [0] at the rising edge of receive clock from 88E1111 chip, completes reception operation.

Fig. 4 is the connection diagram of control chip and conversion chip, the connection diagram of gmii interface and fpga chip is basically illustrated in figure, fpga chip can be the CycloneIIIEP3C10E144C8N chip of A Ertela (Altera) company, in CycloneIII series, inherit complete gigabit Ethernet stone, stone comprises MAC (MediaAccessControl, medium access control) module.And this MAC module supports the transfer rate of 10Mb/s or 100Mb/s or 1000Mb/s, as shown in Figure 4, the GTX_CLK of this 88E1111 chip is connected with the TX_CLK pin of the MAC module in fpga chip, TXD [7] to TXD [0] pin of this 88E1111 chip is connected with GM_TX_D [7] to GM_TX_D [0] pin of the MAC module in fpga chip respectively, the TX_EN pin of this 88E1111 chip is connected with the GM_TX_EN pin of the MAC module in fpga chip, the TX_ERR pin of this 88E1111 chip is connected with the GM_TX_ERR pin of the MAC module in fpga chip, the RX_CLK of this 88E1111 chip is connected with the RX_CLK pin of the MAC module in fpga chip, RXD [7] to RXD [0] pin of this 88E1111 chip is connected with GM_RX_D [7] to GM_RX_D [0] pin of the MAC module in fpga chip respectively, the RX_DV pin of this 88E1111 chip is connected with the GM_RX_DV pin of the MAC module in fpga chip, and the RX_ERR pin of this 88E1111 chip is connected with the GM_RX_ERR pin of the MAC module in fpga chip.

Alternatively, described level transferring chip comprises 74ALVCH164245ID chip and 74LVC1T45DBV chip.

In the utility model embodiment, described level transferring chip, for when the transmission direction of the data received is unidirectional, by the level conversion described in 74LVC1T45DBV chip controls between control chip and described encryption chip; When the transmission direction of the data received is two-way, by the level conversion described in 74ALVCH164245ID chip controls between control chip and described encryption chip, like this, according to the difference of the transmission direction of signal, select corresponding level transferring chip flexibly, thus reduce the waste of transfer resource.

Wherein, Fig. 5 is the pin figure of 74ALVCH164245ID chip, and wherein pin one DIR and 2DIR accesses fpga chip, and Fig. 6 is the pin figure of 74LVC1T45DBV chip.

It should be noted that, the encryption device in the utility model can be hardware encryption card, adopts this hardware encryption card, by with the coordinating of CN7010 master chip, data encrypting and deciphering speed can reach 60Mbps; Under 1000MLAN (LocalAreaNetwork, LAN (Local Area Network)) environment, encryption tunnel is consulted to set up and is postponed < 1 millisecond; Data packet discarding rate is 0 at full capacity.

The above is only preferred implementation of the present utility model; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection domain of the present utility model.

Claims

1. an encryption device, is characterized in that, comprising: conversion chip, control chip and the encryption chip be connected with described control chip; Wherein,

Described conversion chip, for controlling the conversion between serial data and parallel data;

Described control chip, be connected with described conversion chip, for the parallel data be converted to being converted to the data of the data layout of corresponding described encryption chip, or, the data of the data layout of the described encryption chip of correspondence after described encryption chip encryption are converted to described parallel data;

Described encryption chip, for being encrypted the data of data layout corresponding to the described encryption chip after the conversion of described control chip.

2. encryption device according to claim 1, is characterized in that,

Described conversion chip, is converted to described parallel data for the described serial data sent by master chip.

3. encryption device according to claim 1, is characterized in that,

Described conversion chip, for being converted to described serial data by the described parallel data after described control chip conversion.

4. the encryption device according to any one of claims 1 to 3, it is characterized in that, described encryption device also comprises: level transferring chip, described level transferring chip is connected between described control chip and described encryption chip, for controlling the level conversion between described control chip and described encryption chip.

5. encryption device according to claim 4, is characterized in that, described conversion chip is 88E1111 chip.

6. encryption device according to claim 4, is characterized in that, described control chip is on-site programmable gate array FPGA chip.

7. encryption device according to claim 6, is characterized in that, described fpga chip is EP3C10E144C8N chip.

8. encryption device according to claim 4, is characterized in that, described level transferring chip comprises 74ALVCH164245ID chip and 74LVC1T45DBV chip.

9. encryption device according to claim 8, is characterized in that, described level transferring chip, for when the transmission direction of the data received is unidirectional, by the level conversion described in 74LVC1T45DBV chip controls between control chip and described encryption chip; When the transmission direction of the data received is two-way, by the level conversion described in 74ALVCH164245ID chip controls between control chip and described encryption chip.