CN204721475U - A kind of control circuit - Google Patents
A kind of control circuit Download PDFInfo
- Publication number
- CN204721475U CN204721475U CN201520440374.5U CN201520440374U CN204721475U CN 204721475 U CN204721475 U CN 204721475U CN 201520440374 U CN201520440374 U CN 201520440374U CN 204721475 U CN204721475 U CN 204721475U
- Authority
- CN
- China
- Prior art keywords
- pin
- resistance
- chip
- clock
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Details Of Connecting Devices For Male And Female Coupling (AREA)
Abstract
The utility model discloses a kind of control circuit, comprise the first chip, the second chip, the first resistance, the second resistance, the 3rd resistance and electrostatic discharge protective circuit; First chip comprises the first clock pin, the first data pin and hot plug pin; Second chip comprises second clock pin, the second data pin and standby signal pin; First clock pin is connected with second clock pin; First data pin is connected with the second data pin; Hot plug pin is connected with the first data pin; Standby signal pin is connected with second clock pin; First resistance is connected between hot plug pin and described first data pin; Second resistance is connected between standby signal pin and described second clock pin; 3rd resistance is connected between the first data pin and signal ground; Electrostatic discharge protective circuit is connected with the first clock pin, the first data pin respectively.Technical solutions of the utility model can save the pin resource of chip, the inner space of optimized device.
Description
Technical field
The utility model relates to electronic circuit technology field, particularly relates to a kind of control circuit.
Background technology
HDMI (High Definition Multimedia Interface) (High Definition Multimedia Interface, be called for short HDMI) be a kind of digitized video/audio interface technology, it is the tailored version digital interface of applicable image transmission, it can transmit audio frequency and signal of video signal simultaneously, and the maximum data transmission speed is 2.25GB/s.Along with the development of science and technology, increasing equipment adopts HDMI cable to connect, and realizes DDC (Direct Digital control is called for short DDC) both-way communication, mutually transmits transition modulation differential signal and control signal between equipment.Before setting up communication, slave devices needs to carry out identification detecting to main process equipment, and one that therefore needs to take slave devices inputs or outputs pin as detecting pin, the detecting level that detecting host equipment sends.Corresponding level data is passed to slave devices and identifies by detecting pin, identifies and just carries out DDC communication successfully.Therefore prior art occupies the pin resource of chip and the inner space of slave devices, causes the wasting of resources.
Summary of the invention
Technical problem to be solved in the utility model is, provides a kind of control circuit, can save the pin resource of chip, the inner space of optimized device.
For solving above technical problem, the utility model embodiment provides a kind of control circuit, comprises the first chip, the second chip, the first resistance, the second resistance, the 3rd resistance and electrostatic discharge protective circuit;
Described first chip comprises the first clock pin, the first data pin and hot plug pin;
Described second chip comprises second clock pin, the second data pin and standby signal pin;
Wherein, described first clock pin is connected with described second clock pin;
Described first data pin is connected with described second data pin;
Described hot plug pin is connected with described first data pin;
Described standby signal pin is connected with described second clock pin;
Described first resistance is connected between described hot plug pin and described first data pin;
Described second resistance is connected between described standby signal pin and described second clock pin;
Described 3rd resistance is connected between described first data pin and signal ground;
Described electrostatic discharge protective circuit is connected with described first clock pin, the first data pin respectively.
Further, described electrostatic discharge protective circuit comprises: the first electric capacity, the second electric capacity, the first diode and the second diode;
Described electrostatic discharge protective circuit is connected with described first clock pin, the first data pin respectively, is specially:
Described first electric capacity is connected between described first clock pin and signal ground;
Described second electric capacity is connected between described first data pin and signal ground;
Described first diode is connected between described first clock pin and signal ground;
Described second diode is connected between described first data pin and signal ground.
Further, described control circuit also comprises: the 4th resistance;
Described 4th resistance is connected between described first clock pin and second clock pin.
Further, described control circuit also comprises: the 5th resistance;
Described 5th resistance is connected between described first data pin and the second data pin.
Visible, the control circuit that the utility model embodiment provides, accesses the hot plug pin of the first resistance and the first chip at the first data pin place of the first chip, access the standby signal pin of the second resistance and the second chip at the first clock pin place of the first chip.After the first chip is connected by HDMI cable with the second chip, hot plug pin generates high level, and is drawn high the level of the second data pin by the first resistance, and the second chip carries out identification according to the level change of the second data pin and judges.Meanwhile standby signal pin generates high level, and is drawn high the level of the first clock pin by the second resistance, and the first chip carries out identification according to the level change of the first clock pin and judges.When the first chip and the second chip all identify successful, the first chip and the second chip carry out DDC communication, transfer control signal.When communication completes, the level of the second data pin is carried out repid discharge by the 3rd resistance, avoids discharging causing the second chip generation erroneous judgement slowly.Compared to prior art by take one input or output pin carry out identification judge, this control circuit can save the pin resource of chip, the inner space of optimized device.
Further, control circuit of the present utility model also comprises electrostatic discharge protective circuit, carries out electrostatic protection by electric capacity and diode pair control circuit, has ensured stability of the present utility model and fail safe further.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of embodiment of the control circuit that the utility model provides.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described.
See Fig. 1, it is the structural representation of a kind of embodiment of the control circuit that the utility model provides.As shown in Figure 1, this control circuit comprises the first chip 1, second chip 2, first resistance RH1, the second resistance RH2, the 3rd resistance RH3 and electrostatic discharge protective circuit.Wherein, electrostatic discharge protective circuit comprises: the first electric capacity CH8, the second electric capacity CH9, the first diode DH7 and the second diode DH6.
In the present embodiment, the first chip 1 and the second chip 2 can be, but not limited to be arranged in different terminals, connected, thus realize HDMI communication by HDMI cable.This terminal can be the TV of band HDMI function, the equipment such as Set Top Box.
First chip 1 comprises the first clock pin 11, first data pin 12 and hot plug pin 13.Hot plug pin 13, for when the first chip 1 is connected by HDMI cable with the second chip 2, exports 5V high level, thus draws high the level of the second data pin 22.
Second chip 2 comprises second clock pin 21, second data pin 22 and standby signal pin 23.Standby signal pin 23 be the second chip 2 standby time signal output pin, for exporting 5V standby signal, thus draw high the level of the first clock pin.
In the present embodiment, as shown in Figure 1, the first clock pin 11 is connected with second clock pin 21.First data pin 12 is connected with the second data pin 22.Hot plug pin 13 is connected with the first data pin 12.Standby signal pin 23 is connected with second clock pin 21.
In the present embodiment, the first resistance RH1 is connected between hot plug pin 13 and the first data pin 12.First resistance RH1 is pull-up resistor, for when accessing HDMI cable, is drawn high as high level by the second data pin 22 by low level.
In the present embodiment, the second resistance RH2 is connected between standby signal pin 23 and second clock pin 22.Second resistance RH2 is pull-up resistor, for when accessing HDMI cable, is drawn high as high level by the first clock pin 11 by low level.
In the present embodiment, when the first chip 1 is connected by HDMI cable with the second chip 2, the first clock pin 11 is connected with second clock pin 21, and the first data pin 12 is connected with the second data pin 22.At this moment, hot plug pin 13 exports high level, is drawn high the level of the second data pin 22 by the first resistance RH1, and the second chip 2 changes according to the level of the second data pin 22, carries out identification and judges, determine whether to carry out DDC communication.Meanwhile, standby signal pin 23 exports high level, is drawn high the level of the first clock pin 11 by the second resistance RH2, and the first chip 1 carries out identification according to the level change of the first clock pin and judges, determines whether to carry out DDC communication.When two chips all complete judge and determine to carry out can DDC communication time, the first chip 1 and the second chip 2 start DDC communication, transmit transition modulation differential signal and control signal.
In the present embodiment, the 3rd resistance RH3 is connected between the first data pin 12 and signal ground GND.3rd resistance RH3 is used for when the first chip and the second chip complete DDC communication, carrying out repid discharge, avoiding causing because discharging the second chip 2 that erroneous judgement occurs slowly to the second data pin 22.
In the present embodiment, electrostatic discharge protective circuit is connected with the first clock pin 11, first data pin 12 respectively, is specially: the first electric capacity CH8 is connected between the first clock pin 11 and signal ground GND.Second electric capacity CH9 is connected between the first data pin 12 and signal ground GND.First diode DH7 is connected between the first clock pin 11 and signal ground GND.Second diode DH6 is connected between the first data pin and signal ground GND.
In the present embodiment, control circuit also comprises: the 4th resistance RH19 and the 5th resistance RH21.4th resistance RH19 is connected between the first clock pin 11 and second clock pin 21.5th resistance RH21 is connected between the first data pin 12 and the second data pin 22.4th resistance RH19 and the 5th resistance RH21 is divider resistance, carries out dividing potential drop when the first chip 1 and the second chip 2 carry out communication.
Therefore, the control circuit that the utility model embodiment provides, access the hot plug pin 13 of the first resistance RH1 and the first chip 1 at the first data pin 12 place of the first chip 1, access the standby signal pin 23 of the second resistance RH2 and the second chip 2 at the first clock pin 11 place of the first chip 1.After the first chip 1 is connected by HDMI cable with the second chip 2, hot plug pin 13 generates high level, and draws high the level of the second data pin 22 by the first resistance RH1, and the second chip 2 carries out identification according to the level change of the second data pin 22 and judges.Meanwhile standby signal 23 pin generates high level, and is drawn high the level of the first clock pin 11 by the second resistance RH2, and the first chip 1 carries out identification according to the level change of the first clock pin 11 and judges.When the first chip 1 and the second chip 2 all identify successfully, the first chip 1 and the second chip 2 carry out DDC communication, transfer control signal.When communication completes, the level of the second data pin 22 is carried out repid discharge by the 3rd resistance RH3, avoids discharging causing the second chip generation erroneous judgement slowly.Compared to prior art by take one input or output pin carry out identification judge, this control circuit can save the pin resource of chip, the inner space of optimized device.
Further, control circuit of the present utility model also comprises electrostatic discharge protective circuit, carries out electrostatic protection by electric capacity and diode pair control circuit, has ensured stability of the present utility model and fail safe further.
The above is preferred implementation of the present utility model; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the utility model principle; can also make some improvements and modifications, these improvements and modifications are also considered as protection range of the present utility model.
Claims (4)
1. a control circuit, is characterized in that, comprises the first chip, the second chip, the first resistance, the second resistance, the 3rd resistance and electrostatic discharge protective circuit;
Described first chip comprises the first clock pin, the first data pin and hot plug pin;
Described second chip comprises second clock pin, the second data pin and standby signal pin;
Wherein, described first clock pin is connected with described second clock pin;
Described first data pin is connected with described second data pin;
Described hot plug pin is connected with described first data pin;
Described standby signal pin is connected with described second clock pin;
Described first resistance is connected between described hot plug pin and described first data pin;
Described second resistance is connected between described standby signal pin and described second clock pin;
Described 3rd resistance is connected between described first data pin and signal ground;
Described electrostatic discharge protective circuit is connected with described first clock pin, the first data pin respectively.
2. control circuit according to claim 1, is characterized in that, described electrostatic discharge protective circuit comprises: the first electric capacity, the second electric capacity, the first diode and the second diode;
Described electrostatic discharge protective circuit is connected with described first clock pin, the first data pin respectively, is specially:
Described first electric capacity is connected between described first clock pin and signal ground;
Described second electric capacity is connected between described first data pin and signal ground;
Described first diode is connected between described first clock pin and signal ground;
Described second diode is connected between described first data pin and signal ground.
3. control circuit according to claim 1, is characterized in that, described control circuit also comprises: the 4th resistance;
Described 4th resistance is connected between described first clock pin and second clock pin.
4. control circuit according to claim 1, is characterized in that, described control circuit also comprises: the 5th resistance;
Described 5th resistance is connected between described first data pin and the second data pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520440374.5U CN204721475U (en) | 2015-06-24 | 2015-06-24 | A kind of control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520440374.5U CN204721475U (en) | 2015-06-24 | 2015-06-24 | A kind of control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204721475U true CN204721475U (en) | 2015-10-21 |
Family
ID=54320432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520440374.5U Active CN204721475U (en) | 2015-06-24 | 2015-06-24 | A kind of control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204721475U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106776459A (en) * | 2016-12-14 | 2017-05-31 | 华为技术有限公司 | Signal processing method, node controller chip and multicomputer system |
| CN109302635A (en) * | 2018-10-16 | 2019-02-01 | 深圳Tcl新技术有限公司 | The shared transmission circuit and television set of HDMI signal wire and control line |
| CN110890047A (en) * | 2019-11-15 | 2020-03-17 | Tcl华星光电技术有限公司 | Display device |
-
2015
- 2015-06-24 CN CN201520440374.5U patent/CN204721475U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106776459A (en) * | 2016-12-14 | 2017-05-31 | 华为技术有限公司 | Signal processing method, node controller chip and multicomputer system |
| CN106776459B (en) * | 2016-12-14 | 2020-06-26 | 华为技术有限公司 | Signal processing method, node controller chip and multiprocessor system |
| CN109302635A (en) * | 2018-10-16 | 2019-02-01 | 深圳Tcl新技术有限公司 | The shared transmission circuit and television set of HDMI signal wire and control line |
| CN109302635B (en) * | 2018-10-16 | 2022-06-10 | 深圳Tcl新技术有限公司 | Shared transmission circuit of HDMI signal line and control line and television |
| CN110890047A (en) * | 2019-11-15 | 2020-03-17 | Tcl华星光电技术有限公司 | Display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3234788B1 (en) | DATA TRANSMISSION USING PCIe PROTOCOL VIA USB PORT | |
| US9197023B2 (en) | Apparatus for enabling simultaneous content streaming and power charging of handheld devices | |
| EP2711843B1 (en) | DisplayPort over USB mechanical interface | |
| US8886852B2 (en) | Techniques for achieving complete interoperability between different types of data and multimedia interfaces in handheld devices | |
| CN203224819U (en) | Mainboard | |
| CN103095855B (en) | I2C communication interface unit | |
| EP2860638B1 (en) | Serial communication over communication control pin | |
| US9197340B2 (en) | Connector and interface circuit for simultaneous content streaming and user data from handheld devices | |
| CN204721475U (en) | A kind of control circuit | |
| US9043528B2 (en) | Bridge between a peripheral component interconnect express interface and a universal serial bus 3.0 device | |
| US11232061B2 (en) | CompactFlash express (CFX) adapters | |
| CN204576500U (en) | A kind of usb communication circuit of compatible I2C communication and system | |
| TW201531099A (en) | Pluggable electronic device and method for determining output data of pluggable electronic device | |
| CN108780430B (en) | Sending Universal Serial Bus (USB) data over an alternate mode connection | |
| CN104967806B (en) | Switching circuit based on HDMI | |
| CN202872142U (en) | Multifunctional USB (Universal Serial Bus) data line | |
| CN103455462A (en) | Usb host controller and scheduling methods thereof | |
| CN104636096A (en) | Graphic card and electronic device | |
| CN203760209U (en) | MHL cable and MHL cable hot plug detecting system | |
| US9547615B2 (en) | Peripheral protocol negotiation | |
| US9853676B2 (en) | Alternative routing of wireless data onto power supply | |
| CN207939643U (en) | Device for shuangping san | |
| CN102547424B (en) | Method for detecting compatibility of CI card interface and CA card | |
| US20130054865A1 (en) | Mouse | |
| CN102572564A (en) | Method for common interface (CI) card interface to be compatible with condition access (CA) card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |