CN204131622U - A kind of Analog Component Video signal decoding circuit of anti-vibration - Google Patents
A kind of Analog Component Video signal decoding circuit of anti-vibration Download PDFInfo
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- CN204131622U CN204131622U CN201420607331.7U CN201420607331U CN204131622U CN 204131622 U CN204131622 U CN 204131622U CN 201420607331 U CN201420607331 U CN 201420607331U CN 204131622 U CN204131622 U CN 204131622U
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Abstract
The utility model discloses a kind of Analog Component Video signal decoding circuit of anti-vibration, it comprises crystal oscillator (10), analog to digital converter (20), decimal filtering wave by prolonging time device (30) and digital processing unit (40); Crystal oscillator (10) for generation of the clock signal (50) of fixed frequency, and is transferred to follow-up analog to digital converter (20); The output of analog to digital converter (20) is connected with the input of digital processing unit (40) and decimal filtering wave by prolonging time device (30) respectively, and analog to digital converter (20) is for being converted to digital component video signal by Analog Component Video signal; The output of decimal filtering wave by prolonging time device (30) is connected with the input of digital processing unit (40), and decimal filtering wave by prolonging time device (30) is for entering horizontal phasing control to digital component video signal; Digital processing unit (40), for processing digital component video signal, recovers at equal intervals, data that fixed sample is counted exports.The utility model decoding circuit can tolerate the impact that variations in temperature and strenuous vibration produce.
Description
Technical field
The utility model relates to Analog Component Video signal decoding field, particularly relates to a kind of Analog Component Video signal decoding circuit adopting the anti-vibration of decimal filtering wave by prolonging time device structure.
Background technology
Analog Component Video signal comprises three analog video passages, and be red (R), green (G), blue (B) respectively, wherein synchronizing signal is embedded in green (G) passage, and synchronizing signal comprises row and field information.Analog Component Video signal decoding mainly comprises the content of two aspects, is that decoding and the row field information of rgb video information is recovered respectively.
Traditional Analog Component Video signal decoding processing procedure is mainly: first carry out clamper to analog video signal, and signal cutting is carried out to it, pass through phase-locked loop (PLL) again to analog to digital converter (ADC) clock signal, after analog to digital converter (ADC) carries out analog-to-digital conversion to vision signal, by digital processing unit to this decoding video signal process.
The clock signal recovered due to phase-locked loop (PLL) has certain difference relative to the clock signal in the signal received, and this clock signal is easily subject to the impact of external environment condition, as variations in temperature, strenuous vibration etc., produce shake (jitter).Found by reality test, traditional Analog Component Video signal decoding can tolerate the impact that the change of temperature produces, and can not put up with the impact that strenuous vibration produces.In strenuous vibration situation, image can obviously be distorted, and vibration amplitude is larger, and scalloping is more severe.By the analysis to the distortion of shock conditions hypograph, clock signal can be confirmed to be and create larger shake (jitter), because the decoding of traditional analog component vide adopts this clock signal directly to sample to analog video signal, so the output data of analog to digital converter (ADC) are affected, this impact cannot be solved by follow-up digital processing unit, thus image produces distortion.
Utility model content
The purpose of this utility model is to overcome the deficiencies in the prior art, a kind of Analog Component Video signal decoding circuit of anti-vibration is provided, fixed frequency clock signal is directly produced by crystal oscillator, decimal filtering wave by prolonging time device is adopted to carry out time delay phase shift to vision signal, by the resampling process of digital processing unit, thus complete the decoding of Analog Component Video signal, this decoding circuit can resist the various changes of external environment condition, as the environmental change such as temperature, vibrations, there is obvious anti-vibration effect.
The purpose of this utility model is achieved through the following technical solutions: a kind of Analog Component Video signal decoding circuit of anti-vibration, and it comprises crystal oscillator, analog to digital converter ADC, decimal filtering wave by prolonging time device and digital processing unit; The output of described crystal oscillator is connected with the clock signal input of analog to digital converter ADC, and crystal oscillator for generation of the clock signal of fixed frequency, and is transferred to follow-up analog to digital converter ADC; The input of described analog to digital converter ADC is connected with Analog Component Video signal input part, the output of analog to digital converter ADC inputs with one of digital processing unit respectively and the input of decimal filtering wave by prolonging time device is connected, analog to digital converter ADC is used for Analog Component Video signal to be converted to digital component video signal, and is transferred to follow-up digital processing unit and decimal filtering wave by prolonging time device; Another of the output of described decimal filtering wave by prolonging time device and digital processing unit inputs and is connected, and decimal filtering wave by prolonging time device is used for entering horizontal phasing control to digital component video signal; Digital processing unit, processes digital component video signal, by the extraction to digital component video signal line synchronous characteristic, and samples to digital component video signal, and the data of recover at equal intervals, fixedly counting export.
Described decimal filtering wave by prolonging time device is all-pass filter, and described all-pass filter does not change the amplitude-frequency characteristic of digital component video signal, only changes the phase place of digital component video signal.
Described decimal filtering wave by prolonging time device adopts 14 rank FIR filter structures, it comprises: the first order stream treatment be made up of 14 grades of shift registers, 14 multiplier units and 7 adders, the second level stream treatment be made up of 7 registers and 6 adders, and the third level stream treatment be made up of 1 register.
In first order stream treatment, an input of each multiplier unit is all connected with at different levels output of 14 grades of shift registers, its another input input coefficient C1 ~ C14 successively, the phase place adjustment that different coefficient C1 ~ C14 is corresponding different, the input of 14 grades of shift registers is connected with the output of analog to digital converter ADC.
In first order stream treatment, two inputs of each adder are connected with the output of adjacent two multipliers respectively.
In the stream treatment of the second level, the input of each register is connected with the output of each adder in first order stream treatment respectively.
In the stream treatment of the second level, the output of every two adjunct registers is connected with the input of an adder respectively, the output of register is all made a gift to someone in adder, adder adopts cascade structure, the output of afterbody adder is connected with the input of register in third level stream treatment, and in third level stream treatment, the output of register is that the output of described decimal filtering wave by prolonging time device is connected with the input of follow-up digital processing unit.
The beneficial effects of the utility model are: the utility model decoding circuit can resist the various changes of external environment condition, as the environmental change such as temperature, vibrations.This circuit comprises: crystal oscillator, analog to digital converter (ADC), decimal filtering wave by prolonging time device and digital processing unit are formed.Crystal oscillator produces fixed frequency clock signal, this clock signal is given analog to digital converter (ADC) and is sampled to analog video signal, the output data of analog to digital converter (ADC) give decimal filtering wave by prolonging time device and digital processing unit processes, thus complete the decoding of Analog Component Video signal.
The utility model decoding circuit improves circuit structure, decoding circuit is no longer needed to carry out signal cutting process process to analog video signal, without the need to passing through phase-locked loop (PLL) to analog to digital converter (ADC) clock signal, directly produced the clock signal of fixed frequency by crystal oscillator; Decimal filtering wave by prolonging time device set up by the utility model decoding circuit, carries out resampling to vision signal, recovers at equal intervals, video data that fixed sample is counted exports.
The utility model decoding circuit structure is simple, can resist the various changes of external environment condition, the impact that tolerance variations in temperature and strenuous vibration produce.Particularly in strenuous vibration situation, the phenomenon of scalloping when image is sampled, can not be there is because of vibrations, export basic completely normal image, realize the object of anti-vibration.
Accompanying drawing explanation
Fig. 1 is the utility model Analog Component Video signal decoding circuit structural representation;
Fig. 2 is the principle schematic that the utility model adopts the decimal filtering wave by prolonging time device of 14 rank FIR filter;
Fig. 3 is decimal filtering wave by prolonging time device group delay spectrum curve of the present utility model;
Fig. 4 is the utility model digital component video signal handling principle schematic diagram;
Fig. 5 is that the utility model Fractional number calculates schematic diagram;
Fig. 6 is the output schematic diagram of the utility model digital processing unit;
Fig. 7 is that the utility model digital processing unit exports and input relation schematic diagram.
Embodiment
Below in conjunction with accompanying drawing, the technical solution of the utility model is described in further detail, but protection range of the present utility model is not limited to the following stated.
As shown in Figure 1, a kind of Analog Component Video signal decoding circuit of anti-vibration, it comprises crystal oscillator 10, analog to digital converter ADC20, decimal filtering wave by prolonging time device 30 and digital processing unit 40; The output of described crystal oscillator 10 is connected with the clock signal input of analog to digital converter ADC20, and crystal oscillator 10 for generation of the clock signal 50 of fixed frequency, and is transferred to follow-up analog to digital converter ADC20; The input of described analog to digital converter ADC20 is connected with Analog Component Video signal input part 60, the output of analog to digital converter ADC20 inputs with one of digital processing unit 40 respectively and the input of decimal filtering wave by prolonging time device 30 is connected, analog to digital converter ADC20 is used for Analog Component Video signal to be converted to digital component video signal, and is transferred to follow-up digital processing unit 40 and decimal filtering wave by prolonging time device 30; Another of the output of described decimal filtering wave by prolonging time device 30 and digital processing unit 40 inputs and is connected, and decimal filtering wave by prolonging time device 30 is for entering horizontal phasing control to digital component video signal; Digital processing unit 40, processes digital component video signal, by the extraction to digital component video signal line synchronous characteristic, and samples to digital component video signal, and the data of recover at equal intervals, fixedly counting export.
Digital processing unit extracts the capable synchronous characteristic information of digital component video signal, and by the resampling technique based on decimal filtering wave by prolonging time device, recover the data of at equal intervals, fixedly counting to export, the described resampling technique based on decimal filtering wave by prolonging time device is: the sampling number calculating a line vision signal, this sampling number is fractional value, carries out resampling based on the vision signal of this sampling number to input.
The fractional part of sampling number calculates and adopts the method for single order myopia to calculate.
Resampling process adopts decimal filtering wave by prolonging time device to enter horizontal phasing control, and this decimal filtering wave by prolonging time device is all-pass filter, and only adjust phase place, the group delay step of this decimal filtering wave by prolonging time device is 64 grades, and minimum delay resolution is 1/64 clock cycle.
As shown in Figure 2, described decimal filtering wave by prolonging time device 30 is all-pass filter, and described all-pass filter does not change the amplitude-frequency characteristic of digital component video signal, only changes the phase place of digital component video signal.
Described decimal filtering wave by prolonging time device 30 adopts 14 rank FIR filter structures, it comprises: the first order stream treatment be made up of 14 grades of shift registers, 14 multiplier units and 7 adders, the second level stream treatment be made up of 7 registers and 6 adders, and the third level stream treatment be made up of 1 register.
In first order stream treatment, an input of each multiplier unit is all connected with at different levels output of 14 grades of shift registers, its another input input coefficient C1 ~ C14 successively, the phase place adjustment that different coefficient C1 ~ C14 is corresponding different, the input of 14 grades of shift registers is connected with the output of analog to digital converter ADC20.
In first order stream treatment, two inputs of each adder are connected with the output of adjacent two multipliers respectively.
In the stream treatment of the second level, the input of each register is connected with the output of each adder in first order stream treatment respectively.
In the stream treatment of the second level, the output of every two adjunct registers is connected with the input of an adder respectively, the output of register is all made a gift to someone in adder, adder adopts cascade structure, the output of afterbody adder is connected with the input of register in third level stream treatment, and in third level stream treatment, the output of register is that the output of described decimal filtering wave by prolonging time device is connected with the input of follow-up digital processing unit 40.
As shown in Figure 3, Fig. 3 is the group delay spectrum curve of decimal filtering wave by prolonging time device coefficient C1 ~ C14 of the present utility model.This decimal filtering wave by prolonging time device is all-pass filter, and only adjust phase place, the group delay step of this decimal filtering wave by prolonging time device is 64 grades, and minimum delay resolution is 1/64 clock cycle.
As shown in Figure 4, Fig. 4 is the utility model digital component video signal handling principle schematic diagram, wherein:
Digital video signal 101 is the output signal of analog to digital converter 20;
Clipping level 111 is the synchronizing signal median of digital video signal 101;
Sampling clock 104 is sampling clocks of analog to digital converter 20;
N-th line synchronizing signal of n moment 106 representative digit vision signal 101;
(n+1)th line synchronizing signal of n+1 moment 107 representative digit vision signal 101;
Line length (integer value) M102 represents the integer sampling period between (n+1)th line synchronizing signal and the n-th line synchronizing signal;
Line length (fractional value) m103 represents the little several sampling period between (n+1)th line synchronizing signal and the n-th line synchronizing signal;
Δ start (n) 109 represents the Fractional number of the n-th line synchronizing signal clipping level;
Δ start (n+1) 110 represents the Fractional number of (n+1)th line synchronizing signal clipping level.
The particular content of the computational process 105 of Fractional number as shown in Figure 5.
As shown in Figure 5, Fig. 5 is that the utility model Fractional number calculates schematic diagram, in figure, A and C represents the sampled value in two neighbouring sample moment respectively, B represents clipping level, and Fractional number Δ start is the interval between clipping level B and C, and the computing formula of Fractional number Δ start is:
Digital processing unit 40 recovers video data by digital video signal 101, line length (integer value) M102, line length (fractional value) m103, Δ start (n) 109, Δ start (n+1) 110, the video data exported ensures that the data amount check between (n+1)th line synchronizing signal and the n-th line synchronizing signal is fixed value, and the numerical computations exporting data adopts decimal filtering wave by prolonging time device technology to realize.
Relation between line length (fractional value) m103 and line length (integer value) M102 is:
Line length (fractional value) m=line length (integer value) M+ Δ start (n)-Δ start (n+1).
This relational expression symbolically is as follows:
m＝M+Δstart(n)-Δstart(n+1)。
The input of digital processing unit 40 comprises: the sampled value of line length (integer value) M, Δ start (n), Δ start (n+1), line length (fractional value) m and analog to digital converter 20.
As shown in Figure 6, Fig. 6 is the output schematic diagram of the utility model digital processing unit 40.Line length (fractional value) m 201 shown in Fig. 3 is same values with line length (fractional value) m 103 shown in Fig. 4.The sequence 202 of 1 ~ N is the output schematic diagram of the utility model digital processing unit 40.Sequence 1,2,3 ... N-2, N-1, N split line length (fractional value) m 201 at equal intervals.Δ N203 is the interval of sequence 1 ~ N, and the computing formula of Δ N203 is:
The position coordinates expression formula of sequence 1 ~ N is respectively:
As shown in Figure 7, Fig. 7 is the output of the utility model digital processing unit 40 and input relation schematic diagram.Line length (fractional value) m103 shown in line length (fractional value) m301 and Fig. 4 shown in Fig. 4 is same value.The sequence 302 of 1 ~ N is the output schematic diagram of the utility model digital processing unit 40.Δ start (n) 109 shown in Δ start (n) 303 shown in Fig. 7 Yu Fig. 2 is same values.Shown in Fig. 7, (X) 304 is the position coordinates of X output sequence.The datum mark K of the decimal filtering wave by prolonging time device corresponding to position coordinates (X) that K shown in Fig. 7 and Δ K 305 is X output sequence and phase difference K.
The output computational process of digital processing unit 40 is:
(1) set X as X output sequence of digital processing unit 40, X scope is 1≤X≤N;
(2) calculate the position coordinates (X) of X, its computing formula is:
(3) according to position coordinates (X), the computing formula of the datum mark K and phase difference K, datum mark K that calculate decimal filtering wave by prolonging time device is:
In formula, symbol " [] " expression rounds symbol, as [10.91]=10;
The computing formula of phase difference K is:
(4) value of X output sequence is calculated according to the sampled value of analog to digital converter 30, the datum mark K of decimal filtering wave by prolonging time device and phase value Δ K.Minimum delay resolution due to decimal filtering wave by prolonging time device is 1/64 clock cycle, evaluation Δ K*64, and tabling look-up according to this evaluation obtains the coefficient C1 ~ C14 of decimal filtering wave by prolonging time device.The data that shifting function obtains 14 rank FIR filter corresponding to datum mark K are carried out to the data of input.Based on the data of 14 rank FIR filter and the coefficient C1 ~ C14 of decimal filtering wave by prolonging time device, namely calculate the value of X output sequence.
The utility model is a kind of Analog Component Video signal decoding circuit, and this decoding circuit can resist the various changes of external environment condition, as the environmental change such as temperature, vibrations.This decoding circuit is formed primarily of crystal oscillator, analog to digital converter (ADC), decimal filtering wave by prolonging time device and digital processing.Crystal oscillator produces fixed frequency clock signal, this clock signal is given analog to digital converter (ADC) and is sampled to analog video signal, the output data of analog to digital converter (ADC) give decimal filtering wave by prolonging time device and digital processing processes, thus complete the decoding of Analog Component Video signal.
The clock signal of the Analog Component Video signal decoding in the utility model is external crystal oscillator input, and without the need to phase-locked loop clocking, the phenomenon of scalloping occurs because of vibrations in sample phase image.
The utility model digital processing unit extracts the capable synchronous characteristic information of digital component video signal, calculate the sampling number of a line vision signal, this sampling number is fractional value, and carry out resampling based on the vision signal of this sampling number to input, the data of recover at equal intervals, fixedly counting export.
Proved by reality test, the utility model can tolerate the impact that variations in temperature and strenuous vibration produce, and particularly in strenuous vibration situation, image is completely normal.
Claims (3)
1. an Analog Component Video signal decoding circuit for anti-vibration, is characterized in that: it comprises crystal oscillator (10), analog to digital converter ADC(20), decimal filtering wave by prolonging time device (30) and digital processing unit (40);
The output of described crystal oscillator (10) and analog to digital converter ADC(20) clock signal input be connected, crystal oscillator (10) for generation of the clock signal (50) of fixed frequency, and is transferred to follow-up analog to digital converter ADC(20);
Described analog to digital converter ADC(20) input be connected with Analog Component Video signal input part (60), analog to digital converter ADC(20) output to input with one of digital processing unit (40) respectively and the input of decimal filtering wave by prolonging time device (30) is connected, analog to digital converter ADC(20) for Analog Component Video signal is converted to digital component video signal, and be transferred to follow-up digital processing unit (40) and decimal filtering wave by prolonging time device (30);
Another of the output of described decimal filtering wave by prolonging time device (30) and digital processing unit (40) inputs and is connected, and decimal filtering wave by prolonging time device (30) is for entering horizontal phasing control to digital component video signal;
Digital processing unit (40), processes digital component video signal, by the extraction to digital component video signal line synchronous characteristic, and samples to digital component video signal, and the data of recover at equal intervals, fixedly counting export.
2. the Analog Component Video signal decoding circuit of a kind of anti-vibration according to claim 1, it is characterized in that: described decimal filtering wave by prolonging time device (30) is all-pass filter, described all-pass filter does not change the amplitude-frequency characteristic of digital component video signal, only changes the phase place of digital component video signal.
3. the Analog Component Video signal decoding circuit of a kind of anti-vibration according to claim 1 and 2, it is characterized in that: described decimal filtering wave by prolonging time device (30) adopts 14 rank FIR filter structures, it comprises: the first order stream treatment be made up of 14 grades of shift registers, 14 multiplier units and 7 adders, the second level stream treatment be made up of 7 registers and 6 adders, and the third level stream treatment be made up of 1 register;
In first order stream treatment, an input of each multiplier unit is all connected with at different levels output of 14 grades of shift registers, its another input input coefficient C1 ~ C14 successively, the phase place adjustment that different coefficient C1 ~ C14 is corresponding different, input and the analog to digital converter ADC(20 of 14 grades of shift registers) output be connected;
In first order stream treatment, two inputs of each adder are connected with the output of adjacent two multipliers respectively;
In the stream treatment of the second level, the input of each register is connected with the output of each adder in first order stream treatment respectively;
In the stream treatment of the second level, the output of every two adjunct registers is connected with the input of an adder respectively, the output of register is all made a gift to someone in adder, adder adopts cascade structure, the output of afterbody adder is connected with the input of register in third level stream treatment, and in third level stream treatment, the output of register is that the output of described decimal filtering wave by prolonging time device is connected with the input of follow-up digital processing unit (40).
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| CN201420607331.7U CN204131622U (en) | 2014-10-20 | 2014-10-20 | A kind of Analog Component Video signal decoding circuit of anti-vibration |
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| CN201420607331.7U CN204131622U (en) | 2014-10-20 | 2014-10-20 | A kind of Analog Component Video signal decoding circuit of anti-vibration |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105516631A (en) * | 2014-10-20 | 2016-04-20 | 成都振芯科技股份有限公司 | Anti-vibration analog component video signal decoding circuit |
| CN110445993A (en) * | 2019-08-23 | 2019-11-12 | 中国航空无线电电子研究所 | A kind of video acquisition system of no phase-locked loop clock |
-
2014
- 2014-10-20 CN CN201420607331.7U patent/CN204131622U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105516631A (en) * | 2014-10-20 | 2016-04-20 | 成都振芯科技股份有限公司 | Anti-vibration analog component video signal decoding circuit |
| CN105516631B (en) * | 2014-10-20 | 2018-06-05 | 成都振芯科技股份有限公司 | A kind of Analog Component Video signal decoding circuit of anti-vibration |
| CN110445993A (en) * | 2019-08-23 | 2019-11-12 | 中国航空无线电电子研究所 | A kind of video acquisition system of no phase-locked loop clock |
| CN110445993B (en) * | 2019-08-23 | 2022-03-08 | 中国航空无线电电子研究所 | Video acquisition system of non-phase-locked loop clock |
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