CN203759722U - Radio frequency reader/writer and radio frequency identification system - Google Patents
Radio frequency reader/writer and radio frequency identification system Download PDFInfo
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- CN203759722U CN203759722U CN201320893421.2U CN201320893421U CN203759722U CN 203759722 U CN203759722 U CN 203759722U CN 201320893421 U CN201320893421 U CN 201320893421U CN 203759722 U CN203759722 U CN 203759722U
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Abstract
The utility model belongs to the technical field of radio frequency identification, and provides a radio frequency reader/writer and a radio frequency identification system. The radio frequency reader-writer is connected with a read-write application terminal through an audio frequency communication interface, and integrates function units which process interaction signals between a radio frequency processing signal and the read-write application terminal into a single card reader integrated chip. Because the standard of the audio communication interface is mature and uniform, using the audio communication interface to realize data transmission can help to improve the adaptability and the universality of the radio frequency reader/writer, thereby facilitating the promotion of the radio frequency reader/writer. Meanwhile, integration of the single chip is realized, the size, weight, power consumption and cost of the radio frequency reader/writer are all substantially reduced, and the portability of the radio frequency reader/writer is improved.
Description
Technical field
The utility model belongs to REID field, relates in particular to a kind of frequency read/write and radio-frequency recognition system.
Background technology
Frequency read/write is the intelligent wireless read-write equipment that is widely used at present the fields such as fiscard mobile payment, the read-write of residents ' health card and identification, the read-write of public transport card and identification, resident identification card read-write and identification, the management of product, logistics management, and the intelligence of can achieve a butt joint touch IC-card or non-contact IC card reads and identifies.
As shown in Figure 1, the frequency read/write that prior art provides comprises: antenna, rf processing circuitry, field programmable gate array chip, processor circuit, local display circuit, peripheral interface circuit.In the time of work, antenna, for forming resonant tank with IC-card as the coil of antenna, produces the carrier wave with certain resonance frequency, utilizes this carrier wave to realize the two-way communication of data; Rf processing circuitry is for the treatment of the ultra-high frequency signal of front end; Field programmable gate array chip is for realizing the base band data encoding and decoding that radio frequency protocol specifies; Processor circuit is for realizing the certain operations interface such as redirect control and the demonstration of return data of instruction; Peripheral interface circuit is used for connecting the peripheral hardwares such as computer, mobile phone, storage card; Local display circuit is for realizing the local Presentation Function of transmission data.As shown in Figure 2, rf processing circuitry wherein further comprises and flows to two contrary signalling channels, be respectively: sendaisle, first sendaisle is produced the carrier signal of relevant work frequency by the quartz oscillator of frequency stabilization, this carrier signal by modulation circuit by carrying out amplitude shift key modulation by the carry information sequence of sending out of Manchester or modification Miller or NRZ rule encoding, after amplifying finally by drive amplification circuit, sent by antenna; Receiving cable, receiving cable first by filtering circuit filtering antenna reception to high-frequency signal in interference and noise, to extract the faint answer signal of IC-card, then by amplifying circuit and by sending field programmable gate array chip further to process after demodulator circuit demodulation.
The above-mentioned frequency read/write that prior art provides has following shortcoming: one, processor circuit is to be received and had the operational order that send the read-write application terminal of upper application software by peripheral interface circuit, read-write application terminal connects peripheral interface circuit by exclusive data interface, and the exclusive data interface standard that different manufacturers adopts differs, cause the suitability of frequency read/write not high, versatility is poor, is unfavorable for the popularization of product; Two, rf processing circuitry, field programmable gate array chip, processor circuit are discrete individual chips, make the volume of frequency read/write large, weight is large, power consumption and cost high, be not easy to carrying of frequency read/write.
Utility model content
The purpose of this utility model is to provide a kind of frequency read/write, being intended to solve existing frequency read/write adopts exclusive data interface to connect peripheral hardware, cause the problem that frequency read/write suitability is not high, and existing frequency read/write integrated level is low, cause that frequency read/write volume is large, weight is large, power consumption and cost is high, the problem of carrying that is not easy to frequency read/write.
The utility model is achieved in that a kind of frequency read/write, and described frequency read/write comprises:
Antenna;
Connect described antenna, send IC-card is carried out to the command sequence of bottom operation and the high-frequency signal that is loaded with response data that described IC-card is imported into through described antenna process the to meet with a response rf processing circuitry of signal via described antenna;
Connect described rf processing circuitry, and connect read-write application terminal by voice communication interface, the order that described read-write application terminal is sent by described voice communication interface is decoded to obtain described digital signal to be resolved to the described response signal that sends to described rf processing circuitry after command sequence and described rf processing circuitry is obtained after can discriminating digit signal and is processed to meet with a response and return to the card reader integrated chip of described read-write application terminal after data by described voice communication interface.
Wherein, described read write line integrated chip can comprise:
System bus;
Be mounted to the control register on described system bus;
Be mounted on described system bus and connect the communications interface unit of described rf processing circuitry;
Connect the voice communication interface of described read-write application terminal;
Be mounted on described system bus the described response signal that described rf processing circuitry is inputted by described communications interface unit process to meet with a response data configure the processor of the value of described control register;
Connect described read-write application terminal, the described order that described read-write application terminal is sent by described voice communication interface is carried out binary conversion treatment and is extracted the voltage comparator of the hopping edge after binaryzation;
Be mounted on described system bus and connect described read-write application terminal and voltage comparator, the described response data of calculating the time interval between the adjacent hopping edge that described voltage comparator extracts and respectively the value of each time interval and described control register being compared to obtain multidigit valid data and described processor is obtained carries out by described voice communication interface, the response data after respective handling being returned to after respective handling the audio signal processing unit of described read-write application terminal.
Further, described frequency read/write also can comprise rechargeable battery, and described read write line integrated chip also can comprise:
Connect described rechargeable battery, described rechargeable battery is carried out to the battery protecting circuit of short-circuit protection, overcurrent protection, over-charge protective and/or Cross prevention;
Connect described rechargeable battery, realize management of charging and discharging to described rechargeable battery and the current charged state of described rechargeable battery is sent in real time to the battery management unit of described processor.
Further, described read write line integrated chip also can comprise: connect external power source or described rechargeable battery, the voltage transitions of external power source or the output of described rechargeable battery is become to the voltage conversion unit of exporting to corresponding electricity consumption part after the required voltage of each electricity consumption some work in described read write line integrated chip;
Be connected in the current supply circuit of described each electricity consumption part, whether the supply voltage that detects corresponding electricity consumption part is abnormal and testing result is sent to the detecting unit of described processor.
Further, described read write line integrated chip also can comprise: the Peripheral Interface unit of carry on described system bus; Described Peripheral Interface unit comprises: UART interface, USB interface, ISO/IEC7816 standard interface, SPI, parallel interface, I2C bus interface, SWP/eSWP interface, NFC-WI interface and/or memory controller;
The external E-SAM card of described ISO/IEC7816 standard interface, P-SAM card, contact storage card, cipher card or smart chip card.。
Further, described read write line integrated chip also can comprise:
Randomizer;
Connect the encryption/decryption element of described processor, described encryption/decryption element is 3DES encryption and decryption module, AES encryption and decryption module, RSA encryption and decryption module, SM1 encryption and decryption module, SM2 encryption and decryption module, SM3 encryption and decryption module, SM4 encryption and decryption module.
Further, described read write line integrated chip also can comprise: carry is on described system bus and connect the low power consumption control unit of described audio signal processing unit or described rf processing circuitry, and described low power consumption control unit can comprise:
As the work register of the trigger of described audio signal processing unit or the trigger of described rf processing circuitry;
Carry is on described system bus and be operated under described system clock the clock enable register of output clock enable signal under the configuration of described processor;
Connect described clock enable register and described work register and be operated under described system clock, producing Clock gating signal and described Clock gating signal is exported to the clock gating unit of described work register according to described clock enable signal;
Carry is on described system bus and be operated under described system clock, under the configuration of described processor the work enable register of output services enable signal in;
Connect described work register, from the input signal of described mode of operation selected cell, select the data input signal of described work register and described data input signal is exported to the mode of operation selected cell of described work register according to described work enable signal.
Further, described communications interface unit can be UART interface, USB interface, SPI, parallel interface, I2C bus interface.
Further, described voice communication interface can comprise three signal wires and a ground wire, and described three signal wires comprise the right-channel signals line that transmit to the signal of described read write line integrated chip to left channel signals line, realization charging or the described read-write application terminal of the signal transmission of described read write line integrated chip realization charging or described read-write application terminal and realize the microphone signal line of described read write line integrated chip to the signal transmission of described read-write application terminal.
In above-mentioned frequency read/write, described rf processing circuitry can be integrated on described read write line integrated chip.
In above-mentioned frequency read/write, described frequency read/write also can comprise:
Connect described antenna and meet the Circuit for Non-contact IC Chip of ISO/IEC14443 standard, TypeA/B standard, ISO/IEC15693 standard or Sony Felica standard.
Another object of the present utility model is to provide a kind of radio-frequency recognition system, comprise read-write application terminal and frequency read/write, described frequency read/write connects described read-write application terminal by voice communication interface, and described frequency read/write is frequency read/write as above.
The frequency read/write the utility model proposes is to connect read-write application terminal by voice communication interface, and each functional unit that the interactive signal between rf processing circuitry and read-write application terminal is processed is integrated in single card reader integrated chip, because voice communication interface standard is ripe unified, realize data transmission with it, can improve the suitability of frequency read/write, improve versatility, be conducive to the popularization of product, simultaneously, realize single-chip integrated, greatly reduce the volume of frequency read/write, weight, power consumption and cost, improve the portability of frequency read/write.
Brief description of the drawings
Fig. 1 is the structural drawing of the frequency read/write that provides of prior art;
Fig. 2 is the structural drawing of rf processing circuitry in Fig. 1;
Fig. 3 is the structural drawing of the frequency read/write that provides of the utility model embodiment;
Fig. 4 is the structural drawing of read write line integrated chip in Fig. 3;
Fig. 5 is that in the utility model embodiment, voltage comparator carries out the signal waveforms example after binary conversion treatment;
Fig. 6 is the structural drawing of low power consumption control unit in Fig. 4.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.
The problem existing for existing frequency read/write, the utility model proposes a kind of frequency read/write, this frequency read/write is to connect read-write application terminal by voice communication interface, and each functional unit that the interactive signal between rf processing circuitry and read-write application terminal is processed is integrated in single card reader integrated chip.
Fig. 3 shows the structure of the frequency read/write that the utility model embodiment provides, and for convenience of explanation, only shows the part relevant to the utility model embodiment.
Specifically the frequency read/write that, the utility model embodiment provides comprises: antenna 3; Connect the rf processing circuitry 1 of antenna 3, for send the command sequence of IC-card being carried out to bottom operation via antenna 3, and the high-frequency signal that is loaded with response data that IC-card is imported into through antenna 3 processes, and signal meets with a response; Connect the card reader integrated chip 2 of rf processing circuitry 1, card reader integrated chip 2 also connects read-write application terminal by voice communication interface, card reader integrated chip 2 is decoded for the order that read-write application terminal is sent by voice communication interface, obtaining can discriminating digit signal, after being resolved to command sequence, this digital signal sends to rf processing circuitry 1, and the response signal that rf processing circuitry 1 is obtained is processed, meet with a response after data, return to read-write application terminal by voice communication interface.
Wherein, read-write application terminal refers to all kinds of terminal devices that upper strata Card Reader application software are installed and have voice communication interface, for example, can be computer, mobile phone, PDA etc.
Wherein, rf processing circuitry 1 can adopt standard small size packing forms with card reader integrated chip 2, further to dwindle the volume of frequency read/write.This standard small size packing forms can be TSSOP encapsulation, QFN encapsulation etc.
Wherein, rf processing circuitry 1 can be integrated or be independent of read write line integrated chip 2, and rf processing circuitry 1 can complete identification and the read-write of the IC-card to meeting ISO/IEC14443 standard, TypeA/B standard, ISO/IEC15693 standard, ISO/IEC18092 standard, ISO/IEC21481 standard, Sony Felica standard.
Further, frequency read/write also can comprise: connect the Circuit for Non-contact IC Chip (not shown) of antenna 3, this Circuit for Non-contact IC Chip can be the IC-card chip that meets ISO/IEC14443 standard, TypeA/B standard, ISO/IEC15693 standard or Sony Felica standard.Like this, frequency read/write can directly be realized read-write operation to its this built-in Circuit for Non-contact IC Chip.
Fig. 4 shows the structure of read write line integrated chip 2 in Fig. 3.
Specifically, read write line integrated chip 2 can comprise: control register 204; Connect the communications interface unit 201 of rf processing circuitry 1; Connect the voice communication interface 202 of read-write application terminal; Processor 203, processes for the response signal that rf processing circuitry 1 is inputted by communications interface unit 201, the data that meet with a response, and the value of configuration control register 204; Voltage comparator 206, carries out binary conversion treatment for the order that read-write application terminal is sent by voice communication interface 202, and extracts the hopping edge after binaryzation; Audio signal processing unit 205, the time interval between the adjacent hopping edge extracting for calculating voltage comparer 206, and respectively the value of each time interval and control register 204 is compared, obtain multidigit valid data, and multidigit valid data are carried out sending to processor 203 after respective handling, send to rf processing circuitry 1 by processor 203 by communications interface unit 201, also carry out respective handling for the response data that processor 203 is obtained, and by voice communication interface 202, the response data after respective handling is returned to read-write application terminal; System bus 207, control register 204, communications interface unit 201, processor 203, control register 204, audio signal processing unit 205 are all mounted on system bus 207, and realize mutual by system bus 207.
Wherein, the respective handling of audio signal processing unit 205 refers to: carry out the processing such as synchronous despreading, carrier synchronization and demodulation, frame synchronization, decoding verification for the signal receiving by voice communication interface 202; For to be sently encoding to the signal of read-write application terminal, spread spectrum, and the processing such as after filtering.
Wherein, processor 203 can be the combination of central processing unit or digital signal processor or central processing unit and digital signal processor.And central processing unit or digital signal processor can be, but not limited to adopt 8,16 or 32 s' kernel.
Wherein, in the time that rf processing circuitry 1 is independent of read write line integrated chip 2, it is universal asynchronous receiving-transmitting transmitter (Universal AsynchronousReceiver/Transmitter that communications interface unit 201 can be, but not limited to, UART) interface, USB (universal serial bus) (Universal Serial Bus, USB) interface, Serial Peripheral Interface (SPI) (Serial Peripheral Interface, SPI), parallel interface, I2C bus interface etc.
Wherein, voice communication interface 202 comprises three signal wires and a ground wire.Three signal wires are respectively left channel signals line, right-channel signals line and microphone signal line.One in left channel signals line or right-channel signals line in order to realize the signal transmission of read-write application terminal to read write line integrated chip 2; Another in left channel signals line or right-channel signals line is in order to charging or realize the signal transmission of read-write application terminal to read write line integrated chip 2; Microphone signal line is in order to realize the signal transmission of read write line integrated chip 2 to read-write application terminal.
Further, the value of control register 204 can comprise flag, threshold value Configuration Values Lx, minimum effective value Lmin and the maximum effective value Lmax of carrier frequency and modulation system, and Lmin<Lx<Lmax.Voltage comparator 206 carries out signal waveforms example after binary conversion treatment as shown in Figure 5, suppose that n(n is positive integer) time interval between individual adjacent hopping edge is Ln, audio signal processing unit 205 can judge current signal transmission content: if Ln<Lmin or Ln>Lmax, represent the current undesired signal that is transmitted as, discard processing; What under non-data transmission state, Lmin<Ln<Lx represented current transmission is carrier signal, and the data bit of the current transmission of the next expression of data transmission state is identical with the value of a data before; Under non-data transmission state, Lx<Ln<Lmax represents currently for data transmission start bit, and switches to data transmission state, and the data bit of the current transmission of the next expression of data transmission state is different with the value of a data before.According to this rule, when receiving the data of a location number and proof test value is subsequently correct, these bit data are combined as to valid data word, and switch to non-data transmission state, produce look-at-me notification processor 203 simultaneously and carry out next step processing.
In the utility model embodiment, frequency read/write can be used external power source, or adopts carry rechargeable battery powered, or adopts the power supply of combining of external power source and rechargeable battery.In the time that frequency read/write comprises rechargeable battery, read write line integrated chip 2 also can comprise: battery protecting circuit 208, for rechargeable battery is carried out to short-circuit protection, overcurrent protection, over-charge protective and/or Cross prevention; Connect the battery management unit 209 of rechargeable battery 208, for realizing the management of charging and discharging to rechargeable battery 208, and the current charged state of rechargeable battery 208 is sent to processor 203 in real time, can carry out accordingly subsequent action to make processor 203, for example, if current charged state has reached certain value, can power to rechargeable battery 208 from external power supply power switching.Preferably, rechargeable battery 208 is lithium batteries.
Wherein, short-circuit protection refers to for the positive/negative Voltage-output pin of rechargeable battery and occurs that the situation of short circuit detects, and in the time short circuit being detected, carries out protection action; Overcurrent protection refers to when detecting while having larger electric current to flow through in load, controls rechargeable battery and stop to load discharge, to protect rechargeable battery; Over-charge protective, in the time detecting that the voltage of rechargeable battery rises to charge threshold, is controlled and is stopped charging to rechargeable battery; Cross prevention refers to when rechargeable battery is in discharge condition lower time, if detect when the voltage of rechargeable battery is down to discharge threshold, controls rechargeable battery and stops powering to the load.
In the utility model embodiment, read write line integrated chip 2 also can comprise: the voltage conversion unit 210 that connects external power source or rechargeable battery 208, become after the required voltage of each electricity consumption some work for the voltage transitions that external power source or rechargeable battery 208 are exported, export to corresponding electricity consumption part; Be connected to the detecting unit 211 in the current supply circuit of each electricity consumption part, whether abnormal for detection of the supply voltage of corresponding electricity consumption part, and testing result is sent to processor 203, so that processor 203 is responded in time, with protection device security of operation.
In the utility model embodiment, read write line integrated chip 2 also can comprise: the Peripheral Interface unit 212 of carry on system bus 207.Peripheral Interface unit 212 can be the peripheral interface units of the peripheral communications such as connecting fluid crystal display, touch-screen or smart card or opertaing device, can be also the memory controller that can produce external memory storage (as: external data memory) interface sequence.Further, if Peripheral Interface unit 212 is peripheral interface units, this peripheral interface units can be, but not limited to comprise: UART interface, USB interface, ISO/IEC7816 standard interface, SPI, parallel interface, I2C bus interface, SWP/eSWP interface or NFC-WI interface etc.Wherein, if peripheral interface units is ISO/IEC7816 standard interface, on ISO/IEC7816 standard interface, can connect all kinds of contact chip cards, for example: E-SAM card, P-SAM card, all kinds of contact storage card, cipher card or smart chip card etc.Wherein, if peripheral interface units is parallel interface, whether parallel interface can be selected input undesired signal to be filtered.This filtering function while leading directly to is set and does not act on, otherwise the undesired signal that duration is less than n clock period is stablized in filtering.
In the utility model embodiment, read write line integrated chip 2 also can comprise: randomizer 215, for generation of the random number of unit or multidigit; Connect the encryption/decryption element 213 of processor 203 and randomizer 215, for the random number producing according to randomizer 215, rf processing circuitry 1 is decrypted to processing by the response signal of communications interface unit 201 input processors 203, the also random number for producing according to randomizer 215, the valid data that processor 203 is received are encrypted.Preferably, encryption/decryption element 213 is 3DES encryption and decryption module, AES encryption and decryption module, RSA encryption and decryption module, SM1 encryption and decryption module, SM2 encryption and decryption module, SM3 encryption and decryption module, SM4 encryption and decryption module.
In the utility model embodiment, also can integrated data error correction and retransmission mechanism in audio signal processing unit 205, be specially: when audio signal processing unit 205 is received disturbed data, to attempt to recover correct data, some disturbing more seriously limited data and reliably reduced, to not produce answer signal, and signal source is not while receiving answer signal, will retransmit the last data that send.
In the utility model embodiment, read write line integrated chip 2 inner also curable monitoring, debugging software, can be used for IC test and assist final user's software development, now, processor 203 is after powering on and working, first judge whether certain pin is specified level value, whether need to enter monitoring, debugging mode or normal use software pattern to determine that this powers on.Read write line integrated chip 2 also can carry out the control of mode of operation by its program voltage pin institute making alive, be specially: when its program voltage pin institute making alive is high voltage, be defined as OTP programming mode, its program voltage pin institute making alive is normal mode of operation while being high level, and its program voltage pin institute making alive is forced resetting pattern while being low level.
In the utility model embodiment, read write line integrated chip 2 also can comprise: carry is on system bus 207 and connect the low power consumption control unit 214 of audio signal processing unit 205 or rf processing circuitry 1, for under the control of processor 203 and system clock, control the trigger of audio signal processing unit 205 or the trigger of rf processing circuitry 1 and export and do not overturn under off working state, thus the dynamic power consumption of reduction system.
Fig. 6 shows the structure of low power consumption control unit 214 in Fig. 4.
Because the dynamic power consumption of frequency read/write is mainly because the upset of circuit node level produces, therefore, by reducing circuit node upset, just can reach the object that reduces dynamic power consumption.Based on this, in the utility model embodiment, low power consumption control unit 214 can comprise: as the work register 2145 of the trigger of audio signal processing unit 205 or the trigger of rf processing circuitry 1, carry is on system bus 207 and be operated in the clock enable register 2141 under system clock SCLK, under the configuration at processor 203, and output clock enable signal CLKEN, connect clock enable register 2141 and work register 2145 and be operated in the clock gating unit 2142 under system clock SCLK, for producing Clock gating signal CLKX and Clock gating signal CLKX exported to work register 2145 according to clock enable signal CLKEN, and in the time that clock enable signal CLKEN is invalid clock gate-control signal CLKX constant be high level or low level, in the time that clock enable signal CLKEN is effective, the phase place of clock gate-control signal CLKX changes with the change of system clock SCLK, carry is on system bus 207 and be operated in the work enable register 2143 under system clock SCLK, under the configuration at processor 203, and output services enable signal ENABLEX, connect the mode of operation selected cell 2144 of work register 2145, be used for according to work enable signal ENABLEX, from the input signal of mode of operation selected cell 2144, select the data input signal DINX of work register 2145 and data input signal DINX is exported to work register 2145, and select the normal input signal DY of mode of operation selected cell 2144 as data input signal DINX in the time that work enable signal ENABLEX is effective, normal input signal DY is as the reset initial value input of work register 2145, in the time that work enable signal ENABLEX is invalid, select the constant initial value input signal DX of mode of operation selected cell 2144 as data input signal DINX.
Wherein, work register 2145 is the trigger of audio signal processing unit 205 or the trigger of rf processing circuitry 1.The feature of trigger is: only at clock hopping edge place, and sampled signal input, and input signal is remained in output; Under the normal mode of operation of work register 2145, when data input signal DINX is normal input signal DY, audio signal processing unit 205 or rf processing circuitry 1 just can complete corresponding processing capacity.Like this, if Clock gating signal CLKX constant be high level or low level, do not overturn, there is not clock edge, work register 44 also just can not change, and can reach the object that reduces circuit dynamic power consumption; If when work enable signal ENABLEX is invalid, the data input signal DINX that mode of operation selected cell 2144 is given work register 2145 is constant DX, now no matter whether Clock gating signal CLKX overturns, the output of work register 2145 can not be overturn, and can reach the object that reduces circuit dynamic power consumption.
For instance, if the effective value of clock enable signal CLKEN is " 0 ", invalid value is " 1 ", that is to say, when clock enable signal CLKEN is " 0 ", will open the clock of work register 2145 of audio signal processing unit 205, clock enable signal CLKEN will close the clock of work register 2145 of audio signal processing unit 205 during for " 1 "; The effective value of work enable signal ENABLEX is " 1 ", invalid value is " 0 ", that is to say, work enable signal ENABLEX will select audio signal processing unit 205 for normal function pattern while being " 1 ", work enable signal ENABLEX will select audio signal processing unit 205 for reset mode while being " 0 ", and work register 44 will stop upset.In the time that processor 203 arranges work enable signal ENABLEX and is effective value " 1 ", mode of operation selected cell 2144 selects the normal input signal DY of mode of operation selected cell 2144 as data input signal DINX, if it is effective value " 0 " that processor 203 arranges clock enable signal CLKEN simultaneously, thereby Clock gating signal CLKX is enabled, and work register 2145 can normally be worked; In the time that processor 203 arranges work enable signal ENABLEX and is invalid value " 0 ", mode of operation selected cell 2144 selects the constant initial value input signal DX of mode of operation selected cell 2144 as data input signal DINX, now, no matter whether clock enable signal CLKEN is effective, work register 2145 will keep the normal value of output, to reduce dynamic power consumption; In the time that processor 203 arranges clock enable signal CLKEN and is invalid value " 1 ", Clock gating signal CLKX is constant " 1 ", can not overturn, to reduce dynamic power consumption, because the dynamic power consumption of clock is the main dynamic power consumption of frequency read/write, therefore reduce clock dynamic power consumption, will greatly reduce the overall dynamics power consumption of frequency read/write.
In addition, the utility model embodiment also provides a kind of radio-frequency recognition system, comprises read-write application terminal and frequency read/write as above, is not repeated herein.
In sum, first, the frequency read/write the utility model proposes is to connect read-write application terminal by voice communication interface, and each functional unit that the interactive signal between rf processing circuitry and read-write application terminal is processed is integrated in single card reader integrated chip, because voice communication interface standard is ripe unified, realize data transmission with it, can improve the suitability of frequency read/write, improve versatility, be conducive to the popularization of product, simultaneously, realize single-chip integrated, greatly reduce the volume of frequency read/write, weight, power consumption and cost, improve the portability of frequency read/write.Secondly, this frequency read/write provides abundant and interface unit has flexibly been realized modularization, has reduced the complexity of the more most advanced and sophisticated IC-card application system of exploitation.Finally, employing clock enables and work enables two kinds of modes, has greatly reduced the dynamic power consumption of frequency read/write, has realized the object of prolongs standby time.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all any amendments of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection domain of the present utility model.
Claims (12)
1. a frequency read/write, is characterized in that, described frequency read/write comprises:
Antenna;
Connect described antenna, send IC-card is carried out to the command sequence of bottom operation and the high-frequency signal that is loaded with response data that described IC-card is imported into through described antenna process the to meet with a response rf processing circuitry of signal via described antenna;
Connect described rf processing circuitry, and connect read-write application terminal by voice communication interface, the order that described read-write application terminal is sent by described voice communication interface is decoded to obtain described digital signal to be resolved to the described response signal that sends to described rf processing circuitry after command sequence and described rf processing circuitry is obtained after can discriminating digit signal and is processed to meet with a response and return to the card reader integrated chip of described read-write application terminal after data by described voice communication interface.
2. frequency read/write as claimed in claim 1, is characterized in that, described read write line integrated chip comprises:
System bus;
Be mounted to the control register on described system bus;
Be mounted on described system bus and connect the communications interface unit of described rf processing circuitry;
Connect the voice communication interface of described read-write application terminal;
Be mounted on described system bus the described response signal that described rf processing circuitry is inputted by described communications interface unit process to meet with a response data configure the processor of the value of described control register;
Connect described read-write application terminal, the described order that described read-write application terminal is sent by described voice communication interface is carried out binary conversion treatment and is extracted the voltage comparator of the hopping edge after binaryzation;
Be mounted on described system bus and connect described read-write application terminal and voltage comparator, the described response data of calculating the time interval between the adjacent hopping edge that described voltage comparator extracts and respectively the value of each time interval and described control register being compared to obtain multidigit valid data and described processor is obtained carries out by described voice communication interface, the response data after respective handling being returned to after respective handling the audio signal processing unit of described read-write application terminal.
3. frequency read/write as claimed in claim 2, is characterized in that, described frequency read/write also comprises rechargeable battery, and described read write line integrated chip also comprises:
Connect described rechargeable battery, described rechargeable battery is carried out to the battery protecting circuit of short-circuit protection, overcurrent protection, over-charge protective and/or Cross prevention;
Connect described rechargeable battery, realize management of charging and discharging to described rechargeable battery and the current charged state of described rechargeable battery is sent in real time to the battery management unit of described processor.
4. frequency read/write as claimed in claim 3, is characterized in that, described read write line integrated chip comprises:
Connect external power source or described rechargeable battery, the voltage transitions of external power source or the output of described rechargeable battery is become to the voltage conversion unit of exporting to corresponding electricity consumption part after the required voltage of each electricity consumption some work in described read write line integrated chip;
Be connected in the current supply circuit of described each electricity consumption part, whether the supply voltage that detects corresponding electricity consumption part is abnormal and testing result is sent to the detecting unit of described processor.
5. frequency read/write as claimed in claim 2, is characterized in that, described read write line integrated chip comprises the Peripheral Interface unit of carry on described system bus;
Described Peripheral Interface unit comprises: UART interface, USB interface, ISO/IEC7816 standard interface, SPI, parallel interface, I2C bus interface, SWP/eSWP interface, NFC-WI interface and/or memory controller;
The external E-SAM card of described ISO/IEC7816 standard interface, P-SAM card, contact storage card, cipher card or smart chip card.
6. frequency read/write as claimed in claim 2, is characterized in that, described read write line integrated chip comprises:
Randomizer;
Connect the encryption/decryption element of described processor and described randomizer, described encryption/decryption element is 3DES encryption and decryption module, AES encryption and decryption module, RSA encryption and decryption module, SM1 encryption and decryption module, SM2 encryption and decryption module, SM3 encryption and decryption module, SM4 encryption and decryption module.
7. frequency read/write as claimed in claim 2, it is characterized in that, described read write line integrated chip comprises: carry is on described system bus and connect the low power consumption control unit of described audio signal processing unit or described rf processing circuitry, and described low power consumption control unit comprises:
As the work register of the trigger of described audio signal processing unit or the trigger of described rf processing circuitry;
Carry is on described system bus and be operated under described system clock the clock enable register of output clock enable signal under the configuration of described processor;
Connect described clock enable register and described work register and be operated under described system clock, producing Clock gating signal and described Clock gating signal is exported to the clock gating unit of described work register according to described clock enable signal;
Carry is on described system bus and be operated under described system clock, under the configuration of described processor the work enable register of output services enable signal in;
Connect described work register, from the input signal of described mode of operation selected cell, select the data input signal of described work register and described data input signal is exported to the mode of operation selected cell of described work register according to described work enable signal.
8. frequency read/write as claimed in claim 2, is characterized in that, described communications interface unit is UART interface, USB interface, SPI, parallel interface, I2C bus interface.
9. frequency read/write as claimed in claim 2, it is characterized in that, described voice communication interface comprises three signal wires and a ground wire, and described three signal wires comprise the right-channel signals line that transmit to the signal of described read write line integrated chip to left channel signals line, realization charging or the described read-write application terminal of the signal transmission of described read write line integrated chip realization charging or described read-write application terminal and realize the microphone signal line of described read write line integrated chip to the signal transmission of described read-write application terminal.
10. frequency read/write as claimed in claim 1, is characterized in that, described rf processing circuitry is integrated on described read write line integrated chip.
11. frequency read/writes as claimed in claim 1, is characterized in that, described frequency read/write also comprises:
Connect described antenna and meet the Circuit for Non-contact IC Chip of ISO/IEC14443 standard, TypeA/B standard, ISO/IEC15693 standard or Sony Felica standard.
12. 1 kinds of radio-frequency recognition systems, comprise read-write application terminal and frequency read/write, it is characterized in that, described frequency read/write connects described read-write application terminal by voice communication interface, and described frequency read/write is the frequency read/write as described in claim 1 to 11 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320893421.2U CN203759722U (en) | 2013-12-31 | 2013-12-31 | Radio frequency reader/writer and radio frequency identification system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320893421.2U CN203759722U (en) | 2013-12-31 | 2013-12-31 | Radio frequency reader/writer and radio frequency identification system |
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| CN203759722U true CN203759722U (en) | 2014-08-06 |
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| CN201320893421.2U Withdrawn - After Issue CN203759722U (en) | 2013-12-31 | 2013-12-31 | Radio frequency reader/writer and radio frequency identification system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103679239A (en) * | 2013-12-31 | 2014-03-26 | 深圳市吉芯微半导体有限公司 | Radio frequency reader-writer and radio frequency identification system |
| CN104732254A (en) * | 2014-10-08 | 2015-06-24 | 南京邮电大学 | Radio frequency identification reader and writer |
| CN112765077A (en) * | 2021-01-18 | 2021-05-07 | 三未信安科技股份有限公司 | PCI password card master control asynchronous dispatching system and method |
| CN113459996A (en) * | 2021-07-12 | 2021-10-01 | 深钛智能科技(苏州)有限公司 | Encrypted radio frequency decoding and pulse LED light testing system |
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2013
- 2013-12-31 CN CN201320893421.2U patent/CN203759722U/en not_active Withdrawn - After Issue
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103679239A (en) * | 2013-12-31 | 2014-03-26 | 深圳市吉芯微半导体有限公司 | Radio frequency reader-writer and radio frequency identification system |
| WO2015101067A1 (en) * | 2013-12-31 | 2015-07-09 | 深圳市吉芯微半导体有限公司 | Rfid reader/writer and rfid system |
| CN103679239B (en) * | 2013-12-31 | 2017-04-26 | 深圳市吉芯微半导体有限公司 | Radio frequency reader-writer and radio frequency identification system |
| CN104732254A (en) * | 2014-10-08 | 2015-06-24 | 南京邮电大学 | Radio frequency identification reader and writer |
| CN104732254B (en) * | 2014-10-08 | 2017-08-01 | 南京邮电大学 | Radio-frequency identification reader/writer |
| CN112765077A (en) * | 2021-01-18 | 2021-05-07 | 三未信安科技股份有限公司 | PCI password card master control asynchronous dispatching system and method |
| CN112765077B (en) * | 2021-01-18 | 2024-01-26 | 三未信安科技股份有限公司 | PCI cipher card master control asynchronous scheduling system |
| CN113459996A (en) * | 2021-07-12 | 2021-10-01 | 深钛智能科技(苏州)有限公司 | Encrypted radio frequency decoding and pulse LED light testing system |
| CN113459996B (en) * | 2021-07-12 | 2022-03-25 | 深钛智能科技(苏州)有限公司 | Encrypted radio frequency decoding and pulse LED light testing system |
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