CN202916446U - Dual-frequency GPS receiver - Google Patents
Dual-frequency GPS receiver Download PDFInfo
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- CN202916446U CN202916446U CN2011204866912U CN201120486691U CN202916446U CN 202916446 U CN202916446 U CN 202916446U CN 2011204866912 U CN2011204866912 U CN 2011204866912U CN 201120486691 U CN201120486691 U CN 201120486691U CN 202916446 U CN202916446 U CN 202916446U
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Abstract
The utility model relates to a dual-frequency GPS receiver which is composed of an antenna, a radio frequency circuit, an intermediate-frequency circuit, a digital baseband signal processor, a clock circuit, a main oscillator and a microprocessor. The radio frequency circuit is used for converting satellite signals, at L1 and L2 frequency bands of a GPS system, received by the antenna into intermediate-frequency signals; the intermediate-frequency circuit further carries out frequency conversion and digital sampling on the intermediate-frequency signals; the digital baseband signal processor is connected with the intermediate-frequency circuit and each digital channel processor in the digital baseband signal processor receives the signals transmitted by one satellite; and the microprocessor is connected with the digital baseband signal processor and is used for extracting needed navigation information from the received satellite signals. The dual-frequency GPS receiver can be used to extract carrier frequencies at the L1 and L2 bands by using a C/A code and an L2C code so that a civilian dual-frequency receiver does not rely on the codeless and semi-codeless technologies any longer and is thus not subject to electromagnetic environment and dynamic constraints.
Description
Technical field
The utility model relates to the GPS receiver, relates in particular to a kind of double-frequency GPS receiver that can be used for receiving L1 and L2 frequency range.
Background technology
Two spectral band of each gps satellite transmission, the signal of L-band transmission: one take frequency as f
1The L1 wave band of=1575.42MHz and one are take frequency as f
2The L2 wave band of=1227.6MHz.These two frequencies are f by frequency
0The base frequency of=1.023MHz multiplies each other and comes f
1=1540 * f
0, f
2=1200 * f
0Adopting L1 and two kinds of frequencies of L2 to come a reason of signal transmission is for the delay of compensating signal by ionosphere the time.The gps system of beginning is at P (Y) code of L1 band transmission C/A code and military's encryption, the L2 wave band only transmits P (Y) code that the military encrypts, so initial civilian GPS can only adopt the C/A code of L1 wave band to position, rely on ionospheric model to revise the error that gps signal brings by ionosphere.Along with the modern enforcement of GPS, the U.S. begins newly to load civil signal L2C code on the L2 wave band, and the L2C code is modulated through duplex by CM code and CL code and formed, so present civilian users also can adopt the dual-frequency receiver of L1 signal and L2 signal.
Commercial receiver can only receive the C/A coded signal at wave band of L1 at present, substantially can only eliminate ionospheric impact with model part ground, causes effectively low precision; The high-precision GPS receiver of some special dimensions adopts without code and half and recovers the carrier wave of L2 wave band without the code technology, but adopts the receiver of these technology technology larger to the loss of carrier-to-noise ratio, carrier wave cycle-skipping probability is risen, so applicability is restricted.
The utility model content
For the deficiencies in the prior art, the utility model provides a kind of double-frequency GPS receiver that can be used for receiving L1 and L2 frequency range.
The technical solution of the utility model is as follows: a kind of double-frequency GPS receiver, be comprised of antenna, radio circuit, intermediate-frequency circuit, digital baseband signal processor, clock circuit, main oscillator, microprocessor, it is characterized in that: described radio circuit becomes intermediate-freuqncy signal with the gps system L1 of antenna reception and the satellite-signal frequency conversion of L2 frequency range;
Intermediate-frequency circuit is made intermediate-freuqncy signal further frequency translation and is carried out digitized sampling;
The digital baseband signal processor is connected with intermediate-frequency circuit, and each digital channel processor receives the signal of a satellite launch in the digital baseband signal processor;
Microprocessor links to each other with the digital baseband signal processor, and it is finished and extract required navigation information from receive next satellite-signal.
Further, described main oscillator produces a master clock frequency, and local gps clock frequency is obtained by the master clock frequency conversion, and main oscillator links to each other with clock circuit, and clock circuit produces local carrier frequency LO1, LO2 and local clock sclk signal.
Further, described clock circuit comprises: frequency phase lock ring 1 circuit links to each other with the major clock of the 10MHz of input, and frequency phase lock ring 1 circuit produces local carrier frequency LO1 and LO2; Frequency phase lock ring 2 circuit link to each other with the 10MHz major clock of input, and frequency phase lock ring 2 circuit produce local clock sclk signal.
Further, described radio circuit comprises: a signal separation module is used for being separated into two parts of signals from the L1 wave band of antenna and the signal of L2 wave band;
A bandpass filter 1 links to each other with signal separation module, filtering is carried out in the signal of L1 wave band here; A low noise amplifier 1 links to each other with bandpass filter 1, and signal is amplified output GPS L1 signal; A frequency mixer is connected with low noise amplifier 1, and output signal is input to 1 li of a bandpass filter; A low noise amplifier 1 is connected with bandpass filter 1, is used for amplifying at the L1 gps signal of 1 li of the first order low noise amplifier output IF-L1 signal;
A bandpass filter 2 links to each other with signal separation module, filtering is carried out in the signal of L2 wave band here; A low noise amplifier 2 links to each other with bandpass filter 2, and signal is amplified output GPS L2 signal;
A frequency mixer is connected with low noise amplifier 2, and output signal is input to 2 li of bandpass filter; A low noise amplifier 2 is connected with bandpass filter 2, is used for amplifying output IF-L2 signal at the L2 of first order low noise amplifier 2 gps signal.
Further, described intermediate-frequency circuit contains intermediate frequency process module 1 and intermediate frequency process module 2, is respectively applied to produce a pair of synchronous orthogonal signal I
L1And Q
L1And a pair of synchronous orthogonal signal I
L2And Q
L2
Further, described intermediate frequency process module 1 and intermediate frequency process module 2 comprise: a signal separation module is used for the intermediate-freuqncy signal IF of input is separated into two part IF1 and IF2;
A frequency mixer is connected with signal separation module, is used for IF1 signal and local synchronous clock signal L02 are carried out mixing; A bandpass filter 1 is connected with frequency mixer, is used for the low frequency component of the signal after the mixing is passed through; A low noise amplifier 1 is connected with bandpass filter 1, is used for the signal of low frequency component is amplified; An A/D sampling thief 1 links to each other with low noise amplifier 1, is used for low frequency signal is carried out digitized sampling output I
L1
A frequency mixer is connected with the information separated module, and the clock signal that is used for IF1 signal and local clock L02 are carried out 90 ° of phase tranformations is carried out mixing; A bandpass filter 2 is connected with frequency mixer, is used for the low frequency component of the signal after the mixing is passed through; A low noise amplifier 2 is connected with bandpass filter 2, is used for the signal of low frequency component is amplified; An A/D sampling thief 2 links to each other with low noise amplifier 2, is used for low frequency signal is carried out digitized sampling output Q
L1
Further, described digital baseband signal processor comprises:
A multiplexer 1 is used for the signal of L1 wave band is divided into a few road I
L1And Q
L1Signal; A signal trace module 1 is connected with multiplexer 1, is used for I
L1And Q
L1Follow the tracks of processing;
A multiplexer 2 is used for the signal of L2 wave band is divided into a few road I
L2And Q
L2Signal; A signal trace module 2 is connected with multiplexer 2, is used for I
L2And Q
L2Follow the tracks of processing.
Further, described signal trace module 1 comprises:
A carrier frequency NCO is connected with two carrier wave correlators, and carrier frequency NCO forms carrier tracking loop by microprocessor control;
Two carrier wave correlators carry out carrier wave to the I road signal of the L1 signal of input and Q road signal respectively to be peeled off, and is transformed into I and the Q component of direct current DC form;
Three code correlators are connected with the carrier wave correlator of an I road signal, and code correlator is with the I of direct current form and the associated code of three kinds of forms of Q road signal correction generation, i.e. leading, instant and delay code;
Three integration totalizers 1 are connected with three code correlators respectively, and it is cumulative that the code after integration totalizer 1 will be correlated with carries out integration, then accumulated value inputed to microprocessor;
Three code correlators are connected with the carrier wave correlator of a Q road signal, and code correlator is with the I of direct current form and the associated code of three kinds of forms of Q road signal correction generation, i.e. leading, instant and delay code;
Integration totalizer 1 is connected with microprocessor, the integral time of microprocessor control integration totalizer;
A code NCO is connected with the shift register of a code generator and a N bit, and code NCO produces the clock control signal L of code generator
1f
1Clock control signal L with shift register
1f
2
The code generator links to each other with N bit shift register, and the code generator produces the C/A code;
Shift register is connected with code correlator, the local relevant chip of shift register generation, i.e. leading, instant and delay code;
Code NCO forms a code tracking loop by microprocessor control, and microprocessor is controlled code NCO and carrier frequency NCO by the value of feedback of integration totalizer input;
The code generator is connected with microprocessor, and microprocessor control code generator produces the C/A code of required tracking satellite;
N bit shift register is connected with microprocessor, and microprocessor control shift register produces conventional relevant chip and narrow relevant chip.
Further, described signal trace module 2 comprises:
A carrier frequency NCO is connected with two carrier wave correlators, and carrier frequency NCO forms carrier tracking loop by microprocessor control;
Two carrier wave correlators carry out carrier wave to L2 number I road signal of input and Q road signal respectively to be peeled off, and is transformed into I and the Q component of direct current DC form;
Three code correlators are connected with the carrier wave correlator of an I road signal, and code correlator is with the I of direct current form and the associated code of three kinds of forms of Q road signal correction generation, i.e. leading, instant and delay code;
Three integration totalizers 2 are connected with three code correlators respectively, and it is cumulative that the code after integration totalizer 2 will be correlated with carries out integration, then accumulated value inputed to microprocessor;
Three code correlators are connected with the carrier wave correlator of a Q road signal, and code correlator is with the I of direct current form and the associated code of three kinds of forms of Q road signal correction generation, i.e. leading, instant and delay code;
Integration totalizer 2 links to each other with microprocessor, the accumulation state of CM code and CL code in the integral time of microprocessor control totalizer and the control L2C code;
A code NCO is connected with the shift register of a code generator and a N bit, and code NCO produces the clock control signal L of code generator
2f
1Clock control signal L with shift register
2f
2
The code generator links to each other with N bit shift register, and the code generator produces the L2C code;
Shift register is connected with code correlator, the local relevant chip of shift register generation, i.e. leading, instant and delay code;
Code NCO forms a code tracking loop by microprocessor control, and microprocessor is controlled code NCO and carrier frequency NCO by the value of feedback of integration totalizer input;
The code generator is connected with microprocessor, and microprocessor control code generator produces the C/A code of required tracking satellite;
N bit shift register is connected with microprocessor, and microprocessor control shift register produces conventional relevant chip and narrow relevant chip.
The beneficial effects of the utility model are: dual-frequency receiver described in the utility model can utilize C/A code and L2C code to extract the carrier frequency of L1 wave band and L2 wave band, civilian dual-frequency receiver is no longer relied on without code and half nothing code technology, therefore be not subjected to electromagnetic environment and dynamic the restriction.
Description of drawings
Fig. 1 is structural representation of the present utility model;
Fig. 2 is the structural representation of the utility model clock circuit;
Fig. 3,4 is the utility model radio frequency structure synoptic diagram;
Fig. 5 is the utility model intermediate-frequency circuit structural representation;
Fig. 6 is the utility model intermediate frequency process modular structure synoptic diagram;
Fig. 7 is the structural representation of digital baseband processor in the utility model;
Fig. 8 is signal trace modular structure synoptic diagram in the utility model.
Embodiment
The utility model is described in further detail below in conjunction with drawings and Examples:
See also Fig. 1, the L1 of gps satellite and L2 signal receive by antenna (1).Antenna (1) possesses the ability that receives L1 wave band and L2 wave band, receive amplifying signal (11) by antenna (1) and be input to radio circuit (2), radio circuit (2) carries out down coversion output intermediate-freuqncy signal IF-L1 (201) and IF-L2(202) to satellite-signal, and IF-L1 and IF-L2 in intermediate-frequency circuit (3) carry out L1 and the L2 digital signal I of further frequency conversion and digitized sampling output orthogonal
L1(301), Q
L1(302), I
L2(303), Q
L2(304), the signal after the digitized sampling is input in the digital baseband signal processor (4) and is further processed, and digital baseband signal processor (4) intercoms mutually with microprocessor (7), and satellite-signal is caught and followed the tracks of.In microprocessor (7), trace information is processed the information such as the time location that calculates the user and speed.The used local clock LO1(51 of radio circuit (2)), the local clock LO2 (52) that uses in the intermediate-frequency circuit (3) and the clock signal sclk(53 that in digital baseband signal processor (4) and intermediate-frequency circuit (3), uses simultaneously) produced by clock circuit (5), clock circuit (5) receives the major clock (61) that local oscillator (6) provides.
See also Fig. 2, frequency phase lock loop circuit 1(54) carry out phase-locked to master clock signal (61) and frequency-conversion processing output LO1 (51) and LO2 (52) signal, frequency phase lock circuit 2(55) carry out phase-locked and frequency-conversion processing clock signal sclk(53 to master clock signal (61)).
See also Fig. 3 and Fig. 4, the signal (11) that antenna (1) receives is divided into two paths of signals by signal separation module (203), wherein one road signal (204) is 1575.42MHz by a centre frequency, the bandpass filter 1(205 of bandwidth BW=25MHz) signal (206) of output L1 wave band, this signal is again by a low noise amplifier 1(207) amplify and export again L1 signal (208); Other one road signal (209) is by a 1227.6MHz, the bandpass filter 2(210 of bandwidth BW=25MHz) signal (211) of output L2 wave band, this signal is again by a low noise amplifier 2(212) amplify and export again L2 signal (213).
L1 signal (208) carries out mixer action with local clock LO1 signal (51) at frequency mixer (215), signal after the mixing (216) is 175.42MHz by a centre frequency, bandwidth is the bandpass filter 1(217 of BW=25MHz), filtered signal (218) is through a low noise amplifier 1(219) amplify output intermediate frequency L1 signal IF_L1(201), L2 signal (213) carries out mixer action with local clock LO1 signal (51) at frequency mixer (222), signal after the mixing (223) is 172.4MHz by a centre frequency, bandwidth is the bandpass filter 2(224 of BW=25MHz), filtered signal (225) is through a low noise amplifier 2(226) amplify output intermediate frequency L1 signal IF_L2(202).
See also Fig. 5, intermediate-freuqncy signal IF-L1 (201) is at intermediate frequency process module 1(305) in by local clock signal LO2(52) and local clock signal sclk(53) control under carry out further frequency conversion, then carry out the L1 digital signal I of digitized sampling output orthogonal
L1(301), Q
L1(302); Intermediate-freuqncy signal IF-L1 (201) is at intermediate frequency process module 2(306) in by local clock signal LO2(52) and local clock signal sclk(53) control under carry out further frequency conversion, then carry out the L2 digital signal I of digitized sampling output orthogonal
L2(303), Q
L2(304).
See also Fig. 6, intermediate-freuqncy signal IF(201) is divided into two paths of signals by signal separation module (307), wherein one tunnel intermediate-freuqncy signal (308) and local clock signal LO2(52) in frequency mixer (309), carry out mixing, signal after the mixing (310) is by a bandpass filter 1(311) carry out filtering, filtered signal (312) is again by low noise amplifier 1(313) carry out power amplification, signal after the amplification (314) is input to A/D sampling 1(315 again) in carry out digitized sampling, A/D sampling thief 1(315 wherein) at clock signal sclk(53) control under carry out digitized sampling, the signal after the sampling is digital medium-frequency signal I
L1(301).The local clock signal (324) of other one tunnel intermediate-freuqncy signal (316) and quadrature carries out mixing in frequency mixer (317), wherein local clock signal (324) carries out phase place by LO2 signal (52) through one 90 ° phase converter (325) and changes and to obtain, signal after the mixing (318) is by a bandpass filter 2(319) carry out filtering, filtered signal (320) is again by low noise amplifier 2(321) carry out power amplification, signal after the amplification (322) is input to A/D sampling thief 2(323 again) in carry out digitized sampling, A/D sampling thief 2(323 wherein) at clock signal sclk(53) control under carry out digitized sampling, the signal after the sampling is digital medium-frequency signal Q
L1(302).
See also Fig. 7, the orthogonal signal I of L1 wave band
L1(301) and Q
L1(302) signal is input to multiplexer 1(401) in, multiplexer 1(401) under the control of the control signal (71.3) of microprocessor (7) output, select wherein one group of I
L1(402) and Q
L1(403) signal is input to signal trace module 1(404) in, signal trace module 1(404) then signal be further processed intercom mutually (71.1) with microprocessor (7), wherein multiplexer 1(401) and signal trace module 1(404) at local clock sclk(53) synchro control under; The orthogonal signal I of L2 wave band
L2(303) and Q
L2(304) signal is input to multiplexer 2(405) in, multiplexer 2(405) under the control of the control signal (71.3) of microprocessor (7) output, select wherein one group of I
L2(406) and Q
L2(407) signal is input to signal trace module 2(408) in, signal trace module 2(408) then signal be further processed intercom mutually (71.2) with microprocessor (7), wherein multiplexer 2(405) and signal trace module 2(408) at local clock sclk(53) synchro control under.
See also Fig. 8, carrier frequency NCO(422) local carrier (424) of output one road local carrier (423) and another road quadrature under the control of the control signal (71) of microprocessor (7).Local carrier (423) carries out frequency dependence with the I railway digital signal (402) of input in frequency dependence device (409), signal (410) after relevant is input to leading correlator (411.1), instant correlator (411.2) and lag correlation device (411.3) respectively with local advanced code (425), it is relevant that instantaneous code (426) and instantaneous code (427) carry out code, leading coherent signal (412.1) after relevant, instant coherent signal (412.2) and lag correlation signal (412.4) are input to integration totalizer 1(414) in carry out integration and add up, value (415) after cumulative is input in the microprocessor (7) processes integration totalizer 1(414) controlled by microprocessor control signal (71);
The local carrier of quadrature (424) carries out frequency dependence with the I railway digital signal (403) of input in frequency dependence device (416), signal (417) after relevant is input to leading correlator (418.1), instant correlator (418.2) and lag correlation device (418.3) respectively with local advanced code (425), it is relevant that instantaneous code (426) and instantaneous code (427) carry out code, leading coherent signal (419.1) after relevant, instant coherent signal (419.2) and lag correlation signal (419.4) are input to integration totalizer 2(420) in carry out integration and add up, value (421) after cumulative is input in the microprocessor (7) processes integration totalizer 2(420) controlled by microprocessor control signal (71);
Code NCO(429) at local clock sclk(53) and the control of the control signal (71) of microprocessor (7) under produce code generator (433) clock control frequency f
2(431) and the clock control frequency f of shift register (428)
1(430); The shift register of N bit (428) is in control signal (71) and the clock control frequency f of microprocessor (7)
1(430) local code (432) with code generator (433) output under the control produces local advanced code (425), instantaneous code (426) and instantaneous code (427); Code generator is in microprocessor control signal (71) and clock control frequency f
2(431) produce local code (432) under the control.
Claims (2)
1. double-frequency GPS receiver, be comprised of antenna, radio circuit, intermediate-frequency circuit, digital baseband signal processor, clock circuit, main oscillator, microprocessor, it is characterized in that: described radio circuit becomes intermediate-freuqncy signal with the gps system L1 of antenna reception and the satellite-signal frequency conversion of L2 frequency range;
Intermediate-frequency circuit is made intermediate-freuqncy signal further frequency translation and is carried out digitized sampling;
The digital baseband signal processor is connected with intermediate-frequency circuit, and each digital channel processor receives the signal of a satellite launch in the digital baseband signal processor;
Microprocessor links to each other with the digital baseband signal processor, finishes and extract required navigation information from receive next satellite-signal.
2. a kind of double-frequency GPS receiver according to claim 1, it is characterized in that: main oscillator produces a master clock frequency, local gps clock frequency is obtained by the master clock frequency conversion, main oscillator links to each other with clock circuit, and clock circuit produces local carrier frequency LO1, LO2 and local clock sclk signal.
3. a kind of double-frequency GPS receiver according to claim 2, it is characterized in that: described clock circuit comprises: a frequency phase lock loop circuit 1 links to each other with the major clock of the 10MHz of input, frequency phase lock loop circuit 2 generation local carrier frequency LO1 and LO2; A frequency phase lock loop circuit 2 links to each other with the 10MHz major clock of input, and frequency phase lock loop circuit 2 produces local clock sclk signal.
4. a kind of double-frequency GPS receiver according to claim 1, it is characterized in that: described radio circuit comprises: a signal separation module is used for being separated into two parts of signals from the L1 wave band of antenna and the signal of L2 wave band;
A bandpass filter 1 links to each other with signal separation module, filtering is carried out in the signal of L1 wave band here; A low noise amplifier 1 links to each other with bandpass filter 1, and signal is amplified output GPS L1 signal; A frequency mixer is connected with low noise amplifier 1, and output signal is input to 1 li of a bandpass filter; A low noise amplifier 1 is connected with bandpass filter 1, is used for amplifying at the L1 gps signal of 1 li of the first order low noise amplifier output IF-L1 signal;
A bandpass filter 2 links to each other with signal separation module, filtering is carried out in the signal of L2 wave band here; A low noise amplifier 2 links to each other with bandpass filter 2, and signal is amplified output GPS L2 signal;
A frequency mixer is connected with low noise amplifier 2, and output signal is input to 2 li of bandpass filter; A low noise amplifier 2 is connected with bandpass filter 2, is used for amplifying output IF-L2 signal at the L2 of first order low noise amplifier 2 gps signal.
5. a kind of double-frequency GPS receiver according to claim 1 is characterized in that: described intermediate-frequency circuit, contain intermediate frequency process module 1 and intermediate frequency process module 2, and be respectively applied to produce a pair of synchronous orthogonal signal I
L1And Q
L1And a pair of synchronous orthogonal signal I
L2And Q
L2
6. a kind of double-frequency GPS receiver according to claim 5, it is characterized in that: described intermediate frequency process module 1 and intermediate frequency process module 2 comprise: a signal separation module is used for the intermediate-freuqncy signal IF of input is separated into two part IF1 and IF2;
A frequency mixer is connected with signal separation module, is used for IF1 signal and local synchronous clock signal L02 are carried out mixing; A bandpass filter 1 is connected with frequency mixer, is used for the low frequency component of the signal after the mixing is passed through; A low noise amplifier 1 is connected with bandpass filter 1, is used for the signal of low frequency component is amplified; An A/D sampling thief 1 links to each other with low noise amplifier 1, is used for low frequency signal is carried out digitized sampling output I
L1
A frequency mixer is connected with the information separated module, and the clock signal that is used for IF1 signal and local clock L02 are carried out the 90o phase tranformation is carried out mixing; A bandpass filter 2 is connected with frequency mixer, is used for the low frequency component of the signal after the mixing is passed through; A low noise amplifier 2 is connected with bandpass filter 2, is used for the signal of low frequency component is amplified; An A/D sampling thief 2 links to each other with low noise amplifier 2, is used for low frequency signal is carried out digitized sampling output Q
L1
7. a kind of double-frequency GPS receiver according to claim 1, it is characterized in that: described digital baseband signal processor comprises:
A multiplexer 1 is used for the signal of L1 wave band is divided into a few road I
L1And Q
L1Signal; A signal trace module 1 is connected with multiplexer 1, is used for I
L1And Q
L1Follow the tracks of processing;
A multiplexer 2 is used for the signal of L2 wave band is divided into a few road I
L2And Q
L2Signal; A signal trace module 2 is connected with multiplexer 2, is used for I
L2And Q
L2Follow the tracks of processing.
8. a kind of double-frequency GPS receiver according to claim 7, it is characterized in that: described signal trace module 1 comprises:
A carrier frequency NCO is connected with two carrier wave correlators, and carrier frequency NCO forms carrier tracking loop by microprocessor control;
Two carrier wave correlators carry out carrier wave to the I road signal of the L1 signal of input and Q road signal respectively to be peeled off, and is transformed into I and the Q component of direct current DC form;
Three code correlators are connected with the carrier wave correlator of an I road signal, and code correlator is with the I of direct current form and the associated code of three kinds of forms of Q road signal correction generation, i.e. leading, instant and delay code;
Three integration totalizers 1 are connected with three code correlators respectively, and it is cumulative that the code after integration totalizer 1 will be correlated with carries out integration, then accumulated value inputed to microprocessor;
Three code correlators are connected with the carrier wave correlator of a Q road signal, and code correlator is with the I of direct current form and the associated code of three kinds of forms of Q road signal correction generation, i.e. leading, instant and delay code;
Integration totalizer 1 is connected with microprocessor, the integral time of microprocessor control integration totalizer;
A code NCO is connected with the shift register of a code generator and a N bit, and code NCO produces the clock control signal L of code generator
1f
1Clock control signal L with shift register
1f
2
The code generator links to each other with N bit shift register, and the code generator produces the C/A code;
Shift register is connected with code correlator, the local relevant chip of shift register generation, i.e. leading, instant and delay code;
Code NCO forms a code tracking loop by microprocessor control, and microprocessor is controlled code NCO and carrier frequency NCO by the value of feedback of integration totalizer input;
The code generator is connected with microprocessor, and microprocessor control code generator produces the C/A code of required tracking satellite;
N bit shift register is connected with microprocessor, and microprocessor control shift register produces conventional relevant chip and narrow relevant chip.
9. a kind of double-frequency GPS receiver according to claim 7, it is characterized in that: described signal trace module 2 comprises:
A carrier frequency NCO is connected with two carrier wave correlators, and carrier frequency NCO forms carrier tracking loop by microprocessor control;
Two carrier wave correlators carry out carrier wave to L2 number I road signal of input and Q road signal respectively to be peeled off, and is transformed into I and the Q component of direct current DC form;
Three code correlators are connected with the carrier wave correlator of an I road signal, and code correlator is with the I of direct current form and the associated code of three kinds of forms of Q road signal correction generation, i.e. leading, instant and delay code;
Three integration totalizers 2 are connected with three code correlators respectively, and it is cumulative that the code after integration totalizer 2 will be correlated with carries out integration, then accumulated value inputed to microprocessor;
Three code correlators are connected with the carrier wave correlator of a Q road signal, and code correlator is with the I of direct current form and the associated code of three kinds of forms of Q road signal correction generation, i.e. leading, instant and delay code;
Integration totalizer 2 links to each other with microprocessor, the accumulation state of CM code and CL code in the integral time of microprocessor control totalizer and the control L2C code;
A code NCO is connected with the shift register of a code generator and a N bit, and code NCO produces the clock control signal L of code generator
2f
1Clock control signal L with shift register
2f
2
The code generator links to each other with N bit shift register, and the code generator produces the L2C code;
Shift register is connected with code correlator, the local relevant chip of shift register generation, i.e. leading, instant and delay code;
Code NCO forms a code tracking loop by microprocessor control, and microprocessor is controlled code NCO and carrier frequency NCO by the value of feedback of integration totalizer input;
The code generator is connected with microprocessor, and microprocessor control code generator produces the C/A code of required tracking satellite;
N bit shift register is connected with microprocessor, and microprocessor control shift register produces conventional relevant chip and narrow relevant chip.
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| CN2011204866912U CN202916446U (en) | 2012-05-22 | 2012-05-22 | Dual-frequency GPS receiver |
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| CN2011204866912U CN202916446U (en) | 2012-05-22 | 2012-05-22 | Dual-frequency GPS receiver |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105607076A (en) * | 2015-12-23 | 2016-05-25 | 北京时代民芯科技有限公司 | Beidou 2nd generation B1 and B3 double-frequency receiver |
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2012
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105607076A (en) * | 2015-12-23 | 2016-05-25 | 北京时代民芯科技有限公司 | Beidou 2nd generation B1 and B3 double-frequency receiver |
| CN105607076B (en) * | 2015-12-23 | 2018-01-19 | 北京时代民芯科技有限公司 | A kind of Beidou II B1 and B3 dual-frequency receivers |
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