CN202837399U - Synchronized phasor measurement apparatus - Google Patents
Synchronized phasor measurement apparatus Download PDFInfo
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- CN202837399U CN202837399U CN201220430918.6U CN201220430918U CN202837399U CN 202837399 U CN202837399 U CN 202837399U CN 201220430918 U CN201220430918 U CN 201220430918U CN 202837399 U CN202837399 U CN 202837399U
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Abstract
The utility model discloses a synchronized phasor measurement apparatus, comprising an AC module, an intelligent DI module, an intelligent DO module, an intelligent AI module, an intelligent AO module, an intelligent SIG module, a CPU module, an HMI module, a power supply module and a motherboard module. The motherboard module provides a uniform power interface and an intelligent IO bus interface for each module. An IO plugin interface on the motherboard can be inserted with various types of IO modules and module interchanging is realized by configuration. The synchronized phasor measurement apparatus employs an FPGA to sample and calculate, thereby preventing frequent interruption of the CPU and liberating the CPU form complex and tedious DFT calculations so as to focus on communication, so that communication real-time can be guaranteed. At the same time, an intelligent IO bus mode is employed and the electrical interface definition at each IO position on the motherboard is consistent, so that a module at some position of the motherboard could be flexibly configured as the DI module, the DO module or the AI module and the AO module through configuration files; the position of each IO module on the motherboard is not fixed any more, but can be configured flexibly; and the synchronized phasor measurement apparatus is very convenient in engineering applications.
Description
Technical field
The utility model relates to the synchronous phasor measuring device of a kind of relay protection of power system and automatic safety device, belongs to technical field of relay protection.
Background technology
Along with the development of China's power grid construction, grid structure is day by day perfect, also becomes increasingly complex, and strengthens the dynamic security monitoring capacity of electrical network in the urgent need to new technological means is arranged, and improves the electricity net safety stable level.Tradition SCADA system acquisition be the steady state data that second level refreshes, fault oscillograph provides before and after the fault fast transient Wave data in a period of time, the Dynamic Phasors data that provide the network-wide basis inter-sync to gather of all having no idea.Synchronous phasor measuring device (PMU) then utilizes the satellite synchronizing clock system to provide unified sampling pulse and the standard time for the whole network synchronized sampling in the wide scope; so that identical time reference point and sampling reference point have been arranged between each website; the dynamic process that resulting synchronized phasor can the accurate description real system at synchronized sampling and after calculating,, observing and controlling novel protected for electric system, safety and stability is controlled that new data source is provided.
Conventional PMU device generally adopts CPU to cooperate the mode of software to sample and DFT calculates, the duty ratio of CPU is heavier, its intake (DI) generally is directly to draw from the CPU module with the amount of leaving (DO) simultaneously, by connecting between the hardwire on the motherboard and the corresponding module, DI and DO module location comparison are fixed on motherboard like this, are unfavorable for the flexible expansion of engineering.
The utility model content
For overcoming the deficiency on the prior art, the utility model purpose is to be to provide a kind of CPU is freed the communication of being absorbed in from a large amount of digital operations, guarantee the synchronous phasor measuring device of the real-time of communication, greatly improved the adaptive faculty of device to different engineerings.
For achieving the above object, technical solutions of the utility model are as follows:
A kind of synchronous phasor measuring device is characterized in that, comprising:
The motherboard module of power supply and intelligent IO bus interface is provided for each module;
Linking to each other with above-mentioned motherboard module, is the AC module of the weak electric signal that can identify of AD chip with the secondary voltage current conversion;
According to the light current AC signal from above-mentioned AC module gained, adopt fpga chip lower synchronously at satellite standard synchronous clock time reference signal, the CPU module of sampling and calculating;
Link to each other with above-mentioned motherboard module, be used for the intelligent DI module of intake signals collecting;
Link to each other with above-mentioned motherboard module, be used for the intelligent DO module that the amount of leaving drives;
Link to each other with above-mentioned motherboard module, be used for the intelligent AI module of 4～20mA signals collecting;
Link to each other with above-mentioned motherboard module, be used for the intelligent AO module of 4～20mA signal output;
Link to each other with above-mentioned motherboard module, the intelligent SIG module of various central alarm signals is provided;
Link to each other with above-mentioned motherboard module, the power supply module of working power is provided for each module;
Link to each other with above-mentioned motherboard module, be used for the HMI module of managing printing machine and man-machine interface.
The CPU module also accesses 1PPS signal and the B coded signal of satellite standard synchronous clock, to realize synchronized sampling.
The motherboard module also is provided with intelligent IO bus interface, to realize the exchange of IO module.
Be provided with a plurality of IO plug-in units on the described intelligent IO bus connection motherboard, each described IO module carries out exchanges data by intelligent IO bus and CPU, and each IO card address disposes DI, DO, AI, AO pattern.
A kind of synchronous phasor measuring device comprises:
Adopt the AC module of measuring level light current mutual inductor;
Be used for driving and leave relay, the intelligent DO module that directly is connected with motherboard intelligence IO bus;
Be used for intake and measure, the intelligent DI module that directly is connected with motherboard intelligence IO bus;
Be used for providing central signal, the intelligent SIG module that directly is connected with motherboard intelligence IO bus;
Be used for measuring 4～20mA direct current signal, the intelligent AI module that directly is connected with motherboard intelligence IO bus;
Be used for driver output 4～20mA direct current signal, the intelligent AO module 6 that directly is connected with motherboard intelligence IO bus;
Be used for sampling and calculate and real-time Communication for Power, the CPU module that directly is connected with motherboard intelligence IO bus;
Be used for the control printer, with background communication, custodian's machine interactive interface, the HMI module that directly is connected with motherboard intelligence IO bus;
Be used to each module of device that the power supply module of power supply is provided;
For the motherboard module that all modules are coupled together;
Above-mentioned host CPU module contains independently CPU processor and FPGA and relevant software programs, by the FPGA calculating of sampling.
Above-mentioned HMI module contains only CPU processor and relevant software programs.
Above-mentioned power supply module provides normally closed node, so that the closed alarm of device node when losing power supply.
Above-mentioned motherboard module provides unified bus interface and power interface by intelligent IO bus for each IO module (comprising DI, DO, AI, AO), so the position of each IO module can flexible configuration becomes AI, AO or DI, DO pattern.
The beneficial effects of the utility model are: adopt synchronous phasor measuring device of the present utility model that two benefits are arranged, one is based on intelligent IO bus with each DI, DO, AI, the AO module couples together, according to different requirement of engineering, each module flexible configuration on the device can be become not same module, such as need not AI in the conventional substation side, the AO module, but need to measure a lot of intakes, then more module can be configured to the DI module, need to measure and export 4～20mA signal at Power Plant Side, and switching value quantity is fewer, then need to dispose AI, AO module, DI module be less configuration then; The 2nd, the sampling of device and calculate and to be finished by FPGA in the CPU module from the large DFT recursion of operand with free the sampling interruption frequently, is absorbed in CPU real-time Communication for Power, thereby has been improved the system communication performance.
Description of drawings
Fig. 1 is the block scheme according to a kind of synchronous phasor measuring device of the present utility model;
Fig. 2 is the theory diagram of CPU module of the present utility model.
Among the figure: 1, AC module; 2, intelligent DO module; 3, intelligent DI module; 4, intelligent SIG module; 5, intelligent AI module; 6, intelligent AO module; 7, CPU module; 8, HMI module; 9, power supply module module; 10, motherboard module.
Embodiment
Following examples are used for explanation the utility model, but are not used for limiting scope of the present utility model.Below in conjunction with accompanying drawing, be described in detail.
The disclosed PMU device of the utility model then adopts FPGA to sample and calculates, and CPU is freed the communication of being absorbed in from a large amount of digital operations, guarantees the real-time of communication; Adopt simultaneously intelligent IO mode bus, each position electric interfaces definition is consistent on the motherboard, can be neatly the module of certain position on the motherboard be configured to DI by configuration file, DO or AI, the AO module, each module position on the motherboard is no longer fixing like this, but can flexible configuration, engineering is very convenient in using, such as in some engineering, there not being 4～20mA signal, but need to gather a lot of switching values, then can dispose some more DI modules, originally belong to AI, the position of AO module also can be configured to the DI module, has so greatly improved the adaptive faculty of device to different engineerings.
Fig. 1 is the overall block-diagram according to a kind of synchronous phasor measuring device of the present utility model.Be converted into behind secondary voltage among the figure (being rated for 100V line voltage) and electric current (being rated for 1A) the measurement level light current mutual inductor by AC module 1 that the AD chip can measure ± the 5V signal, through access the AD conversion chip of CPU module 7 after the low-pass filtering by motherboard, under the control of FPGA, carry out AD sampling and calculating.In order to realize synchronized sampling, B code time signal and 1PPS pps pulse per second signal access FPGA with satellite standard synchronous clock, the sampling pulse of FPGA device is synchronized with the 1PPS signal, and after each sampled point is finished, stamp the temporal information that is accurate to ns, can realize like this synchronized sampling and the calculating of the whole network; The theory diagram of CPU module is seen Fig. 2.
Intelligence IO bus connects each the IO plug-in unit on the motherboard, be that electric interfaces on each IO card address is the same, each IO module carries out exchanges data by intelligent IO bus and CPU, rather than by the hardwire connection, each IO card address can flexible configuration be DI, DO, AI, AO pattern like this.
A kind of synchronous phasor measuring device of the present utility model, hardware unit and related software programming two parts, described hardware components is by AC module 1, intelligent DO module 2, intelligent DI module 3, intelligent SIG module 4, intelligent AI module 5, intelligence AO module 6, CPU module 7, HMI module 8, power supply module 9, motherboard module 10 form, and described software has CPU program, FPGA program, DO module interface routine, DI module interface routine, AO module interface routine, AI module interface routine, HMI module program.Described AC module 1, intelligent DO module 2, intelligent DI module 3, intelligent SIG module 4, intelligent AI module 5, intelligent AO module 6, CPU module 7, HMI module 8, power supply module 9 all are connected on the motherboard module 10.Its workflow is: be converted into behind the electric system secondary voltage electric current process AC module 1 ± 5V signal input CPU module 7, the fpga chip of CPU module 7 at a high speed mails to data concentrator by Ethernet interface in calculatings of sampling synchronously of 1PPS pulse signal and B code time signal after the formation synchronized phasor data; The collection of switching value is then finished by intelligent DI module, gathered required DI signal after, data packings is sent to CPU by intelligent IO bus; When switching value drives, by CPU the respective switch amount is input to the intelligent DO module of appointment through intelligent IO bus, this intelligence DO module is strictly differentiated Frame and whether is belonged to this module, then drives in this way corresponding relay outlet, otherwise abandons this Frame; The collection of 4～20mA direct current signal is finished by intelligent AI, gathered required direct current signal after, CPU module 7 is mail in data packings; When 4～20mA direct current signal drives, be sent to corresponding intelligent AO module by module 7 digital signal that this 4～20mA direct current signal is corresponding, this intelligence AO module is differentiated the Frame of receiving by the address and whether is belonged to this module, then this signal is converted to 4～20mA direct current signal in this way, and through output after the isolation, otherwise abandon this Frame.
Above-mentioned said CPU module 1 adopts CPU and the FPGA technical grade chip of 32 bit strip flating point registers, and dominant frequency is up to 400M, extend out 32MB NOR FLASH, 256MB NAND FLASH, 64MB SDRAM can satisfy the sampling request of 1024 in the every cycle of power frequency component.
Above-mentioned said AI, AO, DI, DO module are worked out special signal procedure, can carry out exchanges data with CPU, and regularly carry out hardware check.
Above-mentioned said HMI module adopts resistance-capacitance type touch-screen and the wide temperature liquid crystal of technical grade, can adapt to various rugged surroundings.
In the present embodiment, above-mentioned intelligent DO module 2, intelligent SIG module 4, intelligent AI module 5 and intelligent AO module 6 all contain independently CPU processor.
Adopt synchronous phasor measuring device of the present utility model that two benefits are arranged, one is based on intelligent IO bus couples together each DI, DO, AI, AO module, according to different requirement of engineering, each module flexible configuration on the device can be become not same module, such as need not AI, AO module in the conventional substation side, but need to measure a lot of intakes, then more module can be configured to the DI module, need to measure and export 4～20mA signal at Power Plant Side, and switching value quantity is fewer, then need to dispose AI, AO module, the DI module is less configuration then; The 2nd, the sampling of device and calculate and to be finished by FPGA in the CPU module from the large DFT recursion of operand with free the sampling interruption frequently, is absorbed in CPU real-time Communication for Power, thereby has been improved the system communication performance.
More than show and described ultimate principle of the present utility model and principal character and advantage of the present utility model.The technician of the industry should understand; the utility model is not restricted to the described embodiments; that describes in above-described embodiment and the instructions just illustrates principle of the present utility model; under the prerequisite that does not break away from the utility model spirit and scope; the utility model also has various changes and modifications, and these changes and improvements all fall in claimed the utility model scope.The claimed scope of the utility model is defined by appending claims and equivalent thereof.
Claims (4)
1. a synchronous phasor measuring device is characterized in that, comprising:
The motherboard module of power supply and intelligent IO bus interface is provided for each module;
Linking to each other with above-mentioned motherboard module, is the AC module of the weak electric signal that can identify of AD chip with the secondary voltage current conversion;
According to the light current AC signal from above-mentioned AC module gained, adopt fpga chip lower synchronously at satellite standard synchronous clock time reference signal, the CPU module of sampling and calculating;
Link to each other with above-mentioned motherboard module, be used for the intelligent DI module of intake signals collecting;
Link to each other with above-mentioned motherboard module, be used for the intelligent DO module that the amount of leaving drives;
Link to each other with above-mentioned motherboard module, be used for the intelligent AI module of 4～20mA signals collecting;
Link to each other with above-mentioned motherboard module, be used for the intelligent AO module of 4～20mA signal output;
Link to each other with above-mentioned motherboard module, the intelligent SIG module of various central alarm signals is provided;
Link to each other with above-mentioned motherboard module, the power supply module of working power is provided for each module;
Link to each other with above-mentioned motherboard module, be used for the HMI module of managing printing machine and man-machine interface.
2. synchronous phasor measuring device according to claim 1 is characterized in that, described CPU module also accesses 1PPS signal and the B coded signal of satellite standard synchronous clock, to realize synchronized sampling.
3. synchronous phasor measuring device according to claim 1 is characterized in that, described motherboard module also is provided with intelligent IO bus interface, to realize the exchange of IO module.
4. synchronous phasor measuring device according to claim 1, it is characterized in that, be provided with a plurality of IO plug-in units on the described intelligent IO bus connection motherboard, each described IO module carries out exchanges data by intelligent IO bus and CPU, and each IO card address disposes DI, DO, AI, AO pattern.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201220430918.6U CN202837399U (en) | 2012-08-28 | 2012-08-28 | Synchronized phasor measurement apparatus |
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| CN201220430918.6U CN202837399U (en) | 2012-08-28 | 2012-08-28 | Synchronized phasor measurement apparatus |
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| CN202837399U true CN202837399U (en) | 2013-03-27 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730914A (en) * | 2014-01-20 | 2014-04-16 | 江苏省电力公司常州供电公司 | Electrical quantity based anti-islanding device and operation method thereof |
| CN104656565A (en) * | 2014-12-25 | 2015-05-27 | 南京因泰莱电器股份有限公司 | Intelligent IO device capable of being freely configured |
| CN106771599A (en) * | 2016-11-21 | 2017-05-31 | 国网四川省电力公司电力科学研究院 | Intelligent substation synchronous phasor measuring device method of testing and test device |
| CN109521272A (en) * | 2018-08-06 | 2019-03-26 | 许继集团有限公司 | A kind of synchronous phasor measuring device |
| CN109902040A (en) * | 2019-02-01 | 2019-06-18 | 京微齐力(北京)科技有限公司 | A kind of System on Chip/SoC of integrated FPGA and artificial intelligence module |
| CN109902037A (en) * | 2019-02-01 | 2019-06-18 | 京微齐力(北京)科技有限公司 | Connect the System on Chip/SoC of the FPGA and artificial intelligence module under different clock-domains |
-
2012
- 2012-08-28 CN CN201220430918.6U patent/CN202837399U/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730914A (en) * | 2014-01-20 | 2014-04-16 | 江苏省电力公司常州供电公司 | Electrical quantity based anti-islanding device and operation method thereof |
| CN103730914B (en) * | 2014-01-20 | 2016-02-03 | 江苏省电力公司常州供电公司 | The anti-islanding device differentiated based on electric parameters and method of work thereof |
| CN104656565A (en) * | 2014-12-25 | 2015-05-27 | 南京因泰莱电器股份有限公司 | Intelligent IO device capable of being freely configured |
| CN106771599A (en) * | 2016-11-21 | 2017-05-31 | 国网四川省电力公司电力科学研究院 | Intelligent substation synchronous phasor measuring device method of testing and test device |
| CN109521272A (en) * | 2018-08-06 | 2019-03-26 | 许继集团有限公司 | A kind of synchronous phasor measuring device |
| CN109902040A (en) * | 2019-02-01 | 2019-06-18 | 京微齐力(北京)科技有限公司 | A kind of System on Chip/SoC of integrated FPGA and artificial intelligence module |
| CN109902037A (en) * | 2019-02-01 | 2019-06-18 | 京微齐力(北京)科技有限公司 | Connect the System on Chip/SoC of the FPGA and artificial intelligence module under different clock-domains |
| CN109902040B (en) * | 2019-02-01 | 2021-05-14 | 京微齐力(北京)科技有限公司 | System chip integrating FPGA and artificial intelligence module |
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Granted publication date: 20130327 |