CN202818360U

CN202818360U - IRIG-B modem based on FPGA

Info

Publication number: CN202818360U
Application number: CN 201220474195
Authority: CN
Inventors: 张熀松
Original assignee: NANJING ADES ELECTRICAL CO Ltd
Current assignee: NANJING ADES ELECTRICAL CO Ltd
Priority date: 2012-09-17
Filing date: 2012-09-17
Publication date: 2013-03-20
Anticipated expiration: 2022-09-17

Abstract

The utility model provides an IRIG-B modem based on FPGA, comprising a power module, a full-duplex interface, a processing module based on FPGA and a display module, wherein the full-duplex interface, the display module and the processing module based on FPGA are connected with the power module, and the full-duplex interface and the display module are further connected with the processing module based on FPGA. The power module is used for converting an input power supply into a power supply required for the IRIG-B modem; the full-duplex interface is used for supplying signals to the processing module based on FPGA; the processing module based on FPGA is used for controlling the data flow direction of the full-duplex interface and completing IRIG-B code encoding and decoding; and the display module is driven by the output of the processing module based on FPGA to display. The IRIG-B modem based on FPGA has the advantages of small fluctuation, good long-term stability, high time precision and a flexible system.

Description

IRIG-B modulator-demodulator based on FPGA

Technical field

The utility model relates to a kind of IRIG-B modulator-demodulator, and particularly relevant for a kind of IRIG-B modulator-demodulator based on FPGA.

Background technology

The power industry automaticity is more and more higher, and the equipment such as protection, communication, telemechanical, monitoring, recording, direct current all need the time high unity, are convenient to the unification of data message, the unification of event time, the unification of accident investigation.During the current power accident analysis requires, travelling wave ranging and traveling-wave protection to the requirement of clock accuracy up to 1us.

Traditional IRIG-B modulator-demodulator is by a long-term measurement data being added up, set up a data model, using the synthetic combined control system of multi-disc singlechip group, the time delay of compensation synchro system.But the speed of service of single-chip microcomputer is slow, and it is larger to introduce time delay in processing procedure.

The utility model content

In order to overcome the deficiencies in the prior art, the purpose of this utility model is to provide a kind of IRIG-B modulator-demodulator little, that long-time stability are good that fluctuates.

For reaching above-mentioned purpose, the utility model proposes a kind of IRIG-B modulator-demodulator based on FPGA, comprise power module, full duplex interface, based on processing module and the display module of FPGA, full duplex interface, display module, connect power module based on the processing module of FPGA, and full duplex interface, display module also connect the processing module based on FPGA.Wherein, power module is for to be converted into the required power supply of IRIG-B modulator-demodulator with input power, the full duplex interface is used for providing input signal to the processing module based on FPGA, be used for the data flow direction of control full duplex interface and finish IRIG-B code encoding and decoding based on the processing module of FPGA, display module is driven by the output based on the processing module of FPGA and shows.

In the utility model, processing module based on FPGA comprises controller, time message parsing module, IRIG-B coding module, IRIG-B decoder module and the time message coding module with UART communication module, time message parsing module, IRIG-B coding module, IRIG-B coding module and time message coding module connect respectively the UART communication module of controller, and IRIG-B coding module connect hours packet parsing module, IRIG-B decoder module connect hours message coding module.

Wherein, the UART communication module is used for going here and there and changing, for controller read/outgoing message information carries out Data Format Transform; The time message parsing module parses temporal information, provides the coded messages such as date Hour Minute Second for controller carries out the IRIG-B coding; IRIG-B code decoder module parses temporal information, provides the coded messages such as date Hour Minute Second for controller carries out the time message coding.Further, the UART communication module comprises baud rate generation module and receiver module

In the utility model, power module comprises power supply chip LM1117 and TPS55383, is input as AC85-265V, is output as 3.3V, 2.5V, 1.2V power supply.

In the utility model, the full duplex interface adopts chip MAX485 by rapid light coupling 6N137 isolation, and three full duplex mouths are arranged, and is respectively IRIG-B, 1PPS, BJT, and 1PPS, BJT are input when the IRIG-B modulator-demodulator is encoded, and IRIG-B is output; When the IRIG-B modem codec, IRIG-B is input, and 1PPS, BJT are output.

In the utility model, display module comprises chip SN74ALVC04NSR and light-emitting diode, and power supply indicator, system's run indicator, IRIG-B indicator light, 1PPS indicator light, BJT indicator light are arranged.

The beneficial effects of the utility model are: fluctuate little, long-time stability good, time precision is high and system flexibility is good.And this IRIG-B modulator-demodulator adopts standard DIN mounting means at mounting means, mounting means is flexible, expansion is convenient.

Description of drawings

Fig. 1 is the theory diagram based on the IRIG-B modulator-demodulator of FPGA of the utility model one embodiment.

Fig. 2 is the theory diagram of the full duplex interface among Fig. 1.

Fig. 3 is the theory diagram based on the processing module of FPGA among Fig. 1.

Fig. 4 is the theory diagram of the UART module among Fig. 3.

Embodiment

For above-mentioned and other objects, features and advantages of the present utility model can be become apparent, preferred embodiment cited below particularly, and cooperate accompanying drawing, be described in detail below.

As shown in Figure 1, IRIG-B modulator-demodulator based on FPGA, comprise power module 10, full duplex interface 20, based on processing module 30 and the display module 40 of FPGA, full duplex interface 20, display module 40, connect power modules 10 based on the processing module 30 of FPGA, and full duplex interface 20, display module 40 also connect the processing module 30 based on FPGA.

Wherein, power module 10 is for to be converted into the required power supply of IRIG-B modulator-demodulator with input power.In the present embodiment, power module be input as AC85-265V, formed by power supply chip LM1117 and TPS55383, be responsible for modulator-demodulator 3.3V, 2.5V., 1.2V power supply be provided.

Full duplex interface 20 is used for providing input signal to the processing module 30 based on FPGA.In the present embodiment, the full duplex interface adopts technical grade chip MAX485 by rapid light coupling 6N137 isolation.As shown in Figure 2, MAX485 is the full duplex device, and three full duplex mouths are arranged, and is respectively IRIG-B, 1PPS, BJT.When pin two, 3 is low level, be the differential signal input, Transistor-Transistor Logic level output; When pin two, 3 is high level, be the input of Transistor-Transistor Logic level signal, differential level output.1PPS, BJT are input when the IRIG-B modulator-demodulator is encoded, and IRIG-B is output; When the IRIG-B modem codec, IRIG-B is input, and 1PPS, BJT are output.

Display module 40 is driven by the output based on the processing module 30 of FPGA and shows.In the present embodiment, display module 40 is comprised of technical grade chip SN74ALVC04NSR and light-emitting diode, comprises power supply indicator, system's run indicator, IRIG-B indicator light, 1PPS indicator light, BJT indicator light.

Processing module 30 based on FPGA is the core of IRIG-B modulator-demodulator, for based on the FPGA device, mainly finishes following functions 1, control full duplex mouth gets the data flow path direction; 2, finish IRIG-B code encoding and decoding algorithm.Fig. 3 is the theory diagram based on the processing module of FPGA in the present embodiment.

Processing module based on FPGA comprises controller, time message parsing module, IRIG-B coding module, IRIG-B decoder module and the time message coding module with UART communication module, time message parsing module, IRIG-B coding module, IRIG-B coding module and time message coding module connect respectively the UART communication module of controller, and IRIG-B coding module connect hours packet parsing module, IRIG-B decoder module connect hours message coding module.

Wherein, the UART communication module is used for going here and there and changing, for controller read/outgoing message information carries out Data Format Transform; The time message parsing module parses temporal information, provides the coded messages such as date Hour Minute Second for controller carries out the IRIG-B coding; IRIG-B code decoder module parses temporal information, provides the coded messages such as date Hour Minute Second for controller carries out the time message coding.

Fig. 4 is the theory diagram of the UART module among Fig. 3, and the UART communication module comprises two modules: baud rate generation module, receiver module.

(1) in fact baud rate generation module, Baud rate generator are exactly a frequency divider, specifically realize by a counter.The design adopts the scheme of 16 times of frequency samplings, namely adopts 16 times to the clock of baud rate, and even baud rate is 9600, and then the output clock of Baud rate generator is 9600 * 16.Simultaneously, because system's master clock is 100MHz, so frequency dividing circuit is 652 to the divider ratio of system's master clock, each count cycle makes the high and low variation of output level, can obtain the clock of UART corresponding to 9600 baud rates.

(2) receiver module.Affect for fear of burr, can access correct initial signal and valid data, need to finish a simple maximum likelihood decision, its method is as follows: because the frequency of bclk signal is 16 times of baud rate, then for each data 16 sampled values can be arranged, final sampling bits value is that occurrence number surpasses 8 times level logic value.Receiver module 0 is started working from first that captures serial data, namely verifies the arrival of start bit, after having verified, begins to receive 8 bit data, and goes here and there and change, and detects subsequently position of rest, correctly then output.

It is as follows to utilize the utility model to carry out the process of IRIG-B code decoding:

Continuous two P code elements are the frame head of IBIG-B code, the judgment frame header need to be to the high level timing of B coded signal in FPGA, when the high level time of continuous two pulses reaches requiring of P code element, just can think frame head, but pass by 8ms the punctual quarter (rising edge) of this second of time.In order to make the pps pulse per second signal irigb_pulse that extracts, design a shielded signal Mask, the front 1ms that arrives at PPS opens, intercept whole P0 code element, so lock-out pulse will be Mask with the IRIG-B signal that enters " with " the result, utilize this combinational logic to realize the synchronous extraction of PPS signal.IRIG-B code per second sends once, is 100 code elements.Code element has Pr code, P code, logical one, logical zero, and wherein the high level width of Pr code and P code is 8ms, and the high level width of logical one is 5ms, and the high level width of logical zero is 2ms.Therefore we can identify code element according to the high level width difference of different code elements, to be identified complete after, data are gone here and there and are transformed, at last the binary-coded decimal time is converted into the binary system time.

It is as follows to utilize the utility model to carry out the process of IRIG-B coding:

IRIG standard code B code per second is sent out 1 time, and each 100 code elements comprise 1 reference synchronization point (rising edge of Pr pulse) and 10 index markers.Symbol width is 10ms, is that the pulse of 8ms represents index marker with the high level width, is that the pulse of 5ms represents logical one with width, is that the pulse of 2m represents logical zero with width.Therefore utilize the FPGA coding method as follows: at first to carry out binary system and can adopt look-up table to BCD(, at first preserve 0～99 binary-coded decimal table, can find corresponding transformational structure according to the address during conversion), then be parallel-serial conversion, then under pulse per second (PPS) triggers, generate clock_1ms and two control of clock_10ms clock.Next defines symbol register data_irig, and width is 10, every output time spent 1ms.So just can realize the coding output of IRIG-B code.

In sum, the beneficial effects of the utility model are: fluctuate little, long-time stability good, time precision is high and system flexibility is good.And this IRIG-B modulator-demodulator adopts standard DIN mounting means at mounting means, mounting means is flexible, expansion is convenient.

The case of implementation described in the utility model only is better case study on implementation of the present utility model, is not to limit practical range of the present utility model.Be that all equivalences of doing according to the content of the utility model claim change and modification, all should be as technology category of the present utility model.

Claims

1. the IRIG-B modulator-demodulator based on FPGA is characterized in that, comprising:

Power module, full duplex interface, based on processing module and the display module of FPGA, full duplex interface, display module, connect power module based on the processing module of FPGA, and full duplex interface, display module also connect the processing module based on FPGA;

Wherein, power module is for to be converted into the required power supply of IRIG-B modulator-demodulator with input power, the full duplex interface is used for providing input signal to the processing module based on FPGA, be used for the data flow direction of control full duplex interface and finish IRIG-B code encoding and decoding based on the processing module of FPGA, display module is driven by the output based on the processing module of FPGA and shows.

2. the IRIG-B modulator-demodulator based on FPGA according to claim 1, it is characterized in that, wherein the processing module based on FPGA comprises the controller with UART communication module, the time message parsing module, the IRIG-B coding module, IRIG-B decoder module and time message coding module, the time message parsing module, the IRIG-B coding module, IRIG-B coding module and time message coding module connect respectively the UART communication module of controller, and IRIG-B coding module connect hours packet parsing module, IRIG-B decoder module connect hours message coding module.

3. the IRIG-B modulator-demodulator based on FPGA according to claim 2 is characterized in that wherein the UART communication module comprises baud rate generation module and receiver module,

4. the IRIG-B modulator-demodulator based on FPGA according to claim 1 is characterized in that wherein power module comprises power supply chip LM1117 and TPS55383, is input as AC85-265V, is output as 3.3V, 2.5V, 1.2V power supply.

5. the IRIG-B modulator-demodulator based on FPGA according to claim 1, it is characterized in that, wherein the full duplex interface adopts chip MAX485, three full duplex mouths are arranged, be respectively IRIG-B, 1PPS, BJT, when the IRIG-B modulator-demodulator was encoded, 1PPS, BJT were input, and IRIG-B is output; When the IRIG-B modem codec, IRIG-B is input, and 1PPS, BJT are output.

6. the IRIG-B modulator-demodulator based on FPGA according to claim 1, it is characterized in that, wherein display module comprises chip SN74ALVC04NSR and light-emitting diode, and power supply indicator, system's run indicator, IRIG-B indicator light, 1PPS indicator light, BJT indicator light are arranged.