CN202748784U - 16-bit multibus circuit in 2-in-3 or 2-in-2 control system - Google Patents
16-bit multibus circuit in 2-in-3 or 2-in-2 control system Download PDFInfo
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- CN202748784U CN202748784U CN 201220260832 CN201220260832U CN202748784U CN 202748784 U CN202748784 U CN 202748784U CN 201220260832 CN201220260832 CN 201220260832 CN 201220260832 U CN201220260832 U CN 201220260832U CN 202748784 U CN202748784 U CN 202748784U
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Abstract
The utility model discloses a 16-bit multibus circuit in a 2-in-3 or 2-in-2 control system. The 16-bit multibus circuit is characterized in that the system comprises three main modules and a bus arbitration application/release circuit, wherein each main module comprises a central processing unit, a programmable logic device, a memorizer and a bus external interface, which are independent from one another; the programmable logic device in each main module is respectively and electrically connected with the central processing unit, the memorizer and the bus external interface in the main module; and the programmable logic devices in the three main modules are respectively and electrically connected with the bus arbitration application/release circuit. According to the 16-bit multibus circuit, under the status of a processor with the same level, the work efficiency and the running speed of the system can be greatly improved, the equipment loss can be reduced, the service life of equipment can be prolonged, and the transmission of error orders can be effectively avoided.
Description
Technical field
The utility model relates to the switching of multibus in the control system to be selected, and is specially a kind of 3 and gets 2 or 2 16 multibus circuit getting in 2 control system.This circuit is used for a control system, processes total line traffic control request signal by programmable logic device (PLD) and bus application/arbitration circuit that primary module carries, determines the current main equipment that works.
Background technology
Use multibus can be designed to easily multiple microprocessor system, realize distribution process, multi task process and parallel processing.It is compared with other bus, have wide application, multiple functional, wiring rationally, the advantages such as strong adaptability, can improve speed and efficient that microsystem information transmits, therefore become widely used a kind of Industry Standard Architecture in the microprocessor system design.
3 get 2 or 2, and to get 2 control system be a kind of a plurality of main equipments to be connected to bus consisting of the control system of multiprocessing configuration, but these main equipment shared bus resources.But some many main equipments control system is determined the priority of self by the corresponding identification information of judging self identification information and other main equipments, and bad adaptability lacks dirigibility.
In traditional control system, the message exchange between external unit and the central processing unit is all finished by central processing unit, has objectively reduced the work efficiency of central processing unit.In general, require the central processing unit intervention more few better during peripheral hardware work, the central processing unit intervention is fewer, and the Center Processing Unit Utilization of this equipment is just lower, and the intelligent degree of devices illustrated is just higher.The multibus standard is between central processing unit and the primary memory, between central processing unit and the external unit, be provided with respectively bus between primary memory and the external unit, thereby improved speed and efficient that microsystem information transmits.Chinese patent " supports the internal memory arbitration of multibus polymorphic type storer to realize system and method ", and (application number 200710063553.1) discloses a kind of implementation method of supporting the internal memory arbitration system of multibus polymorphic type storer.Although this scheme design is rigorous, relatively loaded down with trivial details, signal produces increase relative with the processing time, thereby the work efficiency of whole system is affected.
In addition, the shared proportion in now industry along with the raising that in the modern industry Microcomputer Calculation amount is required and MICROCOMPUTER PROCESSING, the challenge that faces is, the life-span of electronic equipment and the life-span of equipment set are complementary in must Guarantee control system, and the job stability of whole control system and reliability, so just can avoid owing to equipment is eliminated and the expired unnecessary work that produces of technology.
The utility model content
For the deficiencies in the prior art, the technical matters that the utility model quasi-solution is determined is, provide a kind of 3 to get 2 or 2 16 multibus circuit getting in 2 control system, this multibus circuit is intended to avoid in the heavy control system of task amount, owing to the break down instruction of a series of mistakes of causing of a certain primary module.The method of this setting priority is comprising the intelligent elastic framework system of at least 2 main equipments, can effectively avoid the multi-Active device conflict that occurs in the control system, in addition, a plurality of main equipments can be intercoursed information, the main equipment of low priority can utilize that the main equipment of high priority transmits directly access should be from equipment about the information of access slave and the effective information of signal, and continue to operate on it, improved device processes speed; The main equipment of high priority also can obtain the information of low priority main equipment access slave, and different main equipments is for guaranteeing from the correctness of equipment operation from the contrast of the access of equipment; A plurality of main equipments are backup mutually, strengthens reliability.
The technical solution that the utility model solve the technical problem is: design a kind of 3 and get 2 or 2 16 multibus circuit getting in 2 control system, it is characterized in that this system comprises three primary modules and a bus arbitration application/release circuit, each primary module all comprises independently central processing unit, programmable logic device (PLD), storer and bus external interface; Programmable logic device (PLD) in each primary module is electrically connected with central processing unit, storer and bus external interface in this primary module respectively; Programmable logic device (PLD) in three primary modules is electrically connected with described bus arbitration application/release circuit respectively.
Compared with prior art, multibus circuit described in the utility model is based on advantages such as the high speed of programmable logic device (PLD), high integration, flexible in programmings, designed by main equipment and carried the technical scheme that programmable logic device (PLD) is controlled the multibus arbitrating signals, adopt the parallel priority technology of multibus, and it is optimized design.The parallel priority technology has adopted a kind of fixing priority structure or has been determined the Technical Design of next main equipment by a certain other distribution mechanisms (for example list type); The utility model is introduced programmable logic device (PLD) composition bus arbitration application/release circuit that primary module carries, improved the dirigibility of control system, make priority structure jump out fixed mode, the user can be according to operating position, for intrinsic integrated circuit board characteristic, capable of regulating goes out optimum priority mode.This working method has improved work efficiency and the travelling speed of system greatly under the situation with level processor, reduce equipment loss, extension device serviceable life; In addition, during to the processor mail message, can realize that multiprocessor judges for information simultaneously, if judged result is consistent, can carry out next-step operation by bus when external unit; Judge inconsistently, then think mechanical disorder, can prevent effectively that therefore bad command from sending.
Description of drawings
Fig. 1 is that the utility model 3 is got the 2 or 2 control system part one-piece constructions planning block diagrams of getting 16 a kind of embodiment of multibus circuit in 2 control system.
Fig. 2 is that the utility model 3 is got the 2 or 2 control flow block diagrams of getting the bus arbitration application/release circuit of 16 a kind of embodiment of multibus circuit in 2 control system.
Embodiment
Below in conjunction with embodiment and accompanying drawing thereof the utility model is further described.The application's claim protection domain is not subjected to the restriction of embodiment.
3 of the utility model design is got 2 or 2 16 multibus circuit getting in 2 control system (abbreviation control system) and (is called for short circuit, referring to Fig. 1), it is characterized in that this main circuit will comprise three primary modules, i.e. primary module 1, primary module 2, primary module 3 and a bus arbitration application/release circuit 16; The structure of each primary module is identical, include independently central processing unit, storer, programmable logic device (PLD) and bus external interface, the programmable logic device (PLD) in each primary module is electrically connected with central processing unit, storer and bus external interface in this primary module respectively; Specifically, primary module 1 comprises central processing unit 4, programmable logic device (PLD) 7, storer 13 and bus external interface 10; Central processing unit 4 is electrically connected with programmable logic device (PLD) 7, and programmable logic device (PLD) 7 is electrically connected with storer 13, and programmable logic device (PLD) 7 is electrically connected with bus external interface 10; Primary module 2 comprises central processing unit 5, storer 14, programmable logic device (PLD) 8 and bus external interface 11; Central processing unit 5 is electrically connected with programmable logic device (PLD) 8, and programmable logic device (PLD) 8 is electrically connected with storer 14, and programmable logic device (PLD) 8 is electrically connected with bus external interface 11; Primary module 3 comprises central processing unit 6, storer 15, programmable logic device (PLD) 9 and bus external interface 12; Programmable logic device (PLD) 9 is electrically connected with storer 15, and programmable logic device (PLD) 9 is electrically connected with bus external interface 12.
Programmable logic device (PLD) (7,8 and 9) in described three primary modules (1,2 and 3) is electrically connected with described bus arbitration application/release circuit 16 respectively.Specifically, primary module 1 is electrically connected with bus arbitration application/release circuit 16 by programmable logic device (PLD) 7, primary module 2 is electrically connected with bus arbitration application/release circuit 16 by programmable logic device (PLD) 8, and primary module 3 is electrically connected with bus arbitration application/release circuit 16 by programmable logic device (PLD) 9.
The utility model circuit is a kind of for solving the technical scheme of sending the bad command problem after multi-fieldbus Control System breaks down, can realize that multiprocessor judges for same information simultaneously, if judged result is consistent, can carry out next-step operation; If judge inconsistently, then think mechanical disorder, thereby can effectively prevent the transmission of bad command.There are 3 primary module (primary modules 1 in the utility model circuit, primary module 2 and primary module 3), with 3 primary modules central processing unit (central processing unit 4 one to one, central processing unit 5 and central processing unit 6), with 3 primary modules programmable logic device (PLD) (programmable logic device (PLD) 7 one to one, programmable logic device (PLD) 8 and programmable logic device (PLD) 9), with 3 primary modules storer (storer 13 one to one, storer 14 and storer 15), with 3 primary modules bus external interface (bus external interface 10 one to one, bus external interface 11 and bus external interface 12), a bus arbitration application/release circuit 16 that is connected with 3 primary modules.Bus arbitration application/release circuit 16 receives the bus access request that 3 primary modules send, and by the ruling to total line traffic control request signal, determines to take the main equipment of bus.The storer of the main equipment that the main equipment of rear operation can move first by bus access, what the main equipment of first operation of utilization gathered directly accesses this from equipment about the information of access slave and the effective information of signal, and continue to operate on it, the main equipment of operation also can be by the storer of the main equipment that moves behind the bus access first, obtain the information of the main equipment access slave of rear operation, different main equipments can judge from the correctness of equipment operation for the contrast from the process of the access of equipment, realizes that with this multibus can access multi-memory and reach in the control system 3 and get 2 or 2 and get 2 concurrent processing purpose.
In the utility model circuit, based on multibus and programmable logic device (PLD), possesses the ability that connects a plurality of main equipment modules (being not limited to embodiment), consists of the multiprocessing configuration.In whole control system, at first determine the main equipment of limit priority by bus arbitration application/release circuit 16, the priority of supposing 3 primary modules is followed successively by primary module 1, primary module 2 and primary module 3 from high to low, when the priority orders of having determined primary module, highest priority device primary module 1 can first be accessed peripheral hardwares by its bus external interface 10, then 2 second of primary modules are by its bus external interface 11 access peripheral hardwares, the 3rd of primary module 3 or last is by its bus external interface 12 access peripheral hardwares.
In the utility model circuit, bus arbitration application/release circuit 16 main programmable logic device (PLD) that rely on primary module to carry are finished the flexible transformation of highest priority device.This circuit design has special-purpose software, and the concrete control flow of this software is (referring to Fig. 2): start-up routine, apply for total line traffic control? if allowed or get the Green Light, the moderator return results is 0, has namely obtained bus control right power; If go whistle or not granted, the moderator return results is 1, namely abandons bus control right power.According to mission requirements and described block diagram, those skilled in the art are not difficult to provide concrete program.
In the utility model circuit, primary module 1 corresponding programmable logic device (PLD) 7, the demand degree output bus control request signal according to 4 pairs of buses of central processing unit are occupied is linked on bus arbitration application/release circuit 16; Primary module 2 corresponding programmable logic device (PLD) 8, according to the demand degree that 5 pairs of buses of central processing unit are occupied, output bus control request signal is linked on bus arbitration application/release circuit 16; Primary module 3 corresponding programmable logic device (PLD) 9, the demand degree that occupies according to 6 pairs of buses of central processing unit, output bus control request signal is linked on bus arbitration application/release circuit 16, bus priority input signal corresponding to bus arbitration application/release circuit 16 output determined the main equipment that immediately should work with this in the programmable logic device (PLD) 9 of the programmable logic device (PLD) 8 of the programmable logic device (PLD) 7 of primary module 1 correspondence, primary module 2 correspondences and primary module 3 correspondences.
In the utility model circuit, primary module refers to have the module with CPU (central processing unit) of control bus ability, 3 primary module shared bus resources, data resource in the storer 13 on the primary module 1, the data resource in the storer 14 on the primary module 2 and the data resource in the storer 15 on the primary module 3 all are directly connected on the bus, therefore each primary module can pass through bus access some storeies wherein, and obtains the data resource in this storer.
In the utility model circuit, each storer and independent primary module are corresponding one by one, are storer 13 specifically, storer 14 and storer 15 respectively with primary module 1, primary module 2 and primary module 3 are corresponding one by one, and each primary module all can independent access storer separately.Design can alleviate the burden of shared bus like this, and the storer on each primary module is directly connected on the multibus, and by this characteristic of multibus, three primary modules can back up mutually, have improved equipment dependability.
The utility model circuit is mainly used in military field and industrial control field, supports the computer system bus of centralized Multiprocessing, is particularly suitable for the practical application of the aspects such as distributed treatment, multi-computer back-up or the multimachine of multitask be fault-tolerant.
Above embodiment only is to 3 getting 2 or 2 and get 2 concrete example application in the utility model control system, not limiting the application's claim.Every modification and non-intrinsically safe that carries out in the application's claim technical scheme is improved, all within the application's claim protection domain.
The utility model is not addressed part and is applicable to prior art.
Claims (1)
1. get 2 or 2 16 multibus circuit getting in 2 control system for one kind 3, it is characterized in that this system comprises three primary modules and a bus arbitration application/release circuit, each primary module all comprises independently central processing unit, programmable logic device (PLD), storer and bus external interface; Programmable logic device (PLD) in each primary module is electrically connected with central processing unit, storer and bus external interface in this primary module respectively; Programmable logic device (PLD) in three primary modules is electrically connected with described bus arbitration application/release circuit respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220260832 CN202748784U (en) | 2012-06-05 | 2012-06-05 | 16-bit multibus circuit in 2-in-3 or 2-in-2 control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220260832 CN202748784U (en) | 2012-06-05 | 2012-06-05 | 16-bit multibus circuit in 2-in-3 or 2-in-2 control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202748784U true CN202748784U (en) | 2013-02-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220260832 Expired - Fee Related CN202748784U (en) | 2012-06-05 | 2012-06-05 | 16-bit multibus circuit in 2-in-3 or 2-in-2 control system |
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| CN (1) | CN202748784U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102722466A (en) * | 2012-06-05 | 2012-10-10 | 天津市英贝特航天科技有限公司 | 16-bit multibus circuit in 2 in 3 or 2 in 2 control system |
| CN107884672A (en) * | 2017-10-30 | 2018-04-06 | 福建福清核电有限公司 | A kind of routine test method of nuclear power plant's reactor protection system link circuit |
-
2012
- 2012-06-05 CN CN 201220260832 patent/CN202748784U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102722466A (en) * | 2012-06-05 | 2012-10-10 | 天津市英贝特航天科技有限公司 | 16-bit multibus circuit in 2 in 3 or 2 in 2 control system |
| CN102722466B (en) * | 2012-06-05 | 2015-06-17 | 天津市英贝特航天科技有限公司 | 16-bit multibus circuit in 2 in 3 or 2 in 2 control system |
| CN107884672A (en) * | 2017-10-30 | 2018-04-06 | 福建福清核电有限公司 | A kind of routine test method of nuclear power plant's reactor protection system link circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130220 Termination date: 20170605 |