CN202495953U - Intrusion detection system based on FPGA - Google Patents

Intrusion detection system based on FPGA Download PDF

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Publication number
CN202495953U
CN202495953U CN2012200131428U CN201220013142U CN202495953U CN 202495953 U CN202495953 U CN 202495953U CN 2012200131428 U CN2012200131428 U CN 2012200131428U CN 201220013142 U CN201220013142 U CN 201220013142U CN 202495953 U CN202495953 U CN 202495953U
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pin
fpga
data
ethernet
memory
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CN2012200131428U
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李晶皎
陈勇
许哲万
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Northeastern University China
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Northeastern University China
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Abstract

The utility model discloses an intrusion detection system based on FPGA, which belongs to the technical field of network security. The intrusion detection system provided by the utility model adopts two pieces of large capacity SDRAM with the capacity of 16M*16 as a hash memory, thus the storage capacity of the system is large, and a large amount of Snort rules can be stored. Two pieces of SDRAM are combined together as a piece of memory for FPGA to access, thus the data width of SDRAM changes from16 bits to 32 bits, and the speed of system data access is doubled. Multiple capacitor filtering is carried out on the power supply of each module, so that the power supply is stable. DM9000A is employed to realize the high-speed accessing of Ethernet. The system employs common components, and the cost of the system is low.

Description

A kind of intruding detection system based on FPGA
Technical field
The utility model belongs to the network security technology field, particularly a kind of intruding detection system based on FPGA.
Background technology
Along with network security is more and more paid attention to, intruding detection system is paid close attention to by people also more and more as core technology that realizes network security and realization difficult point, and intruding detection system comprises character match and bag classification two parts.
At present, mainly adopt hardware and software approach for the character match in the invasion safety and bag classification two parts both at home and abroad.Wherein slower based on the matching algorithm processing speed of software, be difficult to satisfy the requirement of present network development.Based on the processing method that is based on FPGA more popular in the hardware.Using CAM (being Content Addressable Memory) is a kind of the most general string matching and packet classification method.CAM is a kind of special storage array; It has all data item of storing among input data and the CAM is compared simultaneously; Judge rapidly the input data whether with CAM in stored data items be complementary, and provide the characteristics of data item corresponding address and match information.Use look-up table and the control logic of lot of F PGA can be spliced into CAM, different joining methods realizes that CAM can obtain different performances and resource utilization.Discrete comparator is to use the look-up table of FPGA to realize.Owing to can realize the PARALLEL MATCHING of character string, so the matching performance of this method is better.But its resource utilization is poor, must use some special methods to reach the purpose of resource-sharing.And CAM, prices are rather stiff and capacity is little for TCAM, and power consumption is big, only is applicable to small-scale rule base.
Summary of the invention
For overcoming above-mentioned shortcoming, the utility model proposes a kind of intruding detection system based on FPGA, to reach the purpose that improves disposal ability.
The technical scheme of the utility model is achieved in that a kind of intruding detection system based on FPGA; Comprise Ethernet drive circuit, FPGA, data buffer, Hash memory, serial port drive circuit and host computer; Its annexation is: the output of Ethernet drive circuit connects the input of FPGA; The data input/output terminal of data buffer connects the first data input/output terminal of FPGA; The data input/output terminal of Hash memory connects the second data input/output terminal of FPGA, and the output of FPGA connects the input of serial port drive circuit, and the output of serial port drive circuit connects host computer;
Wherein, Described FPGA comprises: be used for the receiving network data bag Ethernet interface, be used for to the network data that receives wrap classification bag classification IP kernel (a kind of peripheral hardware), be used for to the network data that receives carry out the character match IP kernel (a kind of peripheral hardware) of character match, as the synchronous DRAM SDRAM of Hash memory and as read only memory ROM on the sheet of tree node memory, be used to store random access memory RAM on the sheet of detected invasion data, be used for network packet is deposited in Ethernet interface and two Nios II processors of twoport random access memory (dual port RAM); Reception that is used to control Ethernet data of described two Nios II processors, another is used for the transmission to host computer of invasion data that controlling packet classification IP kernel, character match IP kernel and control detection go out;
The advantage of the utility model: the big capacity SDRAM that to have adopted two capacity be 16M*16 is as the Hash memory; So the memory capacity of system is bigger; Can store a large amount of Snort rules, two SDRAM are linked together, supply the FPGA visit as a slice memory; Make the data width of 16 of SDRAM become 32, the system data access speed is doubled.Power supply to each module carries out multiple capacitor filtering, makes the power supply power supply stable; Adopt DM9000A to realize that Fast Ethernet inserts; System adopts components and parts commonly used, and system cost is lower.
Description of drawings
Fig. 1 is the intruding detection system structured flowchart of the utility model based on FPGA;
Fig. 2 is the structured flowchart of the utility model based on FPGA in the intruding detection system of FPGA;
Fig. 3 is the circuit theory diagrams of the utility model based on the intruding detection system Hash memory storage SDRAM 0 of FPGA;
Fig. 4 is the circuit theory diagrams of the utility model based on the intruding detection system Hash memory storage SDRAM 1 of FPGA;
Fig. 5 is the intruding detection system Hash memory power circuit theory diagrams of the utility model based on FPGA;
Fig. 6 is the intruding detection system Hash memory control pin circuitry schematic diagram of the utility model based on FPGA;
Fig. 7 is the intruding detection system data buffer circuit theory diagrams of the utility model based on FPGA;
Fig. 8 is the intruding detection system data buffer power circuit principle figure of the utility model based on FPGA;
Fig. 9 is the intruding detection system data buffer control pin circuitry schematic diagram of the utility model based on FPGA;
Figure 10 is the intruding detection system ethernet controller circuit theory diagrams of the utility model based on FPGA;
Figure 11 is the intruding detection system ethernet controller power circuit principle figure of the utility model based on FPGA;
Figure 12 is the intruding detection system Ethernet serial port drive circuit schematic diagram of the utility model based on FPGA;
Figure 13 is intruding detection system FPGA piece 1 circuit theory diagrams of the utility model based on FPGA;
Figure 14 is intruding detection system FPGA piece 2 circuit theory diagrams of the utility model based on FPGA;
Figure 15 is intruding detection system FPGA piece 4 circuit theory diagrams of the utility model based on FPGA;
Figure 16 is intruding detection system FPGA piece 7 circuit theory diagrams of the utility model based on FPGA;
Figure 17 is intruding detection system FPGA piece 8 circuit theory diagrams of the utility model based on FPGA.
Embodiment
Below in conjunction with accompanying drawing and embodiment the utility model is done further explain.
Fig. 1 is the system block diagram of the utility model; Comprise Ethernet drive circuit, FPGA, data buffer, Hash memory, serial port drive circuit and host computer; Wherein, the FPGA block diagram is as shown in Figure 2, and the model of said fpga chip is Cyclone II series EP2C70F896C6N; It is the controller of system, the control system operation; Used Ethernet chip for driving is DM9000A, the transmitting-receiving of its control system Ethernet data; Said data buffer is that capacity is the SSRAM chip I S61LPS51236A-200TQL of 512K*38, the intermediate data of its storage system operation; Said Hash memory is made up of the SDRAM memory of two 16M*16; Its storage is through the rule of the Snort after the Hash mapping; The operation of fpga chip control system; Hash mapping runs among the SSRAM chip I S61LPS51236A-200TQL, and two SDRAM that deposit the Hash memory in are at first shone upon with the Snort rule through hash function in system, secondly through ethernet control chip DM9000A receiving network data; Read the Snort rule from the Hash memory then and invade Data Matching, through serial ports detected invasion data are sent to host computer at last.
The FPGA cut-away view is as shown in Figure 2.FPGA generates SSRAM interface, sdram interface, serial interface, Ethernet interface through SOPC (system on the upper side able to programme), controls SSRAM, SDRAM, serial ports, ethernet communication respectively.
The Hash memory (Hash) of the utility model is realized the Hash mapping of data: deposit rule among the Snort in corresponding Hash address; Then it is deposited in the SDRAM appropriate address; Read when supplying coupling; Like Fig. 3 and shown in Figure 4; 1 pin, 14 pin, 27 pin, 3 pin, 9 pin, 43 pin, 49 pin of said two SDRAM memories as the Hash memory are all received on the SDRAM power supply 3.3V supply pin DR_VCC33 two 28 pin, 41 pin, 54 pin, 6 pin, 12 pin, 46 pin, the equal ground connection of 52 pin;
Fig. 5 is Hash memory power circuit theory diagrams; In order to make power supply stable; Reach filter effect, 3.3V power supply VCC33 pin through 9 electric capacity of resistance R 6 back parallel connection after ground connection, C1, C2 capacitance are 10u in 9 electric capacity; BC1 is 0.1u to the BC7 value, and SDRAM power supply DR_VCC33 picks out from the electric capacity parallel connected end;
Fig. 6 is Hash memory control pin circuitry schematic diagram, and control pin 38 pin of two SDRAM, 37 pin, 15 pin, 39 pin, 39 pin, 16 pin, 17 pin, 18 pin, 19 pin all are connected on the 3.3V power supply DR_VCC33 through the resistance of 4.7K;
Fig. 7 is the data buffer circuit theory diagrams; 15 pin, 41 pin, 65 pin, 91 pin, 4 pin, 11 pin, 20 pin, 27 pin, 54 pin, 61 pin, 70 pin, 77 pin as the SSRAM of data buffer are all received on the 3.3V power supply SR_VCC33 of SSRAM, and 17 pin, 40 pin, 67 pin, 90 pin, 5 pin, 10 pin, 21 pin, 26 pin, 55 pin, 60 pin, 71 pin, 76 pin are direct ground connection all;
Fig. 8 is data buffer power circuit principle figure; In order to make power supply stable; Reach filter effect, 3.3V power supply VCC33 pin through 13 electric capacity of resistance R 12 back parallel connection after ground connection, the C3 capacitance is 10u in 13 electric capacity; Electric capacity BC15 is 0.1u to the BC26 value, and SSRAM power supply SR_VCC33 picks out from the electric capacity parallel connected end;
Fig. 9 is data buffer control pin circuitry schematic diagram; The OE_n of SSRAM, CE1_n receive on the power supply SR_VCC33 through 5.1K resistance; Receive on the power supply SR_VCC33 through resistance R 18 after CE2 and resistance R 23 are parallelly connected; Receive on the power supply SR_VCC33 through resistance R 15 after CE3_n and resistance R 24 are parallelly connected; Receive on the power supply SR_VCC33 through resistance R 20 after GW_n and resistance R 25 are parallelly connected, receive on the power supply SR_VCC33 through resistance R 21 after ZZ and resistance R 26 are parallelly connected, receive on the power supply SR_VCC33 through resistance R 22 after MODE and resistance R 27 are parallelly connected;
The ethernet control module of the utility model adopts DM9000A to realize that the 10/100M Ethernet of FPGA inserts, and the designing user interface circuit is connected with DM9000A in SOPC Builder, utilizes Nios II processor to drive Ethernet interface, realizes ethernet communication; Figure 10 is the ethernet controller circuit theory diagrams; RXGND, TXGND, GND, the direct ground connection of TEST pin as the DM9000A of ethernet control chip; 42 pin, 24 pin, 30 pin are directly received on the 3.3V power supply N_VCC33 of ethernet controller; 34 pin, 37 pin are connected on the 3.3V power supply N_VCC33 through 4.7K resistance; 2 pin are received on the 2.5V power supply N_VCC25 through resistance L2, and 3 pin are received on 3 pin of chip RJ45INTLED after parallelly connected with resistance R 76, capacitor C 19, and 4 pin of DM9000A are received on 6 pin of chip RJ45INTLED after parallelly connected with resistance R 75, capacitor C 19; 7 pin of DM9000A are received on 1 pin of chip RJ45INTLED after parallelly connected with resistance R 73, capacitor C 18; 8 pin of DM9000A are received on 2 pin of chip RJ45INTLED after parallelly connected with resistance R 74, capacitor C 18,13 pin of RJ45INTLED, 14 pin, 8 pin ground connection, and 12 pin of RJ45INTLED, 9 pin are received on the 3.3V power supply N_VCC33;
Figure 11 is ethernet controller power circuit principle figure; In order to make power supply stable; Reach filter effect, 3.3V power supply VCC33 pin through 6 electric capacity of resistance R 69 back parallel connection after ground connection, the C20 capacitance is 10u in 6 electric capacity; Electric capacity BC38 is 0.1u to the BC42 value, and ethernet controller power supply N_VCC33 picks out from the electric capacity parallel connected end.
The serial port module of the utility model realizes the RS232 protocol communication through the UART IP kernel among the SOPC, sends the detected invasion data of FPGA to host computer and further handles, because the invasion data in the network are less; Do not influence overall system performance with serial ports transmission invasion data, Figure 12 be an Ethernet serial port drive circuit schematic diagram, then links to each other with 3.3V power supply VCC33 with resistance R 44 through Light-Emitting Diode LEDR as 12 pin of the ADM302 of serial ports control chip; 11 pin link to each other with 3.3V power supply VCC33 with resistance R 45 backs through Light-Emitting Diode LEDG, and 1 pin links to each other with 3 pin through 1u capacitor C 9 backs, and 4 pin link to each other with 5 pin through 1u capacitor C 10 backs; 2 pin are through capacitor C 11 ground connection; 6 pin process capacitor C, 12 ground connection, the direct ground connection of 15 pin, 16 pin are through electric capacity BC33 ground connection; 13 pin of ADM302 are received 3 pin of RS232 plug; 8 pin of ADM302 are received 7 pin of RS232 plug, and 14 pin of ADM302 are received 2 pin of RS232 plug, and 7 pin of ADM302 are received 8 pin of RS232 plug; After 10 pin of RS232 plug, the 11 pin parallel connections through electric capacity BC32 ground connection; The direct ground connection of 5 pin of RS232 plug, serial ports links to each other with computer through the RS232 plug, carries out serial port protocol communication.
Used fpga chip EP2C70F896C6N contains 8 pieces (BANK) in inside, and pin is distributed in 8 pieces.
FPGA is connected shown in figure 13 with the circuit of SDRAM0; The FAPG pin of control SDRAM0 and SDRAM1 is distributed in the piece 1; 23 pin of SDRAM0,24 pin, 25 pin, 26 pin, 29 pin, 30 pin, 31 pin, 32 pin, 33 pin, 34 pin, 22 pin, 35 pin and 36 pin are connected AA4 pin, AA5 pin, AA6 pin, AB5 pin, AB7 pin, AC4 pin, AC5 pin, AC6 pin, AD4 pin, AC7 pin, Y8 pin, AF4 pin and the AF4 pin of SDRAM0 respectively, are used for the transmission of address; 2 pin of SDRAM0,4 pin, 5 pin, 7 pin, 8 pin, 10 pin, 11 pin, 13 pin, 42 pin, 44 pin, 45 pin, 47 pin, 48 pin, 50 pin, 51 pin and 53 pin are connected AC1 pin, AC2 pin, AC3 pin, AD1 pin, AD2 pin, AD3 pin, AE1 and AE2 pin, AE3 pin, AF1 pin, AF2 pin, AF3 pin, AG2 pin, AG3 pin, AH1 pin and the AH2 pin of SDRAM0 respectively, are used for the transmission of data;
FPGA is connected shown in figure 13 with the circuit of SDRAM1; 23 pin of SDRAM1,24 pin, 25 pin, 26 pin, 29 pin, 30 pin, 31 pin, 32 pin, 33 pin, 34 pin, 22 pin, 35 pin and 36 pin are connected T5 pin, T6 pin, U4 pin, U6 pin, U7 pin, V7 pin, V8 pin, W4 pin, W7 pin, W8 pin, T4 pin, Y4 pin and the Y7 pin of SDRAM1 respectively, are used for the transmission of address; 2 pin of SDRAM1,4 pin, 5 pin, 7 pin, 8 pin, 10 pin, 11 pin, 13 pin, 42 pin, 44 pin, 45 pin, 47 pin, 48 pin, 50 pin, 51 pin and 53 pin are connected U1 pin, U2 pin, U3 pin, V2 pin, V3 pin, W1 pin, W2 pin, W3 pin, Y1 pin, Y2 pin, Y3 pin, AA1 pin, AA2 pin, AA3 pin, AB1 and the AB2 pin of SDRAM1 respectively, are used for the transmission of data;
The clock signal of control SDRAM1, the FPGA pin that external memory storage is write control are distributed in the piece 2, and 38 pin of SDRAM1,37 pin and 16 pin are connected G5 pin, L10 pin and the M9 pin of FPGA respectively, and are shown in figure 14;
FPGA is connected shown in figure 15 with the circuit of DM9000A.The FPGA pin of control DM9000A is distributed in the piece 4.19 pin of DM9000A, 18 pin, 17 pin, 14 pin, 13 pin, 12 pin, 11 pin, 10 pin, 31 pin, 29 pin, 28 pin, 27 pin, 26 pin, 25 pin, 34 pin, 32 pin, 36 pin, 35 pin, 37 pin, 40 pin are received A23 pin, C22 pin, B22 pin, A22 pin, B21 pin, A21 pin, B20 pin, A20 pin, B26 pin, A26 pin, B25 pin, A25 pin, C24 pin, B24 pin, A24 pin, B23 pin, C27 pin, B27 pin, B28 pin, A28 pin, C28 pin, the B28 pin of FPGA piece 4 respectively; FPGA communicates through above pin and DM9000A, the reception of control Ethernet data.
FPGA is connected shown in figure 15 with the circuit of serial ports control chip ADM3202.The FPGA pin of control ADM3202 is distributed in the piece 4.9 pin of ADM3202,10 pin respectively with FPGA piece 4 in F23 pin, G22 pin link to each other, FPGA communicates through above pin and ADM3202, realizes the serial communication with host computer.
FPGA is connected like Figure 13, Figure 16, shown in Figure 17 with the circuit of SSRAM.The FPGA pin of control SSRAM is distributed in piece 1, piece 7, the piece 8.89 pin of SSRAM link to each other with the AD7 pin of FPGA piece 1; 45 pin of SSRAM, 46 pin, 47 pin, 48 pin, 49 pin, 50 pin, 81 pin, 82 pin, 99 pin, 100 pin, 43 pin, 42 pin, 7 pin, 8 pin, 13 pin, 93 pin, 95 pin, 94 pin, 80 pin, 84 pin, 86 pin, 88 pin, 87 pin, 97 pin, 98 pin, 1 pin, 85 pin, 83 pin, 92 pin, 96 pin, 82 pin, 99 pin, 100 pin respectively with FPGA piece 7 in AH16 pin, AK17 pin, AJ17 pin, AH17 pin, AJ18 pin, AH18 pin, AK19 pin, AJ19 pin, AK23 pin, AJ20 pin, AK21 pin, AJ21 pin, AJ16 pin, AC21 pin, AD20 pin, AC20 pin, AJ23 pin, AK23 pin, AC18 pin, AD18 pin, AG18 pin, AF18 pin, AG19 pin, AH19 pin, AK20 pin, AG17 pin, AD16 pin, AD22 pin, AH20 pin, AC16 pin, AF20 pin, AG20 pin link to each other, 52 pin of SSRAM, 53 pin, 56 pin, 57 pin, 58 pin, 59 pin, 62 pin, 9 pin, 12 pin, 18 pin, 19 pin, 22 pin, 23 pin, 24 pin, 25 pin, 28 pin, 29 pin, 37 pin, 36 pin, 35 pin, 34 pin, 33 pin, 32 pin, 44 pin, 45 pin, 46 pin, 47 pin, 48 pin, 49 pin, 50 pin, 81 pin, 43 pin, 42 pin, 30 pin, 51 pin respectively with FPGA piece 8 in AH10 respectively with FPGA piece 7 in AJ10 pin, AK10 pin, AJ11 pin, AK11 pin, AH12 pin, AJ12 pin, AH15 pin, AJ15 pin, AK14 pin, AJ14 pin, AJ13 pin, AH13 pin, AK12 pin, AK7 pin, AJ8 pin, AK8 pin, AG8 pin, AF8 pin, AH7 pin, AG7 pin, AG6 pin, AG5 pin, AE12 pin, AG12 pin, AD13 pin, AE13 pin, AF14 pin, AG14 pin, AE15 pin, AF15 pin, AE11 pin, AF11 pin, AJ9 pin, AK9 pin link to each other.FPGA carries out data access through above pin to SSRAM.

Claims (2)

1. intruding detection system based on FPGA; It is characterized in that: comprise Ethernet drive circuit, FPGA, data buffer, Hash memory, serial port drive circuit and host computer; Its annexation is: the output of Ethernet drive circuit connects the input of FPGA; The data input/output terminal of data buffer connects the first data input/output terminal of FPGA; The data input/output terminal of Hash memory connects the second data input/output terminal of FPGA, and the output of FPGA connects the input of serial port drive circuit, and the output of serial port drive circuit connects host computer.
2. the intruding detection system based on FPGA according to claim 1; It is characterized in that: described FPGA comprises: be used for the receiving network data bag Ethernet interface, be used for to the network data that receives wrap classification bag classification IP kernel, be used for to the network data that receives carry out the character match IP kernel of character match, as the synchronous DRAM SDRAM of Hash memory and as read only memory ROM on the sheet of tree node memory, be used to store random access memory RAM on the sheet of detected invasion data, be used for network packet is deposited in Ethernet interface and two Nios II processors of twoport random access memory; Reception that is used to control Ethernet data of described two Nios II processors, another is used for the transmission to host computer of invasion data that controlling packet classification IP kernel, character match IP kernel and control detection go out.
CN2012200131428U 2012-01-12 2012-01-12 Intrusion detection system based on FPGA Expired - Fee Related CN202495953U (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102571494A (en) * 2012-01-12 2012-07-11 东北大学 Field programmable gate array-based (FPGA-based) intrusion detection system and method
CN103780460A (en) * 2014-01-15 2014-05-07 珠海市佳讯实业有限公司 System for realizing hardware filtering of TAP device through FPGA
CN107562221A (en) * 2017-08-21 2018-01-09 北京航空航天大学 PS/2 keyboard and mouse interface online experiment methods based on FPGA online experiment platforms
CN110958259A (en) * 2019-12-12 2020-04-03 浙江军盾信息科技有限公司 Detection method, device, equipment and storage medium of snort rule

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102571494A (en) * 2012-01-12 2012-07-11 东北大学 Field programmable gate array-based (FPGA-based) intrusion detection system and method
CN102571494B (en) * 2012-01-12 2014-11-05 东北大学 Field programmable gate array-based (FPGA-based) intrusion detection system and method
CN103780460A (en) * 2014-01-15 2014-05-07 珠海市佳讯实业有限公司 System for realizing hardware filtering of TAP device through FPGA
CN103780460B (en) * 2014-01-15 2017-06-30 珠海市佳讯实业有限公司 It is a kind of that the system that TAP device hardwares are filtered is realized by FPGA
CN107562221A (en) * 2017-08-21 2018-01-09 北京航空航天大学 PS/2 keyboard and mouse interface online experiment methods based on FPGA online experiment platforms
CN107562221B (en) * 2017-08-21 2019-11-15 北京航空航天大学 PS/2 keyboard and mouse interface online experiment method based on FPGA online experiment platform
CN110958259A (en) * 2019-12-12 2020-04-03 浙江军盾信息科技有限公司 Detection method, device, equipment and storage medium of snort rule

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