CN201955776U - Novel I/O (input/output) bus - Google Patents
Novel I/O (input/output) bus Download PDFInfo
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- CN201955776U CN201955776U CN201020679275XU CN201020679275U CN201955776U CN 201955776 U CN201955776 U CN 201955776U CN 201020679275X U CN201020679275X U CN 201020679275XU CN 201020679275 U CN201020679275 U CN 201020679275U CN 201955776 U CN201955776 U CN 201955776U
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Abstract
The utility model relates to a novel I/O (input/output) bus, which is characterized by comprising a host I/O bus interface circuit and a plurality of I/O template bus interface circuits. The host I/O bus interface circuit is connected with the I/O template bus interface circuits via a bus mother board, the host I/O bus interface circuit comprises a host bus driver, a decoder, a logic power source and an auxiliary power source which are respectively connected with a bus slot, each I/O template bus interface circuit comprises a template bus controller, a template bus driver, an identification detecting circuit, a current limiting circuit and a DC/DC circuit, and the template bus drivers and the identification detecting circuits are respectively connected with the template bus controllers. Bus ports, the identification detecting circuits and power circuits of the template bus interface circuits are respectively connected with a bus plug, and a parallel port used for switching values and an SPI (single program initiation) interface connected with other interface devices are provided. The novel I/O bus is simple and reliable in structure, can control a plurality of I/O templates, and has electric hot plugging and plug-and-play functions.
Description
Technical field
The utility model relates to a kind of novel I/O bus, is used for the bussing technique of automation control appliance.
Background technology
What the method for the input and output control signal of automation control appliance detection on-site signal was common has three kinds, is to use IO channel, the packaged type IO channel of using interfaces such as USB that carries respectively and uses the input-output device of outside by the communication technology.Consider factors such as actual demand, reliability and cost price, most of opertaing device uses is the method for the IO channel that carries.The IO channel quantity that carries when opertaing device normally is combined as several IO channel a template or module for the ease of making and using, more for a long time by the I/O(input and output) bus inserts automation control appliance.The I/O bus all is that each manufacturer defines voluntarily at present, and versatility is bad, nor possesses charged hot-swappable and plug and play capabilities, and the utility model has been done corresponding improvement at these shortcomings.
Summary of the invention
The purpose of this utility model provides a kind of novel I/O bus, can control a plurality of I/O plates, and is simple for structure, reliable.
The utility model adopts following scheme to realize: a kind of novel I/O bus is characterized in that: comprise the main frame I/O bus interface circuit and a plurality of I/O template bus interface circuit that connect through bus mother board; Described I/O template bus interface circuit comprises template bus controller, the template bus driver that is connected with this template bus controller respectively and identification testing circuit, current-limiting circuit and DC/DC circuit.The bus port of described template bus driver, identification testing circuit are connected with bus plug respectively with power circuit.
In the utility model one examples of implementation, described main frame I/O bus interface circuit comprises host bus driver, code translator, logic power and the accessory power supply that is connected with bus slot respectively.
In the utility model one examples of implementation, described template bus controller adopts CPLD or fpga chip, and this chip internal is provided with logical circuit, circuit, output translator, output register, input converter, output selector switch and three SPI interfaces take place ID; Described template bus controller is provided for the parallel interface and the SPI interface that is connected other device of switching value.
In the utility model one examples of implementation, be connected to current-limiting circuit in the described bus driver supply line.
In the utility model one examples of implementation, the input end of described bus is connected with pull-up resistor.
In the utility model one examples of implementation, described template bus driver adopts the 74HCT244 chip.
The utility model adopts the serial data communication with the SPI compatibility, and is simple for structure reliable, can control the I/O template of 16 configuration analog quantitys and switching value IO channel at most, and have charged hot-swappable and plug and play capabilities.Can carry out the online replacing and the repairing of integrated circuit board at any time not shutting down charged plug I/O template under the situation about not having a power failure in the use, the I/O passage on the I/O template of extracting, not influence the normal operation of opertaing device and other passage.Opertaing device can be discerned insertion, existence and the model of I/O template automatically, and link or deletion driver are guaranteed reliability of operation.For the user provides a great convenience.
Description of drawings
Fig. 1 is the utility model I/O bus general structure synoptic diagram.
Fig. 2 is the logic connection diagram of the utility model main frame I/O bus interface and bus mother matrix.
Fig. 3 is the utility model template bus interface logic connection diagram.
Fig. 4 is the utility model template bus controller inner control logic synoptic diagram.
Embodiment
Please refer to Fig. 1, this practical I/O bussing technique comprises: I/O bussing technique standard and I/O bus mother board, opertaing device main frame I/O bus interface circuit, I/O template bus interface circuit, charged hot-swappable and plug and play technique.Motherboard, slot and the bus hub of I/O bus are set on the opertaing device main frame (being designated hereinafter simply as main frame), the I/O template is fixed by slot after inserting main frame, and realizes being electrically connected by I/O template bus interface circuit, bus hub, main frame I/O bus interface circuit and main frame.The opertaing device main frame is by the access state of I/O monitoring bus I/O template, call control algolithm and finish Dynamic Recognition and diagnosis the I/O template, AutoLink or deletion corresponding driving program, control I/O template realize detecting the input and the control signal output of on-site signal.
Concrete, the utility model comprises main frame I/O bus interface circuit and a plurality of I/O template bus interface circuit that connects through bus; Described I/O template bus interface circuit comprises template bus controller, the template bus driver that is connected with this template bus controller respectively and identification testing circuit; The input end of described power circuit, identification testing circuit, template bus driver is connected with bus plug respectively.Described main frame I/O bus interface circuit comprises host bus driver, code translator, logic power and the accessory power supply that is connected with bus slot respectively.In present embodiment, described template bus controller adopts CPLD or fpga chip, and this chip internal is provided with logical circuit, circuit, output translator, output register, input converter, output selector switch and three SPI interfaces take place ID.Be connected to current-limiting circuit in the described bus driver supply line, the input end of described bus is connected with pull-up resistor, is used to prevent that the CMOS integrated circuit from producing parasitic controlled silicon effect.
Be described further below in conjunction with the formation and the principle of accompanying drawing the utility model bus.
Please refer to Fig. 2, Fig. 2 is the logic connection diagram of the utility model main frame I/O bus interface and bus mother matrix.The utility model I/O bus is made of data communication, address and total line traffic control and three parts of power supply power supply.Data communication interface comprises serial clock SCK, data line MOSI and MISO.The standard of serial clock SCK is the square wave of frequency 1MHz, is used for the timing of data communication, and frequency can make alterations as required where necessary; Data line MOSI is that the master goes out from going into, and is used for the transmission of data from main frame to the I/O template; Data line MISO is used for the transmission of data from the I/O template to main frame for going into from going out the master.SCK, MOSI and MISO are Transistor-Transistor Logic level, and it is unit that the data of MOSI and MISO transmit with the byte, and transmission is that two-way simultaneous carries out.Data communication interface and spi bus compatibility are adapted to the present situation that present most of analog to digital conversion circuit and D/A converting circuit have all adopted the SPI interface, are convenient to the design and the manufacturing of I/O template.Because the data communication of this I/O bus is directly controlled by main frame, therefore do not use the slave of SPI to select signal SS, use the circuit of SPI interface all to be set to slave mode on the I/O template.
The address signal of I/O bus has adopted 2-4 root address wire, is Transistor-Transistor Logic level.The opertaing device less for scale uses 2 address wire Addr0 and Addr1, can control 4 block I/O templates; Medium scale opertaing device uses 3 address wire Addr0, Addr1 and Addr2, can control 8 block I/O templates; Fairly large opertaing device uses 4 address wire Addr0, Addr1, Addr2 and Addr3, can control 16 block I/O templates at most.Owing to bus interface circuit driving force and bus-structured reason, should not control above 16 block I/O templates.Bus control comprises control select lines IOEN and reset line RES, is Transistor-Transistor Logic level.Control select lines IOEN low level is effective, is used for the auxiliary timing of data and control signal; Reset line RES also is that low level is effective, is used for the reset initialization of I/O template.
The power supply power pack of I/O bus provides power supply to the I/O template, and logic power is+5V, is the power supply of logic glue; Accessory power supply is that 12V is used for to the miniature DC/DC insulating power supply power supply of prime; These two groups of power supplys are essential, but do not require between them and isolate.For reaching more performance, can increase by one group ± 12V power supply, be used for the mimic channel power supply on the I/O template.Because the simulating signal on the I/O template and the other parts of opertaing device are isolated, and therefore, must isolate between ± 12V power supply and other power supply.The I/O bus interface circuit of opertaing device main frame is a part of main machine structure among Fig. 2, by bus driver, code translator, current-limiting circuit, logic power, accessory power supply and bus slot 1(1J1)～bus slot n(1Jn) form.The control of I/O bus requirements processor can also can be provided with special-purpose I/O processor by the primary processor control of opertaing device.The processor (being designated hereinafter simply as processor) of control I/O bus provides one group 3 the three-wire system communication interfaces with the SPI interface compatibility to the I/O bus interface, 4～6 GPIO use as address wire, IOEN and RES, 1 external interrupt incoming line is used to detect the TST signal that template is inserted, and all bus signals all will and be isolated by the bus driver buffering.Code translator is converted to I/O template gating signal with the input of the address of bus, and gating signal is inserted the strobe pin of each I/O template slot according to the order of sequence, so the address of I/O template is by the determining positions of slot.
As shown in Figure 3, Fig. 3 is the utility model template bus interface logic connection diagram, and I/O template bus interface circuit is made up of bus driver, template bus controller, identification testing circuit, current-limiting circuit, DC/DC circuit and bus plug.Bus driver adopts 74HCT244 or similar bus driver, and all bus signals all will and be isolated by the bus buffer buffering.The SCK of I/O template, MOSI, IOEN and MISO are controlled by CS, are driven by bus driver, and SCK, MOSI, IOEN enter the I/O template by impact damper when CS is effective, and MISO then sends into the I/O bus by impact damper; SCK is a low level when CS is invalid, and MOSI, IOEN are high level, and MISO is a high-impedance state.Gating control CS and RES are driven by bus driver for what lead directly to.In order to realize charged plug, insert current-limiting circuit in the VCC supply line of bus driver, the input end of bus side is connected to faint pull-up resistor.
Please refer to Fig. 4, Fig. 4 is the utility model template bus controller inner control logic synoptic diagram, the template bus controller has adopted CPLD or fpga chip, one end is connected with the I/O bus interface by bus driver, the other end is provided with one group of parallel input interface, one group of parallel output interface and three SPI interfaces, and these three SPI interfaces are respectively applied for and connect A/D circuit, D/A circuit, temperature sensor and the EEPROM that uses the SPI interface.The template bus controller be built-in with control logic circuit, ID take place circuit,, output translator, output register, input converter, SPI interface 1, SPI interface 2, SPI interface 3 and output selector switch.All steering logics are through writing by the JATG interface.Template bus controller control logic circuit produces the inner control logic signal according to bus control signal CS, SCK, MOSI and IOEN.Circuit takes place ID is the shift register that presets the ID input, exports the ID sign indicating number by output selector switch under the control of CLK and steering logic.Input converter also is a shift register, latchs parallel input signal under the control of CLK and steering logic, exports by output selector switch again.Output translator also is a shift register, under the control of CLK and steering logic, the parallel output signal of the series form of MOSI input is converted to parallel form, is latched in output register output.Control logic circuit also can be selected three built-in SPI interfaces according to bus control signal, controls corresponding SPI device, finishes corresponding operation.
Every block I/O template all has an output pin TST, is OC output, sends into main frame after the TST signal parallel connection of all I/O templates, as a look-at-me of host-processor.The I/O template is inserted the host bus socket back TST that powers on and is in low level at first automatically, and making has no progeny in the generation of host-processor rises to high level.Host-processor calls control algolithm and finishes Dynamic Recognition and diagnosis to the I/O template in interrupt routine, link corresponding driving program.Owing at first will read the ID of template to the operation of I/O template at every turn, when the I/O template was pulled out, the ID of template can't read, and just can delete the corresponding driving program.So just realized the plug and play of I/O template.
Generally speaking, the novel charged hot-plugging technology of this practicality divides hardware and software two parts, and the logic power pin of bus plug should guarantee that the access of logic power should have precedence over other signal than long 1 millimeter of other pin in the I/O template.All bus signals must insert by bus driver, insert current-limiting circuit in the bus driver supply line, and the input end of bus side is connected to faint pull-up resistor, prevent that the CMOS integrated circuit from producing parasitic controlled silicon effect.Plug and play software is realized charged hot-swappable function under the support of hardware.
In order to allow those skilled in the art better understand the utility model, below the I/O bus operation method is simply introduced, after opertaing device starts, the I/O template that processor resets all by the RES signal, use the I/O bus timing subsequently or as required the I/O template operated, realize required input/output task:
1.. processor is sent the template address by address wire, and code translator is I/O template gating signal CS with address translation, sends into the I/O template that needs operation by I/O template slot, makes the bus driver of this template effective, the template of gating appointment.
2.. processor sends template ID sense command by data telecommunication line, the control logic circuit that is positioned at the template bus controller produces the corresponding control logic signal according to this order, under CLK control, at first the ID value is inserted the shift register backward shift output that circuit takes place as ID, sent to the I/O bus by output selector switch and receive by processor.Correct as the ID value, processor link corresponding driving program, and send the order of SPI interface gating connects and reads configuration and control information in the EEPROM on the template.Incorrect or do not meet prevalue as the ID value, then end this operation of this template.
3.. as needs input switch amount signal, processor transmit button amount input command, the template bus controller at first will be inserted the interior shift register as input converter of template bus controller through the parallel input signal of conditioning, displacement output then sends to the I/O bus by output selector switch and is received by processor.
4.. as needs output switching value signal, the data of processor transmit button amount output command and output, the template bus controller in output translator with series form and line output be converted to parallel form, be latched in output register output again.
5.. as needs input analog amount signal, processor sends SPI interface gating and A/D control command, connect and the control A/D converter, read analog quantity numerical value by output selector switch, configuration of reading in 2. by step and control information are finished and are proofreaied and correct and conditioning again.As the needs cold junction compensation, processor also needs to connect and control the SPI interface temperature sensor that is positioned on the template, reads in the cold junction compensation temperature.
6.. as needs output analog signals, processor sends the order of SPI interface gating, connects D/A converter; Send the output data of D/A control command and D/A again.Connect and the control A/D converter, read analog quantity numerical value by output selector switch, configuration of reading in 2. by step and control information are finished and are proofreaied and correct and conditioning again.
7.. after finishing this analog quantity input of template or switching value input, need detect and confirm this template ID once more.Correct as the ID value, illustrate that shuttering work is normal in this input process, this input of this template is effectively; Unusual as the ID value, illustrate that shuttering work is undesired or be pulled out that this imports calcellation.
8.. after Form board tape was electrically interposed in bus hub, the TST pin on the template at first was in low level, and making has no progeny in the generation of processor rises to high level.Processor calls template ID read routine and finishes Dynamic Recognition and diagnosis to the I/O template in interrupt routine, link corresponding driving program realizes charged hot-swappable and plug and play.
The above only is preferred embodiment of the present utility model, and all equalizations of being done according to the utility model claim change and modify, and all should belong to covering scope of the present utility model.
Claims (7)
1. novel I/O bus is characterized in that: comprise the main frame I/O bus interface circuit and a plurality of I/O template bus interface circuit that connect through bus mother board; Described I/O template bus interface circuit comprises template bus controller, the template bus driver that is connected with this template bus controller respectively and identification testing circuit, current-limiting circuit and DC/DC circuit.The bus port of described template bus driver, identification testing circuit are connected with bus plug respectively with power circuit.
2. novel I according to claim 1/O bus is characterized in that: described main frame I/O bus interface circuit comprises host bus driver, code translator, logic power and the accessory power supply that is connected with bus slot respectively.
3. novel I according to claim 1/O bus, it is characterized in that: described template bus controller adopts CPLD or fpga chip, and this chip internal is provided with logical circuit, circuit, output translator, output register, input converter, output selector switch and SPI converting interface take place ID; Described template bus controller is provided for the parallel interface and the SPI interface that is connected other device of switching value.
4. novel I according to claim 1/O bus is characterized in that: the logic power pin of the bus plug of described I/O template should be than long 1 millimeter of other pin, is connected to current-limiting circuit in the described template bus driver supply line.
5. novel I according to claim 1/O bus is characterized in that: the input end of described bus is connected with pull-up resistor.
6. novel I according to claim 1/O bus is characterized in that: every block I/O template all is provided with the ID that template ID is provided circuit takes place.
7. novel I according to claim 1/O bus is characterized in that: described template bus driver adopts the 74HCT244 chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020679275XU CN201955776U (en) | 2010-12-24 | 2010-12-24 | Novel I/O (input/output) bus |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201020679275XU CN201955776U (en) | 2010-12-24 | 2010-12-24 | Novel I/O (input/output) bus |
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| CN201955776U true CN201955776U (en) | 2011-08-31 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102937942A (en) * | 2012-11-26 | 2013-02-20 | 中国民用航空飞行学院 | Universal interface system of flight simulator based on USB (Universal Serial Bus) |
| CN107918593A (en) * | 2017-05-16 | 2018-04-17 | 烟台市迈高机器人科技有限公司 | The expansion interface circuit and communication means of the one-to-many universal serial bus of near-end |
| CN112241383A (en) * | 2019-07-18 | 2021-01-19 | Wago管理有限责任公司 | Updating of components of a modular system |
-
2010
- 2010-12-24 CN CN201020679275XU patent/CN201955776U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102937942A (en) * | 2012-11-26 | 2013-02-20 | 中国民用航空飞行学院 | Universal interface system of flight simulator based on USB (Universal Serial Bus) |
| CN107918593A (en) * | 2017-05-16 | 2018-04-17 | 烟台市迈高机器人科技有限公司 | The expansion interface circuit and communication means of the one-to-many universal serial bus of near-end |
| CN107918593B (en) * | 2017-05-16 | 2024-05-24 | 烟台市迈高机器人科技有限公司 | Expansion interface circuit of near-end one-to-many serial bus and communication method |
| CN112241383A (en) * | 2019-07-18 | 2021-01-19 | Wago管理有限责任公司 | Updating of components of a modular system |
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| C14 | Grant of patent or utility model | ||
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| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110831 Termination date: 20131224 |