CN201910425U - LDMOS (laterally diffused metal oxide semiconductor) device suitable for high and low-voltage monolithic integration - Google Patents

Abstract

The utility model provides an LDMOS (laterally diffused metal oxide semiconductor) device suitable for high and low-voltage monolithic integration, which comprises a P-type substrate, a high-voltage N-trap drift region, a P-type multi-ring field reducing region, a field oxidation layer, a gate oxidation layer, a polysilicon gate, a polysilicon field plate, a P-type base region, an N-type drain region buffer layer, an N+ source region, an N+ drain region, a P+ contact region, a low-temperature deposition oxidation layer and aluminum metal. The LDMOS device is characterized in that three types of combined optimal structures of the P-type multi-ring field reducing region, the polysilicon and metal double-layer field plate and the N-type drain region buffer layer are arranged on the non-epitaxial monocrystal substrate, conflict between breakdown voltage and break-over resistance is effectively solved, and reliability of the device is simultaneously enhanced. The LDMOS device adopts non-epitaxial monocrystal high-voltage BCD (bipolar, CMOS (complementary metal oxide semiconductor) and DMOS (domplementary metal oxide semiconductor)) technique, omits working procedures such as layer burying, isolating, epitaxial processing and the like, reduces manufacturing cost and has higher practicality.

Description

A kind of single chip integrated LDMOS device of high-low pressure that is applicable to

Technical field

The utility model relates to a kind of high-voltage LDMOS device, belongs to technical field of integrated circuits.

Background technology

Power integrated circuit has been widely used in fields such as Switching Power Supply, motor-driven, automotive electronics, consumer electronics; it is to utilize the BCD technology can realize Bipolar, CMOS and LDMOS high-low voltage device compatibility on same chip, and the circuit that can realize including functions such as power, sensing, signal processing and protection is integrated.Wherein high-voltage LDMOS device is the key components of whole power integrated circuit, and its structural behaviour directly has influence on the function and the efficient of power integrated circuit.

The key technical problem that LDMOS exists mainly contains: the contradiction between the high pressure resistant and low on-resistance of LDMOS; The process compatible of high-voltage LDMOS and low-voltage ic; High-voltage LDMOS structure utility model designing technique.At present, mainly be at the design of a certain parameter of device or to the improvement at its a certain position both at home and abroad to the research of LDMOS, and still rare at the analysis-by-synthesis of each parameter designing of LDMOS of high-low pressure compatible technology chip.Because the performance of device is not the simple accumulation of each performance parameters, is interactional between each parameter.Therefore, press for each main structure parameters of LDMOS is carried out Combinatorial Optimization.

The utility model content

For addressing the above problem, the purpose of this utility model is to provide a kind of single chip integrated LDMOS device of high-low pressure that is applicable to.

For achieving the above object, the utility model provides technical scheme, falls place, field oxide, gate oxide, polysilicon gate, polysilicon field plate, P type base, N type drain region resilient coating, N+ source region, N+ drain region, P+ contact zone, low temperature deposition oxide layer, metallic aluminium comprising P type substrate, high pressure N trap drift region, the many rings of P type; It is characterized in that: on no epitaxy single-crystal substrate, adopt the many rings of P type to fall place, polysilicon and metal bi field plate, three kinds of Combinatorial Optimization structures of N type drain region resilient coating; Wherein the many rings of P type fall above the high pressure N trap drift region of place between leak in the source; Oxygen top, field in the high pressure N trap drift region is polysilicon and metal bi field plate, and the silicon dioxide insulator body with low temperature deposition between the field plate is isolated; N type drain region resilient coating is between high pressure N trap drift region and drain contact region.

Compare with existing LDMOS device, the utlity model has following beneficial effect: adopt the many rings of P type to fall the place, the drift region impurity concentration is doubled, make the conducting resistance drop by half, and make the device surface electric field be tending towards even, improve the puncture voltage of device, solved the contradiction between conducting resistance and the puncture voltage; Adopt polysilicon and metal bi field plate to reduce the surface field of device, increased the withstand voltage of device; Between high pressure N trap drift region and drain contact region, inject N type drain region resilient coating, solved the concentration gradient problem between high pressure N trap drift region and the drain contact region, avoid at device drain region generation breakdown problem.

Description of drawings

Fig. 1 is applicable to the single chip integrated LDMOS device architecture of high-low pressure figure.

Embodiment

See also shown in the Figure of description 1, the utility model is a kind of single chip integrated LDMOS device of high-low pressure that is applicable to, its structure comprises that place 3, field oxide 4, gate oxide 5, polysilicon gate 6A, polysilicon field plate 6B, P type base 7, N type drain region resilient coating 8, N+ source region 9A, N+ drain region 9B, P+ contact zone 10, low temperature deposition oxide layer 11, metallic aluminium 12 fall in P type substrate 1, high pressure N trap drift region 2, the many rings of P type.

On P type substrate 1, inject high pressure N trap drift region 2, above N trap drift region 2, inject the many rings of P type and fall place 3, form field oxide 4 and gate oxide 5 by oxidation, deposit polysilicon gate 6A and polysilicon field plate 6B on gate oxide, P type base 7 is injected in the device source region, in P type base 7, inject N+ source region 9A and P+ contact zone 10 simultaneously, N type resilient coating 8 and N+ drain region 9B are injected in the device drain region, device by contact hole by metallic aluminium 12 respectively with N+ source electrode 9A, the N+ 9B that drains, polysilicon gate 6A and polysilicon field plate 6B draw as line, metallic aluminium 12 is again as the metal field plate simultaneously, form polysilicon and metal bi field plate with polysilicon field plate 6B and overlapping part polysilicon gate 6A, isolate by low temperature deposition oxide layer 11 between the field plate.

Above embodiment only is preferred embodiment of the present utility model; not in order to limit protection range of the present utility model; all any modifications of on technological thought of the present utility model and technical scheme basis, being made, be equal to replacement, improvement etc., all within protection range of the present utility model.

Claims (1)

1. one kind is applicable to the single chip integrated LDMOS device of high-low pressure, it is characterized in that: adopt the many rings of P type to fall place, polysilicon and metal bi field plate, three kinds of Combinatorial Optimization structures of N type drain region resilient coating on no epitaxy single-crystal substrate; Wherein the many rings of P type fall above the high pressure N trap drift region of place between leak in the source; Polysilicon and metal bi field plate are positioned at the oxygen top, field of drift region, and the silicon dioxide insulator body with low temperature deposition between the double-deck field plate is isolated; N type drain region resilient coating is between high pressure N trap drift region and drain contact region.

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