CN201504095U

CN201504095U - Electrostatic discharge protection circuit of voltage fluctuation sensitive-class power signal line

Info

Publication number: CN201504095U
Application number: CN2009202046201U
Authority: CN
Inventors: 李琳; 颜再寒
Original assignee: Shenzhen ZTE Mobile Telecom Co Ltd
Current assignee: Shenzhen ZTE Mobile Telecom Co Ltd
Priority date: 2009-09-11
Filing date: 2009-09-11
Publication date: 2010-06-09
Anticipated expiration: 2019-09-11

Abstract

The utility model relates to an electrostatic discharge protection circuit of a voltage fluctuation sensitive-class power signal line. The circuit at least comprises three parts: A, B and C, wherein for the A, a bypass piezoresistor or a TVS is additionally arranged at the position at which the electrostatic is located on a power supply or a super-low-velocity signal line; for the B, a capacitance with the equivalent capacity being over muF magnitude is connected beside the piezoresistor or the TVS in parallel; and for the C, an electrostatic attenuation component is connected on the signal line in series. Therefore, due to the arrangement of the piezoresistor or the TVS and the capacitance, most electrostatic can be quickly discharged; meanwhile, the circuit has the action of voltage stabilization, and can inhibit the electrostatic energy from entering a chip and enhance the antistatic property.

Description

A kind of ESD protection circuit of the class power supply signal line to the voltage fluctuation sensitivity

Technical field

The utility model relates to the end product field of similar mobile phone, relates in particular to the ESD protection circuit of cellular phone power supplies or utmost point low speed signal line.

Background technology

Static is a kind of natural phenomena that people are familiar with very much.Static discharge ESD (Electro-StaticDischarge) causes the dysfunction even the parts damages of electronic product and equipment easily.Modem semi-conductor devices, resemble similar cell phone platform especially, function is more and more complete, and volume is but more and more littler, and operating voltage is more and more lower, caused semiconductor device to external world the electromagnetic disturbance sensitivity also improve greatly.Simultaneously, the overall volume of the end product of similar mobile phone is variation and small and exquisite both, and the environment that the user uses is various.In design, structure and circuit design are improper as fruit product, just cause unusual, the deadlock of machine works easily because of ESD, even damage and cause other safety problem.Often be connected to as above press key lamp, the combination hub etc. for the power supply on the mobile phone, holding wire, and these devices often may expose, and cause static to enter easily.

For the protection of the static discharge of power supply signal line, common way is to add pressure-sensitive resistance in the place that static enters or TVS is protected.Piezo-resistance or TVS can bleed off most static fast, but they are more weak for antistatic effect, especially the influence of voltage fluctuation can't eliminate, big slightly voltage fluctuation will cause the unusual power supply of machine works, utmost point low speed signal line, increases piezo-resistance or TVS separately and can not stablize, solve reliably this class problem.

The utility model content

For overcome for antistatic effect more weak, to the power supply or the utmost point low speed signal line of voltage fluctuation sensitivity, increase the insurmountable problem of piezo-resistance or TVS separately, the utility model provides a kind of low cost, antistatic circuit method for designing that reliability is high.The influence that this method can avoid voltage fluctuation to cause, strongly fragrant system electrostatic energy enters chip, strengthens antistatic effect.

Therefore, the utility model is achieved in that

A kind of ESD protection circuit of the class power supply signal line to the voltage fluctuation sensitivity, it comprises following part A, B, C, three parts at least:

A, on power supply or utmost point low speed signal line (below we abbreviate power supply or utmost point low speed signal line as holding wire), add a bypass piezo-resistance or TVS in the place that static enters;

B, equivalent capacity in parallel is the electric capacity more than the uF magnitude on the next door of piezo-resistance or TVS;

C, the electrostatic attenuation device of on holding wire, connecting.

Pass through the setting of piezo-resistance or TVS, electric capacity like this, can bleed off most static fast, have the effect of voltage stabilizing again simultaneously, and can enter chip by strongly fragrant system electrostatic energy, strengthen antistatic effect.

Described ESD protection circuit, it can also comprise the D part:

D, near one or more electric capacity local in parallel of chip pin, this D portion has pressure stabilization function, prevents to enter chip signal and fluctuates excessive.

The electric capacity of described B part is to be connected in parallel on the input that static may enter, this electric capacity is more than one or one, and generally, the above electric capacity of uF magnitude just can be dealt with problems, at some in particular cases, can adopt the mode that increases electric capacity to strengthen pressure stabilization function.

The electrostatic attenuation device of described series connection has one at least, and the electrostatic attenuation device is any one of magnetic bead, inductance or resistance.

Therefore, if reach good elimination static and reactance voltage fluctuation, the ESD protection circuit on power supply described in the utility model or the utmost point low speed signal line may further comprise the steps:

The first step: at the place that static an enters piezo-resistance in parallel or TVS.

Second step: equivalent capacity in parallel is the uF magnitude or the electric capacity of Da Rong value more on the next door of piezo-resistance or TVS.

The 3rd step: series connection electrostatic attenuation device on the holding wire, such as magnetic bead, inductance or resistance.

The 4th step: holding wire enters the chip pin shunt capacitance.

Beneficial effect: adopt circuit described in the utility model, add in original place that enters at static on the basis of a bypass piezo-resistance or TVS equivalent capacity and electrostatic attenuation device are set again, increased the stability and the antistatic effect of voltage.For antistatic effect more weak, to the electrostatic protection ability of the power supply of voltage fluctuation sensitivity or utmost point low speed signal line compared with prior art, improve the stability and the antistatic effect of circuit widely.

Description of drawings

Accompanying drawing Fig. 1 is seen in principle method of attachment about the utility model circuit.

Fig. 1 is the circuit diagram of the utility model embodiment.

Embodiment

Below in conjunction with accompanying drawing, enforcement of the present utility model is elaborated.

Fig. 1 is described, for realizing the simplest circuit design mode of the utility model, specifically, be exactly at power supply or utmost point low speed signal line (VCC/LOW_SPEED_SIGNAL, be called for short holding wire) piezo-resistance at first in parallel or TVS (RV2), while equivalent capacity in parallel (C1), equivalent capacity are the above electric capacity of uF magnitude, the electrostatic attenuation device (L1) of connecting again is then near chip pin equivalent capacity in parallel again (C2).

Specifically, the ESD protection circuit embodiment on power supply described in the utility model or the utmost point low speed signal line comprises the steps:

The first step: at a piezo-resistance local in parallel or TVS that static enters, the ground of piezo-resistance or TVS will well be communicated with main ground.

Second step: uF magnitude in parallel or the bigger equivalent capacity of appearance value on the next door of piezo-resistance or TVS, and also the line thick line of trying one's best is connected with piezo-resistance or TVS.The ground of electric capacity will well be communicated with main ground.

The 3rd step: the electrostatic attenuation device position of connecting on the holding wire can be put according to the layout needs.

The 4th step: holding wire enters the chip pin shunt capacitance, and the two ends of electric capacity well are communicated with the power supply of chip and ground.

Adopt circuit described in the utility model, the protection antistatic effect more weak, to the ability of the power supply of voltage pulsation sensitivity or utmost point low speed signal line compared with prior art, improve widely the antistatic effect of circuit.

Claims

1. ESD protection circuit to the class power supply signal line of voltage fluctuation sensitivity is characterized in that comprising at least following part A, B, C, three parts:

A, on power supply or utmost point low speed signal line, add a bypass piezo-resistance or TVS in the place that static enters;

C, the electrostatic attenuation device of on power supply or utmost point low speed signal line, connecting.

2. the ESD protection circuit of the class power supply signal line to the voltage fluctuation sensitivity as claimed in claim 1 is characterized in that described ESD protection circuit, and it can also comprise the D part:

D, near one or more electric capacity local in parallel of chip pin.

3. the ESD protection circuit of the class power supply signal line to the voltage fluctuation sensitivity as claimed in claim 1 is characterized in that the electric capacity of described B part is the input that is connected in parallel on static, and this electric capacity is more than one or one.

4. the ESD protection circuit of the class power supply signal line to the voltage fluctuation sensitivity as claimed in claim 1 is characterized in that the electrostatic attenuation device of described series connection having one at least, and the electrostatic attenuation device is any one of magnetic bead, inductance or resistance.