CN201497947U - Power management circuit with embedded chip - Google Patents
Power management circuit with embedded chip Download PDFInfo
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- CN201497947U CN201497947U CN2009202081084U CN200920208108U CN201497947U CN 201497947 U CN201497947 U CN 201497947U CN 2009202081084 U CN2009202081084 U CN 2009202081084U CN 200920208108 U CN200920208108 U CN 200920208108U CN 201497947 U CN201497947 U CN 201497947U
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- cpld
- cpu
- effect transistor
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Abstract
The utility model relates to a power management circuit with an embedded chip. The utility model is characterized in that the circuit comprises a CPLD chip; the CPLD chip is connected with a CPU (computer processing unit); the input terminal of the CPLD chip is connected with a CPLD power supply chip through a switching circuit; the switching circuit is connected with a power supply keystroke; the power supply keystroke is also connected with the CPU; and one output terminal of the CPLD chip is connected with a CPU power supply chip. The utility model has the advantages that the structure is simple; software shutdown and battery management can be realized; and current leakage during shutdown is very small.
Description
Technical field:
The utility model relates to electronic applications, specifically a kind of electric power management circuit of embedded chip.
Background technology:
A lot of embedded chips do not have power management capabilities, can only realize the function of switching on and shutting down by battery main switch.There are several shortcomings in this mode: if having very high possibility to damage storer memory being carried out write operation during shutdown; Support that if desired powered battery standby current when shutdown is bigger.
Summary of the invention:
The purpose of this utility model is to provide a kind of electric power management circuit of embedded chip, can realize standby, battery charging and discharging, the function of power failure protection of equipment.
To achieve these goals, the technical solution of the utility model is: a kind of electric power management circuit of embedded chip, it is characterized in that this circuit comprises the CPLD chip, the CPLD chip is connected with CPU, the input end of CPLD chip is connected with the CPLD power supply chip by on-off circuit, on-off circuit is connected with power button, and this power button also is connected with CPU, and an output terminal of CPLD chip is connected with the cpu power chip.
When needs are started shooting, press power button, on-off circuit is connected, and after the input end of CPLD chip detected signal, output signal made the cpu power chip operation, and the cpu power chip is opened total system.When needs shut down, press power button once more, after CPU detects push button signalling, then enter shutdown programm, after can safety shutdown, CPU outputs signal to the CPLD chip, and the CPLD chip signal output is given the cpu power chip, and system power supply is closed.Advantage of the present utility model is simple in structure, can realize software shutdown, battery management and when shutdown leakage current very little.
Description of drawings:
Fig. 1 is the circuit diagram of the utility model one embodiment
Embodiment:
The utility model will be further described below in conjunction with drawings and Examples.
A kind of electric power management circuit of embedded chip, it is characterized in that this circuit comprises the CPLD chip, the CPLD chip is connected with CPU, the input end of CPLD chip is connected with the CPLD power supply chip by on-off circuit, on-off circuit is connected with power button, this power button also is connected with CPU, and an output terminal of CPLD chip is connected with the cpu power chip.Wherein on-off circuit comprises field effect transistor Q1, the grid of field effect transistor Q1 is connected with the positive pole of the first diode D1, the negative pole of the first diode D1 is connected with an end of power button, the other end ground connection of power button, the negative pole of diode D1 also is connected with the first input end of CPLD chip, the source electrode of field effect transistor Q1 is connected with anode VBAT, the drain electrode of field effect transistor Q1 is connected with the CPLD power supply chip, the source electrode of field effect transistor Q1 also is connected with the negative pole of the second diode D2, the drain electrode of field effect transistor Q1 also is connected with the positive pole of the second diode D2, be connected with resistance between the grid of field effect transistor Q1 and the source electrode, the grid of field effect transistor Q1 also is connected with second input end of CPLD chip.According to an embodiment of the present utility model, the model of CPLD chip is the EPM240 of altera corp.The model of CPU is the PXA255 of Marvell company, and the model of CPLD power supply chip is the RT9193 of Richtek company.The model of cpu power chip is the RT8011 of Richtek company.
According to this embodiment, specifically describe principle of work of the present utility model below.
VBAT is an anode, by charging chip battery is charged by (battery less than time) when external power source is arranged, and the charging voltage of external power source substitutes battery and powers to total system simultaneously.Directly power by battery during no external power source to total system.
When power button is not pressed, the field effect transistor pipe Q1 that CPLD is other is because grid is pulled to cell voltage, therefore be in off state, cut off the power supply to the power supply chip of CPLD power supply, other power supply chips enables because CPLD does not work and is in closed condition simultaneously.This moment, the leakage current of total system was only caused by pull-up resistor, almost can ignore, so battery can keep long standby.
After power button was pressed, the grid of metal-oxide-semiconductor Q1 was pulled to ground level, and this moment, metal-oxide-semiconductor was opened, and power supply chip begins the power supply to CPLD, and CPLD starts working.CPLD drags down the SHDN_CPLD signal after starting, and keeps the conducting state of metal-oxide-semiconductor, even power button discharges like this, because the effect of the first diode D1, CPLD can oneself guarantee that also power supply chip continues power supply.CPLD draws high the SHDN_MISC signal then, enables cpu power, opens total system.
Press power button once more,, then enter shutdown programm, stop the operation of storer if CPU can shut down after detecting button at this moment.After can safety shutdown, CPU issues CPLD with POWER OFF signal, and CPLD drags down SHDN_MISC after detecting POWER OFF signal, closes CPU POWER, draws high SHDN_CPLD again, with self power remove.
Claims (2)
1. the electric power management circuit of an embedded chip, it is characterized in that this circuit comprises the CPLD chip, the CPLD chip is connected with CPU, the input end of CPLD chip is connected with the CPLD power supply chip by on-off circuit, on-off circuit is connected with power button, this power button also is connected with CPU, and an output terminal of CPLD chip is connected with the cpu power chip.
2. electric power management circuit according to claim 1, it is characterized in that: on-off circuit comprises field effect transistor, the grid of field effect transistor is connected with the positive pole of first diode, the negative pole of first diode is connected with an end of power button, the other end ground connection of power button, the negative pole of diode also is connected with the first input end of CPLD chip, the source electrode of field effect transistor is connected with anode, the drain electrode of field effect transistor is connected with the CPLD power supply chip, the source electrode of field effect transistor also is connected with the negative pole of second diode, the drain electrode of field effect transistor also is connected with the positive pole of second diode, be connected with resistance between the grid of field effect transistor and the source electrode, the grid of field effect transistor also is connected with second input end of CPLD chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202081084U CN201497947U (en) | 2009-08-19 | 2009-08-19 | Power management circuit with embedded chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202081084U CN201497947U (en) | 2009-08-19 | 2009-08-19 | Power management circuit with embedded chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201497947U true CN201497947U (en) | 2010-06-02 |
Family
ID=42441150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009202081084U Expired - Lifetime CN201497947U (en) | 2009-08-19 | 2009-08-19 | Power management circuit with embedded chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201497947U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104679210A (en) * | 2015-03-17 | 2015-06-03 | 浪潮集团有限公司 | Device and method for powering on computer on basis of CPLD controller |
| US10485706B2 (en) | 2016-08-29 | 2019-11-26 | 3M Innovative Properties Company | Electronic hearing protector with switchable electrical contacts |
-
2009
- 2009-08-19 CN CN2009202081084U patent/CN201497947U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104679210A (en) * | 2015-03-17 | 2015-06-03 | 浪潮集团有限公司 | Device and method for powering on computer on basis of CPLD controller |
| US10485706B2 (en) | 2016-08-29 | 2019-11-26 | 3M Innovative Properties Company | Electronic hearing protector with switchable electrical contacts |
| US10987251B2 (en) | 2016-08-29 | 2021-04-27 | 3M Innovative Properties Company | Electronic hearing protector with switchable electrical contacts |
| US11337861B2 (en) | 2016-08-29 | 2022-05-24 | 3M Innovative Properties Company | Electronic hearing protector with switchable electrical contacts |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP03 | Change of name, title or address |
Address after: Bi Sheng Road, Zhangjiang hi tech park Shanghai city 201204 289 Lane 2, Room 201 Patentee after: Shanghai Style Information Technology Co.,Ltd. Address before: 201203, No. 6, building 4, No. 3000 East Main Road, Shanghai, Pudong New Area Patentee before: Shanghai Fengge Information Technology Co., Ltd. |
|
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI WIBOX SCIENCE + TECHNOLOGY DEVELOPMENT CO Free format text: FORMER OWNER: SHANGHAI FIGURE IT CO., LTD Effective date: 20150716 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20150716 Address after: Bi Sheng Lu Pudong New Area Zhangjiang hi tech park Shanghai 201204 Lane 289 Building No. 2 Patentee after: SHANGHAI WIBOX SCIENCE & TECHNOLOGY DEVELOPMENT CO., LTD. Address before: Bi Sheng Road, Zhangjiang hi tech park Shanghai city 201204 289 Lane 2, Room 201 Patentee before: Shanghai Style Information Technology Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: No.2 Building, 289 Lane, Bisheng Road, Zhangjiang High-tech Park, Pudong New Area, Shanghai, 20104 Patentee after: Shanghai Baibei Science and Technology Development Co., Ltd. Address before: No.2 Building, 289 Lane, Bisheng Road, Zhangjiang High-tech Park, Pudong New Area, Shanghai, 20104 Patentee before: SHANGHAI WIBOX SCIENCE & TECHNOLOGY DEVELOPMENT CO., LTD. |
|
| CP01 | Change in the name or title of a patent holder | ||
| CX01 | Expiry of patent term |
Granted publication date: 20100602 |
|
| CX01 | Expiry of patent term |