CN201270504Y - Frequency synthesizer - Google Patents
Frequency synthesizer Download PDFInfo
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- CN201270504Y CN201270504Y CNU2008200586465U CN200820058646U CN201270504Y CN 201270504 Y CN201270504 Y CN 201270504Y CN U2008200586465 U CNU2008200586465 U CN U2008200586465U CN 200820058646 U CN200820058646 U CN 200820058646U CN 201270504 Y CN201270504 Y CN 201270504Y
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Abstract
The utility model discloses a frequency synthesizer comprising a frequency-locking ring which operates based on the reference frequency from a crystal oscillator, a frequency correcting unit and an interpolating logical unit, wherein the frequency correcting unit generates a digital frequency correcting control word based on a first parameter and a second parameter, and the first parameter is the combination of an automatic frequency correction word and a fixed frequency control word. The interpolating logical unit is used for generating the second parameter which represents the temperature change compensation, wherein when the first parameter is a constant, and the frequency-locking ring generates fixed clock signals or generates frequency modulating signals when the first parameter is a binary sequence which represents the frequency change of modulating signals. The synthesizer can realize the temperature compensation to the frequency excursion of the reference clock through controlling the frequency correcting control word.
Description
Technical field
The utility model relates to electronic circuit design field, particularly the compensation technique of the temperature frequency of frequency synthesizer drift.
Technical background
Can both be normally or synchronous working in order to ensure all electronic devices, it is very important that accurate clock signal is provided in design of electronic circuits.Usually, described clock signal is produced by crystal oscillator (crystaloscillator), and wherein said crystal oscillator is to utilize the mechanical resonant of the oscillating crystal of piezoelectric to produce the electronic circuit of the certain frequency signal of telecommunication.This frequency can be used for timing (such as quartz watch) usually, also can be used to digital integrated circuit that clock signal is provided, and can also be used for stablizing the frequency of wireless launcher/receiver.A reason that causes clock signal to be different from design is temperature, and it may influence the running of piezoelectric and crystal oscillator.Along with variation of temperature, the frequency of crystal oscillator output can also can change thereupon.In fact, electronic equipment may be used to such as portable computer, mobile phone and electronic instrument therefore guarantee that these electronic equipments can both normally errorless work be very important under all temps environment in the environment of all temps variation.
Many modern communications equipments need high accuracy, stable frequency to increase the sensitivity of radio transceiver in it such as GPS and gsm system and reduce acquisition time.In frequency synthesizer (frequencysynthesizer),
The output frequency of crystal oscillator multiply by known coefficient just can obtain to expect channel frequency.Usually, the scope of the output frequency of crystal oscillator is the number megahertz, and the scope of channel frequency is a Gigahertz.Yet the output of crystal oscillator can be drifted about along with life-span and variation of temperature again and again, and crystal oscillator does not provide the inhibition mechanism that crystal frequency changes with environment temperature yet.Because harsh demand, it is impossible using low-cost independent crystal oscillator in the cellular system from the frequency tuning support of base station not.
The frequency source of wireless telecommunications system or mobile phone includes digitally controlled crystal oscillator (digitallycontrolled crystal oscillator) or temperature compensating crystal oscillator (temperature-compensated crystal oscillator).Yet the digitally controlled crystal oscillator circuit need be introduced capacitor array and carry out frequency correction in crystal oscillator.Like this, use digitally controlled crystal oscillator just to become very expensive, especially for the digitally controlled crystal oscillator of deep-submicron COMS technology.In addition, cause frequency hopping effect (frequency beating effects) possibly, thereby be difficult to satisfy the requirement of output frequency stability by the output frequency of the switching of a large amount of electric capacity in the digitally controlled crystal oscillator being adjusted crystal oscillator.
In existing temperature compensating crystal oscillator (temperature-compensated crystaloscillator), self-operated thermostatic controller generates correction voltage to guarantee that oscillator frequency is constant.Such voltage controlled temperature compensated crystal oscillator has a temperature sensor according to the proportional generation linear voltage of temperature.
The output of three grades of linear function voltage generators and temperature sensor offers VCXO, described VCXO and then can carry out temperature-compensating according to the temperature frequency characteristic of use crystal.
Yet such voltage controlled temperature compensated crystal oscillator at first needs a high-quality crystal to satisfy described three grades of linear compensation needs, and so high-quality crystal is very expensive, especially undersized crystal.Owing to limited the maximum output frequency of crystal oscillator, therefore also be difficult to guarantee high frequency stability and accuracy.In addition, owing to be difficult to accurately generate microvolt level aanalogvoltage, the change of the very difficult control of described voltage controlled temperature compensated crystal oscillator small frequency (such as, less than 1.0 hertz).
Therefore,
Waiting to propose a kind of low cost, low noise, high-precision solution generates and has wide frequency range and through the frequency of temperature-compensating.
The utility model content
In view of this, the purpose of this utility model is to provide low-cost, high-precision frequency synthesizer, and it can carry out temperature-compensating to its output frequency.
In order to achieve the above object, the utility model provides a kind of frequency synthesizer, FLL, frequency correction unit and the interpolation logical block moved for the basis from the reference frequency of crystal oscillation device since it comprises.Described frequency correction unit serves as that the basis generates the digitally correcting frequency control word with first parameter and second parameter, and described first parameter is the combination of automatic frequency correction word and fixed frequency control word.Described interpolation logical block is used to generate second parameter of expression variations in temperature compensation.Wherein described FLL generates the fixed clock signal or when first parameter described FLL generated frequency modulation signal during for the binary sequence of the frequency shift of representing modulation signal when first parameter is constant.
Further, f
OUTRepresent described clock signal, f
RThe expression reference frequency, FCW_new represents described digitally correcting frequency control word, and following formula is then arranged:
f
OUT＝K*FCW_new*f
R，
Wherein K represents proportionality coefficient K.
Further, make clock signal reach expected frequency by the resize ratio COEFFICIENT K.
Further again, be not subjected to influence of temperature change and keep stable to such an extent as to described digitally correcting frequency control word compensates described clock signal to the frequency drift of reference frequency.
Further again, described fixed frequency control word is to be provided by the outside, and it is the binary sequence of expression clock signal expected frequency.
Still further, determine described automatic frequency correction word according to accurate frequency source.
Further again, described accurate frequency source is the clocking information of wireless base station emission.
Further, it further comprises: digital temperature sensor is used to respond to the environment temperature of the temperature that comprises described frequency synthesizer place integrated circuit; The decode logic unit is connected with digital temperature sensor, and reception and decoding are from the digital measurement of temperature value of digital temperature sensor; Look-up table is used for the corresponding relation of storing frequencies correction signal and temperature, and drives the interpolation logical block and adjust second parameter.
Further, described FLL comprises: the digit phase accumulator, receive the digitally correcting frequency control word from described frequency correction unit, the frequency accuracy of wherein said clock signal or frequency modulated signal is by the word length of digit phase accumulator and reference frequency decision; The numerical frequency comparator, the output of comparative figures phase accumulator and comprise frequency divider and the output of the feedback loop of frequency digital quantizer; The digital loop filter is connected with the numerical frequency comparator, is used for the error signal of numerical frequency comparator output is carried out filtering, and wherein said digital loop filter provides the control of loop bandwidth and lock adjustment time; Digital analog converter is connected with the digital loop filter, and the output that receives the digital loop filter is to generate analog signal; Low pass filter is used for described analog signal is carried out filtering, and described analog signal has further been controlled the input voltage of voltage controlled oscillator, and wherein described FLL enters lock-out state when the output of voltage controlled oscillator is locked in expected frequency.
Further, described FLL further comprises:
Connect the frequency digital quantizer, be used to utilize reference frequency
The output signal of voltage controlled oscillator
Switch through and change the numerical frequency data flow into.
Further, described FLL further comprises:
Connect the frequency digital quantizer, thereby be used to utilize the output signal of voltage controlled oscillator that reference frequency is sampled
Connect
The output signal of voltage controlled oscillator is converted to the numerical frequency data flow.
Further again, described FLL further comprises: be used for the output of voltage controlled oscillator is carried out frequency division to obtain the frequency divider of described clock signal.
Further, described FLL comprises: the digit phase accumulator, receive the digitally correcting frequency control word and generate the reference frequency data flow from described frequency correction unit, the frequency accuracy of wherein said clock signal or frequency modulated signal is by the word length of digit phase accumulator and reference frequency decision; The numerical frequency comparator, the output of comparative figures phase accumulator and comprise frequency divider and the output of the feedback loop of frequency digital quantizer; The digital loop filter is connected with the numerical frequency comparator, is used for the error signal of numerical frequency comparator output is carried out filtering, and wherein said digital loop filter provides the control of loop bandwidth and lock adjustment time; The digital controlled oscillator gain control circuit, be output as the digital controlled signal that the basis generates the weighting switch binary system capacitor array be used to control digital controlled oscillator with the digital loop filter, wherein said digital controlled oscillator gain control unit is used to eliminate the influence to phase place and frequency of technology, voltage and temperature; And numerically-controlled oscillator, generating wireless frequency signal, described wireless frequency signal is converted into intermediate-freuqncy signal, and the frequency digital quantizer is further
Described intermediate-freuqncy signal converts the numerical frequency data flow to, and wherein described FLL enters lock-out state when the numerical frequency data flow is locked in the reference frequency data flow.
Further again, weighting switch binary system capacitor array can switch to high capacitance pattern or low capacitive according to the control of digital controlled signal.
Further, by changing the high-resolution that the figure place of using delta-sigma modulated digital control signal can obtain clock signal or frequency modulated signal.
So compared with prior art, in the technical scheme that the utility model proposes,, realize temperature-compensating to the frequency drift of reference clock by control to the frequency correction control signal.
Description of drawings
Fig. 1 is the functional-block diagram of the temperature-compensating frequency synthesizer in the utility model, and wherein said temperature-compensating frequency synthesizer comprises numerical control FLL (Digitally-Controlled Frequency-LookedLoop) and crystal oscillator;
Fig. 2 is the not compensation temperature frequency characteristic curve diagram of crystal oscillator;
Fig. 3 is the point-to-point Tc compensated curve figure corresponding with the not compensation temperature frequency characteristic of crystal oscillator;
Fig. 4 is the functional-block diagram of the FLL in the utility model, and wherein said FLL is at reference frequency f
RThe basis on use numerical frequency control word FCW (digital frequency control word) that the desired output frequency f is set
OUT
Fig. 5 is the functional-block diagram of another framework of the FLL in the utility model, and wherein said FLL comprises
Connect frequency/digital quantizer (frequency-to-digital converter);
Fig. 6 is the functional-block diagram of the FLL in the utility model, and wherein said FLL utilizes digital controlled oscillator (digitally controlled oscillator) to substitute voltage controlled oscillator (voltage controlledoscillator);
Fig. 7 is to use the block diagram of the dual-point modulation framework of FLL and voltage controlled oscillator;
Fig. 8 is to use the block diagram of the dual-point modulation framework of FLL and digital controlled oscillator.
Embodiment
Below in conjunction with Figure of description embodiment of the present utility model is described.
Fig. 1 shows and provides temperature-compensating output frequency f in the utility model
OutTemperature-compensating frequency synthesizer 100.Oscillating circuit 101 generates reference frequency signal f by crystal oscillator 117
RDescribed reference frequency signal f
RAs FLL 107 reference clock of (Frequency-Looked Loop is called for short FLL).Described FLL 107 generates the desired output frequency f by utilizing frequency correction control signal FCW_new (frequencycorrected control signal)
OUTOne of advantage of the present utility model, purpose or characteristics are exactly to reference clock f by frequency correction control signal FCW_new
RFrequency drift compensate.In one embodiment, frequency correction control signal FCW_new is generated by frequency correction unit 109, can get:
f
OUT＝K*FCW_new*f
R
Wherein K represents proportionality coefficient.According to proportionality coefficient K, the output frequency signal that can obtain expecting.
FCW_new＝FCW
AFC+FCW
tmp
Described automatic frequency control word FCW
AFCComprise fixed frequency control word FCW (fixed frequencycontrol signal or word) and automatic frequency correction word AFC (automatic frequencycorrection word).In one embodiment, fixed frequency control word FCW can change within the specific limits, and fixed frequency control word FCW also can be used as frequency modulated signal to generate modulation output frequency f like this
OUTHere, word (word) might not mean 8, and it means with binary sequence (such as 8,16 or 32) comes representation of data.Described automatic frequency control word FCW
AFCCan be expressed as following formula.
FCW
AFC＝FCW+AFC
Such as, needs generate frequency modulation(FM) (FrequencyModulated) signal of 890MHz～910MHz frequency range, and fixed frequency control word FCW can represent the binary sequence of described frequency range.Along with the change of fixed frequency control word FCW, automatic frequency control word FCW
AFCAlso can change thereupon.Equally, automatic frequency correction word AFC also can be as the binary sequence of the described frequency range of expression.Like this, described temperature-compensating frequency synthesizer 100 shown in Figure 1 can be counted as having the frequency modulation(FM) maker of temperature-compensating frequency.Automatic frequency correction word AFC can be provided by the outside.
In one embodiment, the automatic frequency correction word AFC clocking information that can send according to wireless base station or other precision frequency sources determines.Just can be by the value that changes automatic frequency correction word AFC to described reference clock f
RFrequency drift compensate.Like this, described reference clock f
RCan adopt simple cheaply crystal to carry out the precise dose frequency compensation, and need in crystal-oscillator circuit, not carry out complexity by AFC control numerical value, expensive
Connect frequency compensation.When frequency modulation(FM), can be as the automatic frequency correction word AFC of frequency modulated signal as the input of frequency synthesizer 100, and described fixed frequency control word FCW is as the frequency that described channel is set.
At " 3GPP TS 05.10 V8.12.0 (2003-08), Digital CellularTelecommunications System (Phase 2+); Radio Subsystem Synchronization (Release 1999) " GSM and the WCDMA standard described, need transmitting of mobile device (such as mobile phone) to compare and have greater than 0.1ppm carrier frequency accuracy with the signal of accepting from the base station.The best head and shoulders above crystal oscillator of this precision is not having the obtainable precision of frequency feedback timing.This frequency feedback corrector loop typically refers to automatic frequency control in GSM standard.Described automatic frequency control signal is a digital signal.Existing automatic frequency control loop is realized can passing through the AFC digital to analog converter usually
Automatic frequency control signal converts analog signal to.Afterwards, come outer VCXO (the voltage-controlled crystal oscillator of control strip with this analog signal, VCXO) or voltage-controlled temperature compensated oscillator (voltage-controlled temperature compensated crystal oscillator, frequency VCTCXO).Compare with the utility model, this traditional implementation need adopt additional D/A converting circuit and independently high-quality analog vco to reach high-precision frequency compensation effect.
The 105 pairs of digital temperatures in described decode logic unit are decoded and decoded signal are provided for frequency correction look-up table 111 and interpolation logical block 115.Described look-up table 111 provides suitable frequency correction signal to described interpolation logical block 115.In other words, described look-up table 111 drives described interpolation logical block 115 according to the digital temperature value of the decoding correction signal FCW that adjusts frequency
Tmp
Fig. 2 shows the not compensation temperature frequency characteristic curve diagram of common AT cutting quartz oscillator, and wherein said common AT cutting quartz crystal has in-50 ℃ to 125 ℃ temperature ranges approximately ± frequency stability of 10ppm.Fig. 3 shows and the corresponding point-to-point Tc compensated curve of compensation temperature frequency characteristic not.As shown in Figure 3, the frequency drift of the output after the compensation more do not compensate output frequency drift reduce greatly.
Figure 3 illustrates the frequency-temperature compensation point.The frequency correction word FCW that the decoded digital temperature value is corresponding with it
TmpIn storage and the look-up table 111.In production or test process, pass through relatively output frequency f
OUTAccurately measure frequency correction word FCW on each temperature spot with expected frequency
TmpUse input signal DATA
Frequency correction word FCW
TmpEnroll in the look-up table.Frequency correction value between two compensation points such as compensation point A among Fig. 3 and the temperature and frequency correcting point between the B, can be estimated by linear interpolation logical block 115.The compensation point that is stored in look-up table is many more, and the frequency correction word that interpolation obtains is accurate more.Yet the hardware spending of look-up table also can be along with compensation points purpose in the look-up table increases and increases.In one embodiment, the size minimum that can be in satisfying operating temperature range makes look-up table under the stable situation of output frequency.
Fig. 4 shows the block diagram of the FLL 107 among embodiment of the utility model.Described FLL 107 can be used for Fig. 1 and come locking frequency according to the desired output frequency of frequency control word FCW definition.Described FLL 107 comprises phase accumulator 120, numerical frequency comparator 121, digital loop filters 123, digital analog converter 125, low pass filter 127, voltage controlled oscillator 129 and comprises frequency divider 133 and the feedback loop of frequency digital quantizer 131.
Different at the phase-locked loop of phase region with conventional operation, described FLL 107 is operated in frequency domain.The major advantage of described FLL 107 is that described frequency comparator 121 has high linearity and can be designed as digital logic circuit.For conventional phase locked loops, described phase signal is to be 2 in the cycle
TTCyclical signal, described phase detectors (or comparator)
Can introduce noise and phase place surging.Described traditional phase-locked loop realizes with analog circuit usually, its design cost is increased and is difficult to realize free integrated with digital circuit.In addition, described analog phase-locked look is also very sensitive to the variation of technology, voltage and environment.
For FLL, can produce any desired output frequency by setting the FCW value, wherein said FCW value can be the frequency correction control signal FCW_new that preamble is mentioned.The precision of frequency is by word length and the reference frequency f of the FCW of phase accumulator
RDecision.For instance, reference frequency f
RBe 50MHz, the word length of FCW is 32, and the precision of frequency can reach 50MHz/2 so
32=0.01Hz.
By using the numerical frequency comparator 121 of digital loop filters 123 and high linearity, FLL can obtain low noise and high-precision signal.Yet, output frequency f
OUTCan be along with reference frequency f
RChange and change output frequency f
OUTThe frequency-drift compensation scheme can be with reference to above describing.
Be used in the feedback road
In frequency divider 133 can
The frequency signal f that voltage controlled oscillator 129 generates
VCOFrequency division is to intermediate-freuqncy signal f
IF, f wherein
IF=f
VCO/ div_n, div_n are the Frequency Dividing Factors of frequency divider 133.
Described frequency digital quantizer 131 provides its input signal of expression f
IFThe numerical frequency data flow Pvco of frequency values.The effect of described frequency digital quantizer 131 is to utilize reference frequency f
RTo input signal f
IFClock cycle (such as rising edge or trailing edge) count.The predetermined clock number is standardized as numerical frequency data flow Pvco, described numerical frequency data flow Pvco
Can be as an input of numerical frequency comparator 121.
Described phase accumulator 120 is with reference frequency f
RGenerate the reference frequency data flow Posc of expression incoming frequency control word FCW setpoint frequency value for the basis.Behind loop-locking, numerical frequency data flow Pvco should be identical with reference frequency data flow Posc.Described numerical frequency comparator 121 produces an error signal by comparative figures frequency data stream Pvco and reference frequency data flow Posc.Subsequently, 123 pairs of described error signals of described digital loop filters are carried out digital filtering.Described digital loop filters 123 provides the control of loop bandwidth and lock adjustment time.By using described digital loop filters 123, can be according to needs (such as phase noise and adjusting time) the active control loop bandwidth and the lock adjustment time of FLL.
The output of described digital loop filters 123 is input to digital analog converter 125 to generate an analog signal.The analog output signal of described digital analog converter 125 is used to control the input voltage of voltage controlled oscillator 129 after the process further low-pass filtering of described low pass filter 127.Behind loop-locking, the output of voltage controlled oscillator 129 is locked to the expected frequency that frequency control word FCW sets.
Fig. 5 shows the block diagram of the FLL 500 of the another kind of framework of the utility model.
Connecing frequency digital quantizer 531 is used for
Connect
The output signal of voltage controlled oscillator VCO 529 is converted to numerical frequency data flow Pvco.For described
Connect frequency digital quantizer 531, described frequency sampling is by high frequency output signal (such as VCO output Pvco) the known frequency reference frequency f of sampling
RRealize.One of advantage of this framework is owing to the VCO output Pvco with high frequency comes the frequency reference frequency f
RSample, thereby improved the precision of frequency digital quantizer 531.Usually the precision of frequency digital quantizer is and uses sample frequency proportional.Sample frequency is high more, and the result is accurate more, and noise is low more.In addition, this framework has been simplified the feedback road
In frequency divider design and reduced hardware cost and related power consumption.For different output frequencies, frequency divider 533 can be used to the output f of frequency division voltage controlled oscillator
VCONeeding to obtain output frequency.
The functional-block diagram of the FLL 600 in Fig. 6 the utility model, wherein said FLL 600 utilize digital controlled oscillator (digitally controlled oscillator) to substitute voltage controlled oscillator (voltagecontrolled oscillator).Described digital controlled oscillator is to finish by the voltage-operated variable capacitor design of using the numerical control capacitor array to substitute in traditional voltage controlled oscillator.Weighting switch binary system electric capacity (such as variable capacitor) array can advance the stages of digital control signal by two and switch to high capacitance pattern or low capacitive.Just can obtain high-resolution capacitance by the numerical control position of using the delta-sigma modulation.
As shown in Figure 6, phase accumulator 601, numerical frequency comparator 603, digital loop filters 605, feedback road
In frequency divider 611 and frequency digital quantizer 613 have identical functions with corresponding module among Fig. 4.Described phase accumulator 601 is with reference frequency f
RGenerate the reference frequency data flow Posc of expression incoming frequency control word FCW setpoint frequency value for the basis.Described frequency digital quantizer 613 provides its input signal of expression f
IFThe numerical frequency data flow Pvco of frequency values.Described numerical frequency comparator 603 produces an error signal by comparative figures frequency data stream Pvco and reference frequency data flow Posc.Subsequently, 605 pairs of described error signals of described digital loop filters are carried out digital filtering.
The output of described digital loop filters 605 is connected to the input of digital controlled oscillator gain control unit 607, and digital controlled oscillator gain control unit 607 can generate the digital controlled signal of the weighting switch binary system capacitor array that is used to control digital controlled oscillator.Described digital controlled oscillator gain control unit 607 is used for normalization digital controlled oscillator gain and eliminates the influence to digital controlled oscillator phase place and frequency from technology, voltage and temperature.Be used in the feedback road
In frequency divider 611 can
The frequency signal f that digital controlled oscillator 609 generates
DCOFrequency division is to intermediate-freuqncy signal f
IFDescribed frequency digital quantizer 613 is further
Described intermediate-freuqncy signal f
IFBe converted to numerical frequency data flow Pvco.Behind loop-locking, by using numerical frequency comparator 603, numerical frequency data flow Pvco is locked to reference frequency data flow Posc.Like this, the output of digital controlled oscillator 609 is locked to the expected frequency that frequency control word FCW sets.
As shown in Figure 6, thereby can remove digital analog converter and low pass filter among Fig. 4 by utilizing digital controlled oscillator to substitute voltage controlled oscillator, whole like this FLL 600 can realize by digital logical course.Like this, frequency signal
Be not easy to be subjected to the influence of noise and other environment.This framework especially is fit to low pressure, deep-submicron COMS technology, because the traditional analog oscillator the range of linearity owing to low-voltage becomes very little, and has higher gain, this makes analog vco very easily be subjected to the influence of noise and operating point drift, but, just adopt digital vco
Be not easy to be subjected to the influence of low-voltage and other factor of environmental.
Fig. 7 is to use the block diagram of the dual-point modulation framework of FLL and voltage controlled oscillator.Described frequency modulated signal FM is that to meet the modulating signal phase that the frequency correction word FCW frequency format of FLL input represents poor.Described modulating data FW is injected into 2 of FLL and is used for
Connect frequency modulation(FM).At a decanting point, utilize adder 723
Described modulating data FW and FCW add with the AFC numeric word and are in the same place.Afterwards,
This synthetic modulating data FCW ' is converted to the reference frequency data flow Posc of expression incoming frequency control word FCW ' setpoint frequency value.
At another decanting point, at first utilize digital to analog converter 721
Described modulation signal converts analog signal to, utilizes adder 717 afterwards
Described analog signal adds in the input control signal of voltage controlled oscillator 709.This injection modulation signal
The frequency data that connect the output of modulation voltage controlled oscillator and cause frequency digital quantizer 713 to produce flow the variation of Pvco.Frequency data stream Pvco that causes by the injection of FM modulation signal and the variation of reference frequency data flow Posc
Can in the output of numerical frequency comparator 701, cancel out each other.Like this, by frequency correction word FCW lock channel frequency and utilize automatic frequency correction word AFC to come compensating frequency when drift, described loop filter 703 can be operated in very on the narrow bandwidth to reduce the spurious frequency and the noise of output.Owing to when described FLL is followed the trail of carrier frequency, do not need Broad-band Modulated Signal through loop low pass filter, thus this FLL can be operated under the narrow loop bandwidth condition, to reduce the spurious frequency of output.When open loop situations, utilize the adaptive gain control unit
Connect
Described wideband frequency modulation signal is used to modulate VCO.Like this, can obtain modulation and the frequency synthesis of low output noise and the requirement of modulation simultaneously to broadband signal.
For the non-linear influence to modulation signal of compensated voltage controlled oscillator 709 owing to technology, voltage and temperature drift, adaptive gain control unit 719 is used for
The frequency error that numerical frequency comparator 701 generates according to the gain of the frequency error bi-directional scaling modulation signal FM that receives with the adaptively changing voltage controlled oscillator, reaches the requirement to the voltage controlled oscillator modulation linearityization as input.
Fig. 8 is to use the block diagram of the dual-point modulation framework of FLL and digital controlled oscillator, and it has used the FLL 830 based on digital controlled oscillator.Described frequency modulated signal FM is injected into 2 points of FLL, and one of them is adder 823 points, and it causes the change of reference frequency data flow Posc, and another is adder 807 points, and it causes the change of frequency data stream Pvco.The variation of frequency data stream Pvco and reference frequency data flow Posc
Can in the output of numerical frequency comparator 801, cancel out each other.
For the influence of offset value controlled oscillator gain owing to technology, voltage and temperature drift, before modulation signal FM injects the input of digital controlled oscillator 809, the size of the frequency error signal that adaptive gain control unit 819 can produce according to numerical frequency comparator 801 is to modulation signal FM corrections that gain, so that the frequency error signal value minimum of comparator 801 generations.FLL shown in Figure 8 can realize the wideband frequency modulation of full-digital circuit.
The utility model is realized also can adopting other different modes to realize to the synthetic of frequency with modulating except that aforesaid way.In one embodiment, the utility model can be used for realizing the stable clock frequency synthesis of an integrated circuit or system integrated chip.In another embodiment, the utility model can be used for frequency modulating signal.In another embodiment, the utility model can be used in the instrument and meter by manually controlling the signal of synthetic various different frequencies.
The above only is preferred embodiment of the present utility model, and is in order to restriction the utility model, not all within spirit of the present utility model and principle, any modification of being done, is equal to replacement etc., all should be included within the protection range of the present utility model.
Claims (8)
1, a kind of frequency synthesizer is characterized in that, it comprises:
Since be the FLL of basis operation from the reference frequency of crystal oscillation device, wherein said crystal oscillator is connected with described FLL and the reference frequency of its output is offered described FLL;
The frequency correction unit that is connected with described FLL, with first parameter and second parameter serves as that the basis generates the digitally correcting frequency control word, and described digitally correcting frequency control word offered described FLL, described first parameter is the combination of automatic frequency correction word and fixed frequency control word;
The interpolation logical block that is connected with frequency correction unit is used to generate second parameter that the expression variations in temperature compensates, and described second parameter is offered described frequency correction unit;
Wherein, described FLL generates timing clock signal or when first parameter described FLL generated frequency modulation signal during for the binary sequence of the frequency shift of representing modulation signal when first parameter is constant.
2, frequency synthesizer as claimed in claim 1 is characterized in that, f
UTRepresent described clock signal, f
RThe expression reference frequency, FCW_new represents described digitally correcting frequency control word, and following formula is then arranged:
f
UT＝K*FCW_new*f
R，
Wherein K represents proportionality coefficient K.
3, frequency synthesizer as claimed in claim 1 is characterized in that, it further comprises:
Digital temperature sensor is used to respond to the environment temperature of the temperature that comprises described frequency synthesizer place integrated circuit;
The decode logic unit is connected with digital temperature sensor, and reception and decoding are from the digital measurement of temperature value of digital temperature sensor;
Look-up table is used for the corresponding relation of storing frequencies correction signal and temperature, and drives the interpolation logical block and adjust second parameter.
4, frequency synthesizer as claimed in claim 1 is characterized in that, described FLL comprises:
The digit phase accumulator receives the digitally correcting frequency control word from described frequency correction unit, and the frequency accuracy of wherein said clock signal or frequency modulated signal is by the word length of digit phase accumulator and reference frequency decision;
The numerical frequency comparator, the output of comparative figures phase accumulator and comprise frequency divider and the output of the feedback loop of frequency digital quantizer;
The digital loop filter is connected with the numerical frequency comparator, is used for the error signal of numerical frequency comparator output is carried out filtering, and wherein said digital loop filter provides the control of loop bandwidth and lock adjustment time;
Digital analog converter is connected with the digital loop filter, and the output that receives the digital loop filter is to generate analog signal;
Low pass filter is used for described analog signal is carried out filtering, and described analog signal has further been controlled the input voltage of voltage controlled oscillator, and wherein described FLL enters lock-out state when the output of voltage controlled oscillator is locked in expected frequency.
5, frequency synthesizer as claimed in claim 4 is characterized in that, described FLL further comprises:
Directly the frequency digital quantizer is used to utilize reference frequency that the output signal of voltage controlled oscillator is directly changed into the numerical frequency data flow.
6, frequency synthesizer as claimed in claim 4 is characterized in that, described FLL further comprises:
Direct frequency digital quantizer, thus the output signal that the output signal that is used to utilize voltage controlled oscillator is sampled directly voltage controlled oscillator to reference frequency is converted to the numerical frequency data flow.
7, frequency synthesizer as claimed in claim 6 is characterized in that, described FLL further comprises:
Be used for the output of voltage controlled oscillator is carried out frequency division to obtain the frequency divider of described clock signal.
8, frequency synthesizer as claimed in claim 3 is characterized in that, described FLL comprises:
The digit phase accumulator receives the digitally correcting frequency control word and generates the reference frequency data flow from described frequency correction unit, and the frequency accuracy of wherein said clock signal or frequency modulated signal is by the word length of digit phase accumulator and reference frequency decision;
The numerical frequency comparator, the output of comparative figures phase accumulator and comprise frequency divider and the output of the feedback loop of frequency digital quantizer;
The digital loop filter is connected with the numerical frequency comparator, is used for the error signal of numerical frequency comparator output is carried out filtering, and wherein said digital loop filter provides the control of loop bandwidth and lock adjustment time;
The digital controlled oscillator gain control circuit, be output as the digital controlled signal that the basis generates the weighting switch binary system capacitor array be used to control digital controlled oscillator with the digital loop filter, wherein said digital controlled oscillator gain control unit is used to eliminate the influence to phase place and frequency of technology, voltage and temperature; With
Numerically-controlled oscillator, generate wireless frequency signal, described wireless frequency signal is converted into intermediate-freuqncy signal, the frequency digital quantizer further converts described intermediate-freuqncy signal to the numerical frequency data flow, and wherein described FLL enters lock-out state when the numerical frequency data flow is locked in the reference frequency data flow.
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| CNU2008200586465U CN201270504Y (en) | 2008-05-20 | 2008-05-20 | Frequency synthesizer |
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| CNU2008200586465U CN201270504Y (en) | 2008-05-20 | 2008-05-20 | Frequency synthesizer |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101272142B (en) * | 2008-05-20 | 2011-05-18 | 曹秀娟 | Frequency synthesizer |
| CN102193029A (en) * | 2010-03-19 | 2011-09-21 | 上海市计量测试技术研究院 | Method for measuring short-term frequency stability of unconventional sampling time |
| CN105306056A (en) * | 2014-07-28 | 2016-02-03 | 北京自动化控制设备研究所 | Scale factor temperature compensating method of current frequency conversion circuit |
| CN106844824A (en) * | 2016-11-22 | 2017-06-13 | 电子科技大学 | A kind of radio frequency crystal oscillator residual life method of estimation based on acceleration vibration condition |
| CN111642140A (en) * | 2019-01-02 | 2020-09-08 | 京东方科技集团股份有限公司 | Measuring device and measuring method |
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2008
- 2008-05-20 CN CNU2008200586465U patent/CN201270504Y/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101272142B (en) * | 2008-05-20 | 2011-05-18 | 曹秀娟 | Frequency synthesizer |
| CN102193029A (en) * | 2010-03-19 | 2011-09-21 | 上海市计量测试技术研究院 | Method for measuring short-term frequency stability of unconventional sampling time |
| CN102193029B (en) * | 2010-03-19 | 2013-05-01 | 上海市计量测试技术研究院 | Method for measuring short-term frequency stability of unconventional sampling time |
| CN105306056A (en) * | 2014-07-28 | 2016-02-03 | 北京自动化控制设备研究所 | Scale factor temperature compensating method of current frequency conversion circuit |
| CN105306056B (en) * | 2014-07-28 | 2019-04-23 | 北京自动化控制设备研究所 | A kind of constant multiplier temperature-compensation method of power frequency conversion circuit |
| CN106844824A (en) * | 2016-11-22 | 2017-06-13 | 电子科技大学 | A kind of radio frequency crystal oscillator residual life method of estimation based on acceleration vibration condition |
| CN106844824B (en) * | 2016-11-22 | 2020-05-12 | 电子科技大学 | Radio frequency crystal oscillator residual life estimation method based on accelerated vibration condition |
| CN111642140A (en) * | 2019-01-02 | 2020-09-08 | 京东方科技集团股份有限公司 | Measuring device and measuring method |
| CN111642140B (en) * | 2019-01-02 | 2023-12-01 | 京东方科技集团股份有限公司 | Measuring device and measuring method |
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