CN201185431Y - Phase shift keying demodulator - Google Patents
Phase shift keying demodulator Download PDFInfo
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- CN201185431Y CN201185431Y CNU2008200771305U CN200820077130U CN201185431Y CN 201185431 Y CN201185431 Y CN 201185431Y CN U2008200771305 U CNU2008200771305 U CN U2008200771305U CN 200820077130 U CN200820077130 U CN 200820077130U CN 201185431 Y CN201185431 Y CN 201185431Y
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The utility model discloses a phase shift keying demodulator, relates to a multi-standard data receiving demodulator device in the field of remote sensing and meteorological satellite receiving system. The demodulator comprises the parts of a monitoring unit, an intermediate frequency unit, a baseband demodulation and decoding module, a frequency source switching module, a power supply and so on. In the working process of the demodulator, the intermediate frequency signal input from the external part is received, and is processed with quadrature demodulation by the intermediate frequency unit. And then the demodulated zero intermediate frequency signal is send to the baseband demodulation and decoding module. The input complex baseband signal is processed with demodulation and decoding by the baseband demodulation and decoding module. The decoded data is output, and the PSK demodulation purpose is realized. The demodulator is characterized in that the demodulator has high integration degree, stable and reliable performance, light weight, low power consumption, simple structure and so on, which is particularly applied for various demodulators of the remote sensing and meteorological satellite receiving system.
Description
Technical field
The utility model relates to a kind of phase shift keying (the being called for short PSK) demodulator in remote sensing, the Meteorologic Satellite Receiving system field, is specially adapted to do the modem device of multiple remote sensing, weather satellite data reception.
Background technology
Raising along with the increasing of remote sensing and meteorological number of satellite, resolution, its data format is varied, data transmission rate also improves constantly, original demodulator uses multiple demodulator at different meteorological satellites, cause that equipment volume is big, complicated operation, press for the demodulator that a kind of energy of development is suitable for multiple Meteorologic Satellite Receiving, this demodulator can receive the weather satellite data of a new generation, and can compatiblely receive existing multiple satellite data.
Summary of the invention
It can be the PSK demodulator of 500K～30Mbps to multiple standard Data Receiving, data rate that the purpose of this utility model is to avoid the weak point in the above-mentioned background technology and provide a kind of, the utility model also have integrated degree height, stable and reliable for performance, in light weight, low in energy consumption, simple in structure, can be than the following characteristics such as operate as normal of harsh environmental conditions (10 ℃～55 ℃).
The purpose of this utility model is achieved in that it is by monitoring unit 1, keypad 2, LCD 3, power supply 4, base band demodulating decoding module 5, intermediate frequency unit 6, frequency source handover module 7 is formed, wherein intermediate frequency unit 6 inputs 1 pin is connected with outside L frequency range intermediate frequency input port A, intermediate frequency unit 6 inputs 4 pin, 5 pin by data wire respectively with base band demodulating decoding module 5 outputs 3 pin, 4 link to each other, base band demodulating decoding module 5 inputs 1 pin, 2 pin respectively with intermediate frequency unit 6 outputs 2 pin, 3 pin connect, base band demodulating decoding module 5 data output ends 5 pin are connected with external output port C, base band demodulating decoding module 5 output terminal of clock 6 pin are connected with external output port D, base band demodulating decoding module 5 discrepancy ends 7 pin go out inbound port E with the outside and are connected, base band demodulating decoding module 5 inputs 8 pin are connected with monitoring unit 1 output 3 pin, monitoring unit 1 output 4 pin are connected with LCD 3 inputs 1 pin by data wire, input 2 pin are connected with keypad 2 outputs 1 pin by data wire, frequency source handover module 7 inputs 1 pin is connected with the external frequency source input port B, frequency source handover module 7 outputs 2 pin are connected power supply 4 output ports+V1 with intermediate frequency unit 6 inputs 6 pin, + V2, the corresponding power end with each parts of-V3 voltage end also connects.
The purpose of this utility model can also reach by following measure:
The utility model baseband modulation and demodulation module 5 is by bit timing recovery circuit 8, digital down converter 9, matched filter 10, adaptive equalizer 11, carrier recovery circuit 12, decoder 13 is formed, digital down converter 9 inputs 1 pin wherein, 4 pin respectively with intermediate frequency unit 6 outputs 1 pin, 2 pin connect, digital down converter 9 outputs 3 pin are connected with matched filter 10 inputs 2 pin, matched filter 10 outputs 5 pin are connected with Adpative equalizing circuit 11 inputs 2 pin, Adpative equalizing circuit 11 outputs 4 pin are connected with carrier recovery circuit 12 inputs 3 pin, carrier recovery circuit 12 outputs 4 pin are connected with digital down converter 9 inputs 6 pin, Adpative equalizing circuit 11 outputs 1 are connected with bit timing recovery circuit 8 inputs 4 pin, bit timing recovery circuit 8 outputs 1 pin is connected with Digital Down Convert 9 inputs 2 pin, bit timing recovery circuit 8 outputs 2 pin are connected with matched filtering circuit 10 inputs 1 pin, Adpative equalizing circuit 11 outputs 6 pin are connected with decoder 13 inputs 3 pin, decoder 13 outputs 5 pin, 6 pin, 7 pin respectively with external output port C, D, E connects, bit timing recovery circuit 8, adaptive equalizer 11 each input 3 pin are connected with power supply 4 outputs+V1 voltage end, bit timing recovery circuit 8, adaptive equalizer 11 inputs 5 pin are connected with the ground end, digital down converter 9 inputs 5 pin are connected with power supply 4 outputs+V1 voltage end, digital down converter 9 inputs 7 pin are connected with the ground end, matched filter 10 inputs 3 pin are connected with power supply 4 outputs+V1 voltage end, input 7 pin are connected with the ground end, carrier recovery circuit 12, decoder 13 each input 1 pin are connected with power supply 4 outputs+V1 voltage end, each input 2 pin and ground end is connected, monitoring unit 1 output 3 pin respectively with bit timing recovery circuit 8, digital down converter 9, matched filter 10, adaptive equalizer 11, carrier recovery circuit 12, each input 8 pin of decoder 13 also connect.
The utility model is compared with background technology has following advantage:
1. after the utility model adopted the high-speed digital signal treatment technology of baseband modulation and demodulation module 5, accessible data rate reached 500K～30Mbps, thereby satisfies big data quantity Data Receiving user's actual demand.
2. the integrated degree height of each parts of the utility model, each parts all adopts the integration module circuit production, and is low in energy consumption, the machine debugging workload is little, and is stable and reliable for performance, can be under than rugged environment (10 ℃～55 ℃) condition operate as normal.
3. the utility model adopts the standard profile structure, and is simple in structure, and inner compact, cost is low, has application value.
Description of drawings
Fig. 1 is a functional-block diagram of the present utility model.
Fig. 2 is the electrical schematic diagram of the utility model base band demodulating decoding module 5.
Embodiment
Referring to figs. 1 through Fig. 2, the utility model is made up of monitoring unit 1, keypad 2, LCD 3, power supply 4, base band demodulating decoding module 5, intermediate frequency unit 6, frequency source handover module 7, Fig. 1 is a functional-block diagram of the present utility model, and embodiment presses Fig. 1 connection line.Wherein base band demodulating decoding module 5 end 7 pin of coming in and going out go out inbound port E by the RS-485 interface with the outer monitoring system and are connected, be used to implement monitoring and control to this machine, supervisory circuit 1 input 2 pin go out end 1 pin with keypad 2 and are connected, by button operation modification of this machine or the state of this machine of monitoring, and LCD 3 demonstrations by being connected with supervisory circuit 1 output 4 pin.Supervisory circuit 1 output 3 pin are connected with base band demodulating decoding module 5 inputs 8 pin, are used to control running parameters such as the information rate of this machine and modulation system, and detect its operating states such as signal to noise ratio.Supervisory circuit 1 its effect is exactly an operate as normal of controlling this machine by these controls and monitoring port, and embodiment supervisory circuit 1 adopts commercially available dedicated cpu integrated circuit C8051F023, application-specific integrated circuit (ASIC) 74LVC4245A, EPM 7064STI44-7, clock circuit DS12C887,485 interface circuit MAX1482ESD to make.LCD 3 embodiment adopt 12 * 12 Chinese to show the liquid crystal making.Keypad 2 embodiment adopt 4 * 4 buttons to make.
7 effects of frequency source modular converter are the outside 10MHz frequency source that input port B is imported to be switched from the 10MHz frequency source that produces with it export intermediate frequency unit 6 to, and embodiment frequency source modular converter 7 adopts the 10MHz frequency source making of special use.
The effect of the utility model base band demodulating decoding module 5 is that psk modulation signal is carried out base band demodulating and decoding, and it is made up of bit timing recovery circuit 8, digital down converter 9, matched filter 10, adaptive equalizer 11, carrier recovery circuit 12, decoder 13.The electric principle connection line of embodiment baseband modulation and demodulation module 5 as shown in Figure 2.Wherein 8 its effects of bit timing recovery circuit are adjustment of carrying out track loop by timing information, the optimum sampling point of obtaining at receiving terminal, 9 its effects of signal digital low-converter are to carry out the orthogonal digital low-converter to received signal, matched filter 10 its effects are Waveform Matching of finishing to received signal, adaptive equalizer 11 its effects are equilibriums of finishing broadband signal, eliminate intersymbol interference, carrier recovery circuit 12 its effects are extractions of finishing the carrier information of coherent demodulation, decoder 13 its effects are to finish error-correcting decoding, embodiment bit timing recovery circuit 8, digital down converter 9, matched filter 10, adaptive equalizer 11, carrier recovery circuit 12, decoder 13 each functional modules adopt the programming device of a monolithic FBGA chip EP2S30484C5 model to make.
4 its effects of the utility model power supply provide parts direct-current working volts at different levels, and embodiment power module 4 adopts the power module of T-60C types to make, and its output+V1 voltage is that+5 volts, output+V2 voltage are+12 volts, and-V3 voltage is-12 volts.The utility model each several part parts have all adopted modularity design technology, constitute to have the corresponding units of standalone feature.
The concise and to the point operation principle of the utility model is as follows: PSK demodulator operating rate is 500K～30Mbps, in the PSK demodulator course of work, intermediate frequency unit 6 receives the intermediate-freuqncy signal of outside input, and to the input intermediate-freuqncy signal carry out quadrature demodulation, send base band demodulating decoding module 5 zero intermediate frequency signals after the demodulation then, the complex baseband signal of 5 pairs of inputs of base band demodulating decoding module carries out demodulation coding, and the data output of decoding back.In the communication process, supervisory circuit 1 is finished the setting of demodulation parameter, the functions such as detection of this machine work signal to noise ratio.
Mounting structure of the present utility model is as follows: complete machine adopts standard 1U cabinet, and cabinet inside adopts modular construction, and each component models all adopts independently circuit to realize; Machine shape is of a size of 482.6 millimeters * 43.6 millimeters * 472 millimeters, in the cabinet both sides rail plate can be installed, the cabinet front portion is equipped with LCD 3, keypad 2 and indicator light, the cabinet rear portion is equipped with supply socket, intermediate frequency input port A socket, external frequency source input port B socket, data-out port C socket, output terminal of clock mouth D socket and standard RS-485 control interface E far away socket, assembly cost utility model.
Claims (2)
1. phase shift keying demodulator, it comprises monitoring unit (1), keypad (2), LCD (3), power supply (4), intermediate frequency unit (6), frequency source handover module (7), it is characterized in that: also comprise base band demodulating decoding module (5), wherein intermediate frequency unit (6) input 1 pin is connected with outside L frequency range intermediate frequency input port A, intermediate frequency unit (6) input 4 pin, 5 pin by data wire respectively with base band demodulating decoding module (5) output 3 pin, 4 link to each other, base band demodulating decoding module (5) input 1 pin, 2 pin respectively with intermediate frequency unit (6) output 2 pin, 3 pin connect, base band demodulating decoding module (5) data output end 5 pin are connected with external output port C, base band demodulating decoding module (5) output terminal of clock 6 pin are connected with external output port D, base band demodulating decoding module (5) discrepancy end 7 pin go out inbound port E with the outside and are connected, base band demodulating decoding module (5) input 8 pin are connected with monitoring unit (1) output 3 pin, monitoring unit (1) output 4 pin are connected with LCD (3) input 1 pin by data wire, input 2 pin are connected with keypad (2) output 1 pin by data wire, frequency source handover module (7) input 1 pin is connected with the external frequency source input port B, frequency source handover module (7) output 2 pin are connected power supply (4) output port+V1 with intermediate frequency unit (6) input 6 pin, + V2, the corresponding power end with each parts of-V3 voltage end also connects.
2. phase shift keying demodulator according to claim 1, it is characterized in that: base band demodulating decoding module (5) is by bit timing recovery circuit (8), digital down converter (9), matched filter (10), adaptive equalizer (11), carrier recovery circuit (12), decoder (13) is formed, digital down converter (9) input 1 pin wherein, 4 pin respectively with intermediate frequency unit (6) output 1 pin, 2 pin connect, digital down converter (9) output 3 pin are connected with matched filter (10) input 2 pin, matched filter (10) output 5 pin are connected with Adpative equalizing circuit (11) input 2 pin, Adpative equalizing circuit (11) output 4 pin are connected with carrier recovery circuit (12) input 3 pin, carrier recovery circuit (12) output 4 pin are connected with digital down converter (9) input 6 pin, Adpative equalizing circuit (11) output 1 is connected with bit timing recovery circuit (8) input 4 pin, bit timing recovery circuit (8) output 1 pin is connected with Digital Down Convert (9) input 2 pin, bit timing recovery circuit (8) output 2 pin are connected with matched filtering circuit (10) input 1 pin, Adpative equalizing circuit (11) output 6 pin are connected with decoder (13) input 3 pin, decoder (13) output 5 pin, 6 pin, 7 pin respectively with external output port C, D, E connects, bit timing recovery circuit (8), each input 3 pin of adaptive equalizer (11) are connected with power supply (4) output+V1 voltage end, bit timing recovery circuit (8), adaptive equalizer (11) input 5 pin are connected with the ground end, digital down converter (9) input 5 pin are connected with power supply (4) output+V1 voltage end, digital down converter (9) input 7 pin are connected with the ground end, matched filter (10) input 3 pin are connected with power supply (4) output+V1 voltage end, input 7 pin are connected with the ground end, carrier recovery circuit (12), each input 1 pin of decoder (13) is connected with power supply (4) output+V1 voltage end, each input 2 pin and ground end is connected, monitoring unit (1) output 3 pin respectively with bit timing recovery circuit (8), digital down converter (9), matched filter (10), adaptive equalizer (11), carrier recovery circuit (12), each input 8 pin of decoder (13) also connect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200771305U CN201185431Y (en) | 2008-04-30 | 2008-04-30 | Phase shift keying demodulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200771305U CN201185431Y (en) | 2008-04-30 | 2008-04-30 | Phase shift keying demodulator |
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| Publication Number | Publication Date |
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| CN201185431Y true CN201185431Y (en) | 2009-01-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNU2008200771305U Expired - Fee Related CN201185431Y (en) | 2008-04-30 | 2008-04-30 | Phase shift keying demodulator |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101909180B (en) * | 2009-06-04 | 2011-11-30 | 承景科技股份有限公司 | Digital intermediate-frequency demodulator |
| CN101674272B (en) * | 2009-10-26 | 2012-01-25 | 西安空间无线电技术研究所 | System and method for recovering high-speed parallel 8PSK carriers |
| CN109309641A (en) * | 2017-07-28 | 2019-02-05 | 西安电子科技大学 | A kind of QPSK base band recovery system resisting big frequency deviation |
-
2008
- 2008-04-30 CN CNU2008200771305U patent/CN201185431Y/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101909180B (en) * | 2009-06-04 | 2011-11-30 | 承景科技股份有限公司 | Digital intermediate-frequency demodulator |
| CN101674272B (en) * | 2009-10-26 | 2012-01-25 | 西安空间无线电技术研究所 | System and method for recovering high-speed parallel 8PSK carriers |
| CN109309641A (en) * | 2017-07-28 | 2019-02-05 | 西安电子科技大学 | A kind of QPSK base band recovery system resisting big frequency deviation |
| CN109309641B (en) * | 2017-07-28 | 2020-04-14 | 西安电子科技大学 | QPSK baseband recovery system resistant to large frequency offset |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090121 Termination date: 20160430 |