CN201142229Y - Flash memory array device - Google Patents
Flash memory array device Download PDFInfo
- Publication number
- CN201142229Y CN201142229Y CNU2007201988860U CN200720198886U CN201142229Y CN 201142229 Y CN201142229 Y CN 201142229Y CN U2007201988860 U CNU2007201988860 U CN U2007201988860U CN 200720198886 U CN200720198886 U CN 200720198886U CN 201142229 Y CN201142229 Y CN 201142229Y
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- flash memory
- memory array
- flash
- array
- output interface
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Abstract
The utility model discloses a flash memory array device which has the advantages that memory size is increased, access speed is expedited and power consumption is lowered. The technical proposal is that the flash memory array device comprises a physical input/output interface which is used for processing the data transmission with the external; a flash memory array composed of a plurality of flash memory modules; and a controller of the flash memory array, wherein, the controller of the flash memory array is arranged between the physical input/output interface and the flash memory array; the controller of the flash memory array further comprises block mapping units which are used for the address mapping between a logical address and a physical address, wherein, the logical address is used for transmitting data between the physical input/output interface and the external, and the physical address is used for transmitting data between the physical input/output interface and the flash memory array. The flash memory array device is applied in the memory device field.
Description
Technical field
The utility model relates to flash memory device, relates in particular to a kind of memory storage that flash memory module is provided with array format.
Background technology
Flash memory (flash memory) memory technology, as nand flash memory, the advantage that has tangible power consumption and reliability with respect to traditional storage based on disk, advantageous particularly in portable and embedded system can reduce the power consumption of the system component that comprises secondary storage to greatest extent.Traditional disk replacing between low-power consumption and high-performance operates, and the parts of their rotations of wearing and tearing too early make whole storage system to work.Therefore can attempt using flash memory storage to replace traditional disk storage such as hard-disc storage.
But, in attempting the process of doing to substitute, running into this problem, flash memory storage is compared with traditional disk storage, and its capacity is restricted, and makes flash memory storage per unit storage in the high power capacity cost performance spend more cost than disk.And when flash capacity became big, its access speed can reduce greatly along with the change of capacity.
Summary of the invention
The purpose of this utility model is to address the above problem, and a kind of flash memory array device is provided, and adds large storage capacity, accelerates access speed, has reduced power consumption.
The technical solution of the utility model is: the utility model has disclosed a kind of flash memory array device, comprising:
The physics input/output interface carries out data transmission with the external world;
The flash array that a plurality of flash memory modules are formed;
The flash array controller is arranged between this physics input/output interface and this flash array, further comprises:
The piece map unit is carried out map addresses between the physical address of data transmission between logical address, this physics input/output interface and this flash array of data transmission between this physics input/output interface and the external world.
Above-mentioned flash memory array device, wherein, those flash memory modules in this flash array are arranged side by side.
Above-mentioned flash memory array device, wherein, this physics input/output interface comprise USB interface, SATA interface, eSATA interface, ata interface one of them.
Above-mentioned flash memory array device, wherein, this device also comprises the printed circuit board (PCB) that holds this flash array controller.
Above-mentioned flash memory array device, wherein, this device also comprises a shell.
Above-mentioned flash memory array device, wherein, this piece map unit is to come mapping address by array that those flash memory modules are formed as the independent array of the addressable blocks of linearity.
Above-mentioned flash memory array device, wherein, this piece map unit is come mapping address by those flash memory modules of while parallel access.
The utility model contrast prior art has following beneficial effect: the utility model is by becoming a flash array side by side with a plurality of flash memory modules, and logical address by setting up interface and PERCOM peripheral communication and the mapping between the internal physical address, compared to traditional flash memory device (such as flash card), it has bigger memory capacity, compared to traditional disk storage device, it has access speed and lower power consumption faster.
Description of drawings
Fig. 1 is the schematic diagram of the preferred embodiment of flash memory array device of the present utility model.
Embodiment
The utility model will be further described below in conjunction with drawings and Examples.
Fig. 1 shows the principle of the preferred embodiment of flash memory array device of the present utility model.See also Fig. 1, flash memory array device 1 comprises physics input/output interface 10, flash array controller 12, flash array 14.Certainly, array apparatus can also comprise printed circuit board (PCB) (not shown) and the shell (not shown) that holds flash array controller 12.Piece map unit 120 is set in the flash array controller 12.Flash array 14 is by flash memory module 141, flash memory module 142 ... a plurality of flash memory modules such as flash memory module 14N are formed, can be as shown in Figure 1 parallel side by side, also can be other arrangement mode.
Physics input/output interface 10 carries out data transmission with the external world, and this data transmission is based on that logical address carries out.The external world comprises memory device, read-write equipment, bus structure etc.Physics input/output interface 10 comprise USB interface, SATA interface, ide interface, eSATA interface, ata interface one of them.For example when device 1 connects with computing machine, the physical store bus interaction of interface 10 and main frame, and the I/O request of main frame is converted to the read write command of logic in the runtime.Interface 10 is also handled the bus particular command, as the order of those discoveries and initialization apparatus.In case receive the read write command of memory bus, interface 10 translations that they will be installed.The physical interface form of physics input/output interface 10 does not limit scope of the present utility model.
From the data that physics input/output interface 10 receives with logical address, need be stored in one of them flash memory module of flash array 14.Because each flash memory module of interface 10 and inside is based on the physical address addressing, the piece map unit 120 in the flash array controller 12 is responsible for this logical address is mapped to physical address.Data are stored on the corresponding flash memory module based on the physical address after shining upon.Similarly, when the data that are stored in a certain flash memory module are outwards transmitted by interface 10, also need by piece map unit 120 logical address of internal physical map addresses to the outside.
The mapping mode of piece map unit 120 has two kinds.The flash array that piece map unit 120 can be formed flash memory module arranged side by side is as the independent array of the addressable blocks of linearity.For example, the capacity of supposing each flash memory module is 256 physical blocks, and then first logical block comprises logical address 0～255, and second logical block comprises logical address 256～511, and the rest may be inferred.But shift for linear data in enormous quantities, its overall performance is subjected to the wherein quantitative limitation of handling up of any one separate, stored module.
The utility model can substitute disk storage to obtain lower power consumption by flash memory storage.The utility model has strengthened the capacity of flash memory storage by a plurality of flash memory modules are organized into array.Flash array in the utility model can be from each flash memory module the parallel read write data, for example, it can end the reading and writing data on other flash memory modules in read-write part flash memory module, can accelerate the speed of flash memory storage like this.
The foregoing description provides to those of ordinary skills and realizes or use of the present utility model; those of ordinary skills can be under the situation that does not break away from invention thought of the present utility model; the foregoing description is made various modifications or variation; thereby protection domain of the present utility model do not limit by the foregoing description, and should be the maximum magnitude that meets the inventive features that claims mention.
Claims (7)
1, a kind of flash memory array device is characterized in that, comprising:
The physics input/output interface carries out data transmission with the external world;
The flash array that a plurality of flash memory modules are formed;
The flash array controller is arranged between this physics input/output interface and this flash array, further comprises:
The piece map unit is carried out map addresses between the physical address of data transmission between logical address, this physics input/output interface and this flash array of data transmission between this physics input/output interface and the external world.
2, flash memory array device according to claim 1 is characterized in that, those flash memory modules in this flash array are arranged side by side.
3, flash memory array device according to claim 2 is characterized in that, this physics input/output interface comprise USB interface, SATA interface, eSATA interface, ata interface one of them.
4, flash memory array device according to claim 1 is characterized in that, this device also comprises the printed circuit board (PCB) that holds this flash array controller.
5, flash memory array device according to claim 1 is characterized in that, this device also comprises a shell.
6, flash memory array device according to claim 2 is characterized in that, this piece map unit is to come mapping address by array that those flash memory modules are formed as the independent array of the addressable blocks of linearity.
7, flash memory array device according to claim 2 is characterized in that, this piece map unit is come mapping address by those flash memory modules of while parallel access.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2007201988860U CN201142229Y (en) | 2007-12-05 | 2007-12-05 | Flash memory array device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2007201988860U CN201142229Y (en) | 2007-12-05 | 2007-12-05 | Flash memory array device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201142229Y true CN201142229Y (en) | 2008-10-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2007201988860U Expired - Lifetime CN201142229Y (en) | 2007-12-05 | 2007-12-05 | Flash memory array device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201142229Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332290A (en) * | 2010-05-24 | 2012-01-25 | 慧荣科技股份有限公司 | Apparatuses for managing and accessing flash memory module |
| CN104699227A (en) * | 2015-04-01 | 2015-06-10 | 苏州壹世通科技有限公司 | Power supply control method and device |
-
2007
- 2007-12-05 CN CNU2007201988860U patent/CN201142229Y/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332290A (en) * | 2010-05-24 | 2012-01-25 | 慧荣科技股份有限公司 | Apparatuses for managing and accessing flash memory module |
| CN102332290B (en) * | 2010-05-24 | 2015-02-04 | 慧荣科技股份有限公司 | Apparatuses for managing and accessing flash memory module |
| CN104699227A (en) * | 2015-04-01 | 2015-06-10 | 苏州壹世通科技有限公司 | Power supply control method and device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20081029 Effective date of abandoning: 20071205 |