CN201107355Y

CN201107355Y - Time synchronization error measuring circuit based on CPLD technology

Info

Publication number: CN201107355Y
Application number: CNU2007200885960U
Authority: CN
Inventors: 涂文杰; 刘帆; 谭显春; 李家志; 陈璇
Original assignee: China Ship Development and Design Centre
Current assignee: China Ship Development and Design Centre
Priority date: 2007-11-29
Filing date: 2007-11-29
Publication date: 2008-08-27
Anticipated expiration: 2017-11-29

Abstract

The utility model provides a time synchronization error measuring circuit based on the CPLD technology. In the circuit, a first input end of an or gate is connected with a reference pulse signal joint point, a second input end of the or gate is connected with a tested pulse signal joint point; a first input end of an AND gate is connected with the tested pulse signal joint point, a second input end of the AND gate is connected with the reference pulse signal joint point; the clock end of a counter is connected with a clock signal joint point, the enabling end of the counter is connected with the output end of the or gate, a zero clearing end of the counter is connected to the output end of the or gate after passing through an inverter; the input end of a second D trigger is connected with the output end of the counter, and the clock end of the second D trigger is connected with the output end of the AND gate. The circuit has the advantages of low efficacy, high measuring accuracy, high integrated level, and simple circuit.

Description

A kind of time synchronization error metering circuit based on the CPLD technology

Technical field

The utility model relates to a kind of error measure circuit, particularly relates to a kind of time synchronization error circuit.

Background technology

Along with progress of science and technology such as modern weapons equipment, navigation, communication, electric power, increasing engineering and scientific domain need time unification.Timing system is in the widespread use of a plurality of fields.Time synchronization error is a technical indicator the most key in the timing system.

The measurement of traditional time synchronization error is to utilize the GPS receiving equipment to produce reference pulse signal, utilizes high precision oscillograph and measured pulse signal to compare then, and the measurement synchronization error amount utilizes high-resolution counter to carry out the measured pulse signal-count.

Traditional measuring method needs a plurality of high precision measurement instruments, comparison signal source equipment, and on the one hand, cost is higher; On the other hand, a plurality of equipment, outfield use, carry all not too convenient.

Therefore, in actual field is measured, join examination, testing apparatus quantity for reducing the scene, the input of comprehensive deadline integrated system, output signal detect, and need integrated, integrated, the portable time reference tester of development.

Summary of the invention

Problem to be solved in the utility model is: a kind of time synchronization error metering circuit based on CPLD (CPLD) technology is provided, this metering circuit can be applied in the time reference tester of above-mentioned required development, the measuring accuracy height, low in energy consumption.

The technical scheme that the utility model adopted is: or the door first input end link to each other with the reference pulse signal tie point, or second input end link to each other with measured pulse signal tie point; Link to each other with measured pulse signal tie point with the first input end of door, link to each other with the reference pulse signal tie point with second input end of door; The clock end of counter links to each other with the clock signal tie point, the Enable Pin of counter with or the output terminal of door link to each other, the clear terminal of counter through be connected to behind the phase inverter or output terminal; The input end of second d type flip flop links to each other with the output terminal of counter, and the clock end of second d type flip flop is with linking to each other with the output terminal of door.

The utility model adopts the high-speed CPLD technology of low-power consumption, the standard high-speed clock signal that utilizes system to provide is counted, suppose that clock signal adopts 50MHz that counter is counted, measuring accuracy reaches 20ns, adopts the CPLD device of present more speed then can reach higher measuring accuracy.Utilize a d type flip flop can also judge that the measured pulse signal is in advance or the hysteresis reference pulse signal.Foregoing circuit is all realized at the piece of CPLD chip internal, the integrated level height, and low in energy consumption, circuit is simple.

Description of drawings

Fig. 1 is the circuit structure schematic diagram of embodiment.

Embodiment

Below in conjunction with accompanying drawing the utility model is specified, but do not limit the utility model.

Embodiment as shown in Figure 1, it is the time synchronization error metering circuit that is used for the time reference tester based on the CPLD technology, comprise reference pulse signal tie point 1, measured pulse signal tie point 2, clock signal tie point 3 or door 11, with door 12, phase inverter 13, counter 14, first d type flip flop 15, second d type flip flop 16, the figure place of counter 14 is 20 or more high-order.

Adopting 20 with counter 14 is example, and the annexation between these elements is: or the first input end 111 of door 11 links to each other with reference pulse

signal tie point

1, or 11 second input end 112 links to each other with measured pulse signal tie point 2; Link to each other with measured pulse signal tie point 2 with the first input end 121 of door 12, link to each other with reference pulse signal tie point 1 with second input end 122 of door 12; The clock end of counter 14 (the clock end on the counter) links to each other with clock signal tie point 3, the Enable Pin of counter 14 (cnt_er) with or door 11 output terminal 113 link to each other, the clear terminal of counter 14 (sclr) is through being connected to behind the

phase inverter

13 or 11 output terminal 113; The output terminal of the input end of second d type flip flop 16 (data[19..0]) and counter 14 (q[19..0 on the counter] end) link to each other, the clock end of second d type flip flop 16 (the clock end on second d type flip flop) is same to link to each other with the output terminal 123 of door 12.The output terminal of second d type flip flop 16 (q[19..0 on second d type flip flop]) output 20 bit data.

This circuit can comprise that also the input end (D) of first d type flip flop, 15, the first d type flip flops 15 links to each other with reference pulse signal tie point 1, and the clock end of first d type flip flop 15 (the clock end on first d type flip flop) links to each other with measured pulse signal tie point 2.The output terminal of first d type flip flop 15 is Q.So just can judge that the measured pulse signal is in advance or the hysteresis reference pulse signal.

The principle of work of foregoing circuit is: by reference pulse signal tie point 1 input reference pulse signal, by measured pulse signal tie point 2 input measured pulse signals, this circuit can be measured the difference between the corresponding rising edge of two pulse signals.Any high level of two pulse signals comes then, or door 11 output terminal 113 be high level, the counting beginning, and counter 14 begins the standard clock signal of being imported by clock signal tie point 3 that system provides is counted; Or door 11 output terminal 113 be low level, passes through phase inverter 13 and becomes high level, counter 14 zero clearings in this time after anti-phase.Rising edge with door 12 output terminal 123 signals when two pulse signals just are high level simultaneously arrives, till when the count value of counter 14 is delivered to the output terminal of second d type flip flop 16 by the input end of second d type flip flop 16 and remained to the arrival of rising edge of output terminal 123 signals of next and door 12, can obtain the synchronous error value by this count value.

If this circuit comprises first d type flip flop 15, the signal of the input end D of first d type flip flop 15 is delivered to the output terminal Q of first d type flip flop 15 when the signal rising edge of measured pulse signal tie point 2 arrives.The output signal of this output terminal Q is as the sign bit of counter 14 count values: when this output signal is that high level is represented measured pulse signal lag reference pulse signal; When this output signal is that low level is represented the leading reference pulse signal of measured pulse signal.

Claims

1, a kind of time synchronization error metering circuit based on the CPLD technology, it is characterized in that: or the first input end (111) of door (11) links to each other with reference pulse signal tie point (1), or second input end (112) of (11) links to each other with measured pulse signal tie point (2); Link to each other with measured pulse signal tie point (2) with the first input end (121) of door (12), link to each other with reference pulse signal tie point (1) with second input end (122) of door (12); The clock end of counter (14) links to each other with clock signal tie point (3), the Enable Pin of counter (14) with or the output terminal (113) of door (11) link to each other, the clear terminal of counter (14) is connected to after through phase inverter (13) or the output terminal (113) of (11); The input end of second d type flip flop (16) links to each other with the output terminal of counter (14), and the clock end of second d type flip flop (16) is with linking to each other with the output terminal (123) of door (12).

2, the time synchronization error metering circuit based on the CPLD technology as claimed in claim 1, it is characterized in that: it also comprises first d type flip flop (15), the input end of first d type flip flop (15) links to each other with reference pulse signal tie point (1), and the clock end of first d type flip flop (15) links to each other with measured pulse signal tie point (2).

3, the time synchronization error metering circuit based on the CPLD technology as claimed in claim 1 or 2 is characterized in that: described counter (14) adopts 20 or more high-order.