CN200962621Y - Image integrated circuit and its image processing device - Google Patents
Image integrated circuit and its image processing device Download PDFInfo
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- CN200962621Y CN200962621Y CN 200620139031 CN200620139031U CN200962621Y CN 200962621 Y CN200962621 Y CN 200962621Y CN 200620139031 CN200620139031 CN 200620139031 CN 200620139031 U CN200620139031 U CN 200620139031U CN 200962621 Y CN200962621 Y CN 200962621Y
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Abstract
An image integrated circuit and image processing device for processing and displaying a plurality of images, which is connected with an image play device comprises a processor, an image absorbing unit, a watermark producing unit, a codec and an image output unit, or the like. The image absorbing unit responds a signal of the processor to receive a digital image signal and produce a processing signal. The watermark producing unit responds the signal of the processor to receive the processing signal and embed a watermark into the corresponding image of the processing signal to produce an integrated signal. The codec responds the signal of the processor to receive and compress the integrated signal to produce a compressing signal. The image output unit responds the signal of the processor to export the compressing signal to the image play device.
Description
Technical field
The utility model relates to a kind of image integrated circuit and image processing apparatus thereof, particularly a kind of image integrated circuit and image processing apparatus thereof that is used for the picture signal processing.
Background technology
In the epoch of this scientific and technological progress, image correlation technique development rapidly, so image display device is and people's closely bound up commodity of living.Yet generally only can show that the image display device of single picture can't cater to the demand that obtains more information at short notice, the image display device that therefore has PIP or many divided frames arises at the historic moment.
The known control and treatment circuit of handling the image display device of a plurality of pictures is made up of a plurality of integrated circuits mostly, for example desire is handled and is comprised the input of a plurality of digital video signals and generate corresponding image, need processor, video I/O mouth unit, coding decoder, integrated driving electronics (integrated drive electronics, IDE) multiple integrated circuit compounding practice such as controller, because such its circuit layout area of combination is big, not only cost is too high, and the volume of its product also can't meet modern compact requirement.
In view of the foregoing, provide a kind of single IC for both, be the industry problem demanding prompt solution to handle the image integrated circuit and the image processing apparatus thereof of multiple picture signal.
Summary of the invention
The purpose of this utility model is to provide a kind of image integrated circuit, and it is connected to image playing device.The image integrated circuit comprises processor, image capture unit, watermark generation unit, coding decoder (codec) and image output unit.The signal of image capture cell response processor and receive data image signal and produce processing signals.The signal of watermark generation unit answer processor and receive processing signals, and the image that watermark is embedded the alignment processing signal is to produce integrated signal.The signal of coding decoder answer processor and receive and compress integrated signal to produce compressed signal.The signal of image output unit answer processor exports compressed signal to image playing device.
Another purpose of the present utility model is to provide a kind of image processing apparatus, is connected to image playing device, and image processing apparatus comprises the first image integrated circuit and the second image integrated circuit.The first image integrated circuit and the second image integrated circuit comprise processor, image capture unit, watermark generation unit, coding decoder and image output unit respectively.The image capture unit comprises the first input end and second input, the signal of answer processor and receive a data image signal and produce processing signals from first input end.The signal of watermark generation unit answer processor and receive processing signals, and watermark signal embedded processing signals to produce integrated signal.The signal of coding decoder answer processor and receive and compress integrated signal to produce compressed signal.The image output unit comprises first output and second output, and the signal of image output unit answer processor exports compressed signal to image playing device from first output.Wherein, second output of the image output unit of the first image integrated circuit is connected to second input of the image capture unit of the second image integrated circuit, and the compressed signal of the first image integrated circuit inputs to the second image integrated circuit.
The utility model only uses single IC for both just image can be carried out multinomial processing.Therefore the utility model can reduce circuit layout area, dwindles the application product volume, and simplifies and make or operation procedure.
Behind the execution mode of reference accompanying drawing and description subsequently, the person of ordinary skill in the field just can understand other purpose of the present utility model, and technological means of the present utility model and execution mode.
Description of drawings
Fig. 1 is the schematic diagram of first embodiment of image integrated circuit of the present utility model;
Fig. 2 is the schematic diagram of second embodiment of image integrated circuit of the present utility model; And
Fig. 3 is the schematic diagram of the embodiment of image processing apparatus of the present utility model.
The main element description of symbols
1: image integrated circuit 103: image playing device
101: memory 104: processing signals
102: data image signal 105: processor
106: 122: the first signals of integrated signal
107: image capture unit 124: secondary signal
108: 126: the three signals of judging result signal
109: 128: the four signals of watermark generation unit
110: 130: the five signals of compressed signal
111: 132: the six signals of image identification unit
113: 134: the seven signals of coding decoder
115: 136: the eight signals of memory control unit
117: 138: the nine signals of image output unit
118: 140: the ten signals of circuit
119: 142: the 11 signals of circuit
121: 144: the ten binary signals of bus
123: video encoder 2: the image integrated circuit
125: 225: the first buses of ciphering unit
127: 201: the second buses of hard disk
129: integrated driving electronic controller 203: bridge
131: peripheral controller interface bus 205: the twin wire control bus
133: peripheral controller interface unit 207: serial circumference interface
135: Serial Advanced Technology Attachment interface 209: the IrDA interface
137: Serial Advanced Technology Attachment controller 211: store card
139: USB (universal serial bus) port 213: general I/O mouth
141: USB unit 215: sound interface
143: Ethernet physical layer 217: stereo audio codec interface
145: Ethernet medium access control layer 219: keyboard and mouse interface
221: universal asynchronous reception and forwarder interface 117 (a), 107 (b): image output unit
223: interrupt control unit 301 (a), 301 (b): first input end
3: image processing is adorned 303 (a), 303 (b): second input
31: the first image integrated circuits 305 (a), 305 (b): first output
33: the second image integrated circuits 307 (a), 307 (b): second output
107 (a), 107 (b): image capture unit 302,304: data image signal
Embodiment
First embodiment of the present utility model for a kind of image integrated circuit 1, be used to handle at least one data image signal, and the data image signal after will handling outputs on the image playing device 103 as shown in Figure 1.
Image integrated circuit 1 is electrically connected to memory 101 and image playing device 103, and comprises processor 105, image capture unit 107, watermark generation unit 109, image identification unit 111, coding decoder 113, memory control unit 115 and image output unit 117.Processor 105 becomes other unit of circuit 1 by circuit 119 and bus 121 output signals with the control chart image set.After image capture unit 107 receives first signal of being exported by processor 105 via line 119 and bus 121 122, respond first signal 122 and receive at least one data image signal 102, and produce processing signals 104, processing signals 104 is transferred into bus 121.In this embodiment, bus 121 be advanced efficient bus (advanced high-performance bus, AHB).
After watermark generation unit 109 receives the secondary signal of being exported by processor 105 via line 119 and bus 121 124, response secondary signal 124 is 107 reception processing signals 104 from the image capture unit, and watermark embedded the image of alignment processing signal, to produce integrated signal 106.Watermark can be considered a kind of noise data, embeds the ad-hoc location in the signal of representing former data, to prevent processing without permission, such as conversion, filtration, compression and the editor etc. between numeral and simulation.Except that the described image of present embodiment, watermark also can add in the data of forms such as text formatting, still image form, moving image format, audio format; And but watermark also can be divided into naked eyes and inspects and two kinds that can't naked eyes inspect.
After coding decoder 113 receives the 4th signal of being exported by processor 105 via line 119 and bus 121 128, respond the 4th signal 128 from bus 121 receive and compression integrated signal or judging result signal to produce compressed signal 110, its compressed format can be JPEG (joint photographic experts group) (jointphotographic experts group, JPEG) reference format, MPEG-3 form, MPEG-4 form or H.264 reference format etc.
After memory control unit 115 received the 5th signal of being exported by processor 105 via line 119 and bus 121 130, the compressed signal 110 that coding decoder 113 is produced was stored to memory 101, so compressed signal 110 just is stored in the memory 101.Memory 101 can be static memory (static memory) or Double Data Rate (double data rate, DDR) memory.If memory 101 is a static memory, its corresponding memory control unit 115 is the static memory controller; If memory 101 is a double data rate memory, its corresponding memory control unit 115 is the double data rate memory controller.
When compressed signal 110 need be ingested out, processor 105 via line 119 and bus 121 transmit the 6th signal 132 to image output unit 117, image output unit 117 just responds the 6th signal 132 from memory 101 picked-up compressed signals 110, and after this compressed signal 110 decompressed, further encoded processing and export image playing device 103 to show the picture after data image signal 102 adds watermarks.Wherein, image output unit 117 also can export the compressed signal 110 that decompresses to the next stage integrated circuit with circuit 118 according to demand.
Image integrated circuit 1 also comprises video encoder 123, and it is between this image output unit 117 and image playing device 103, and the compressed signal after image output unit 117 will decompress by video encoder 123 exports image playing device 103 to.Video encoder 123 codings are from the compressed signal 110 of image output unit 117 picked-ups, and the compressed signal after will encoding exports image playing device 103 to.Video encoder 123 can be Video Graphics Array encoder or television encoder.When video encoder 123 was the Video Graphics Array encoder, image integrated circuit 1 can directly produce the signal of Video Graphics Array, and corresponding image playing device 103 is Video Graphics Array display, projector or LCD.When video encoder 123 was television encoder, image integrated circuit 1 can directly produce TV signal, and corresponding image playing device 103 is TV or projector.
Image integrated circuit 1 also comprises ciphering unit 125.After ciphering unit 125 receives the 7th signal of being exported by processor 105 via line 119 and bus 121 134, respond the 7th signal 134 and use key with ciphered compressed signal 110.Ciphering unit 125 can be data encryption standard (data encryptionstandard, DES) unit, triple DES (triple data encryption standard, the 3DES) unit of unit or other encryption standard.
Image integrated circuit 1 also is connected to hard disk 127, and image integrated circuit 1 also comprises integrated driving electronics (integrated drive electronics, IDE) controller 129, it is stored to hard disk 127 with compressed signal 110 after receiving the 8th signal of being exported by processor 105 via line 119 and bus 121 136.Because hard disk 127 can store lot of data, so compressed signal 110 can be preserved for a long time, reads out from hard disk 127 when treating need use in the future again, plays or further handles.
Image integrated circuit 1 also is connected to peripheral controller interface bus 131, and image integrated circuit 1 also comprises peripheral controller interface unit (peripheral controller interface, PCI) 133, after it receives the 9th signal of being exported by processor 105 via line 119 and bus 121 138, export compressed signal 110 to peripheral controller interface bus 131, and peripheral controller interface bus 131 is the standard interface of computer data transmission, and computer shows or further processing thereby compressed signal 110 can be sent to.
Image integrated circuit 1 also is connected to Serial Advanced Technology Attachment (serial advancedtechnology attachment, SATA) interface 135, and image integrated circuit 1 also comprises Serial Advanced Technology Attachment controller 137, it exports compressed signal 110 to Serial Advanced Technology Attachment interface 135 after receiving the tenth signal of being exported by processor 105 via line 119 and bus 121 140.Serial Advanced Technology Attachment interface 135 also is a kind of interface that can be connected with main frame or multimedia video and audio device, thereby compressed signal 110 can be sent to computer or multimedia video and audio device shows or further processing.
Image integrated circuit 1 also is connected to USB (universal serial bus, USB) port one 39, and image integrated circuit 1 also comprises USB unit 141, it exports compressed signal 110 to USB (universal serial bus) port 139 after receiving the 11 signal of being exported by processor 105 via line 119 and bus 121 142.USB (universal serial bus) port 139 also is a kind of interface that can be connected with main frame, and computer shows or further processing thereby compressed signal 110 can be sent to.
Image integrated circuit 1 also is connected to Ethernet physical layer (physical layer) 143, and image integrated circuit 1 also comprises Ethernet medium access control layer (medium access controllayer) 145, after it receives the tenth binary signal of being exported by processor 105 via line 119 and bus 121 144, export compressed signal to Ethernet physical layer 143, thereby compressed signal can be sent to network.
Second embodiment of the present utility model as shown in Figure 2, the image integrated circuit 2 of this embodiment also is connected to memory 101 and image playing device 103, comprise processor 105, image capture unit 107, watermark generation unit 109, image identification unit 111, coding decoder 113, memory control unit 115 and image output unit 117 equally, its function is identical with the corresponding element of first embodiment, so do not give unnecessary details.In addition, first bus 225 that image integrated circuit 2 comprises is identical with the bus 121 among first embodiment, so also do not give unnecessary details at this.
Be that with image integrated circuit 1 difference image integrated circuit 2 also comprises second bus 201 and bridge 203, wherein second bus 201 is Advanced Peripheral Bus (advanced peripheralbus, APB), and bridge 203 is the AHB-APB bridger, in order to connect first bus 225 and second bus 201.Second bus 201 is connected to twin wire control bus (I
2C bus) 205 serial circumference interface (serial peripheral interface,, SPI) 207, IrDA (IrDA) interface 209, store card (storage card) interface 211, general I/O mouth (GPIO port) 213, sound interface (audio I/F, can be inter IC sound, I
2S) 215, stereo audio codec (stereoaudio codec) interface 217, keyboard and mouse interface 219, universal asynchronous reception and conveyer (UART) interface 221 and interrupt control unit 223.Second bus 201 can be transmitted signal with first bus 225 by bridge 203, so processor 105, image capture unit 107, watermark generation unit 109, image identification unit 111, coding decoder 113, any signal that memory control unit 115 and image output unit 117 are produced can be via above-mentioned interface 205,207,209,211,213,215,217,219,221,223 send out, and the user also can pass through above-mentioned interface 205,207,209,211,213,215,217,219,221,223 input to image integrated circuit 2 with control signal or data.
The utility model also provides a kind of image processing apparatus, embodiment as shown in Figure 3, this image processing apparatus 3 is in order to after a plurality of data image signal processing controls, be shown on the displays such as LCD, TV, monitor, projector, make the single display device show a plurality of divided frames simultaneously.
Image processing apparatus 3 comprises the first image integrated circuit 31 and the second image integrated circuit 33.The inner member of the first image integrated circuit 31 and the second image integrated circuit 33 is identical with first embodiment, second embodiment, so do not give unnecessary details.The image capture unit 107 (a) of the first image integrated circuit 31 also comprises the first input end 301 (a) and second input 303 (a), and the image capture unit 107 (b) of the second image integrated circuit 33 also comprises the first input end 301 (b) and second input 303 (b).First input end 301 (a) and first input end 301 (b) are in order to receive at least one data image signal 302,304, and producing foregoing compressed signal, second input 303 (b) is connected to the image output unit 117 (a) of previous stage image integrated circuit 31.The image output unit 117 (a) of the first image integrated circuit 31 also comprises first output 305 (a) and second output 307 (a), the image output unit 107 (b) of the second image integrated circuit 33 also comprises first output 305 (b) and second output 307 (b), first output 305 (b) exports compressed signal to second input 303 (b) that image playing device 103, the second outputs 307 (a) then are connected to the image capture unit 107 (b) of next stage image integrated circuit 33.Concerning this embodiment, second output 307 (a) of the image output unit 117 (a) of the first image integrated circuit 31 is connected to second input 303 (b) of the image capture unit 107 (b) of the second image integrated circuit 33, and therefore the compressed signal of the first image integrated circuit 31 can input to the second image integrated circuit 33.
If the first image integrated circuit 31 and the second image integrated circuit 33 can be handled four data image signals respectively, then first output 305 (b) of the image output unit 117 (b) of the second image integrated circuit 33 and second output 307 (b) are distinguished exportable eight pictures, four data image signals wherein from the first input end 301 (a) of the image capture unit 107 (a) of the first image integrated circuit 31, four data image signals from the first input end 301 (b) of the image capture unit 107 (b) of the second image integrated circuit 33.The second image integrated circuit 33 can be simultaneously displayed on these eight pictures on the image playing device by its first output 305 (b).
Though this embodiment illustrates with the image processing apparatus that comprises two image integrated circuits, but the person of ordinary skill in the field can release the execution mode of the image processing apparatus that comprises two above image integrated circuits easily, the image processing apparatus that for example comprises four image integrated circuits, such image processing apparatus just can show 16 pictures simultaneously.
Because image integrated circuit 1, image integrated circuit 2 and image processing apparatus 3 can receive at least one data image signal, therefore can handle and show at least one picture simultaneously.Known technology must use multiple arrangement when handling a plurality of picture signal, so cost height and volume are big.Image integrated circuit of the present utility model is incorporated into the function of known a plurality of integrated circuit (IC) chip on the single IC for both chip, only uses single IC for both just image can be carried out multinomial processing.Therefore the utility model has reduced the area of circuit layout, and then reaches the purpose of simplifying manufacturing or operation procedure, reduce cost and dwindling small product size.
In sum, though the utility model adopts previous embodiment to describe, but be not in order to limit execution mode of the present utility model, any person of ordinary skill in the field, in the content and corresponding techniques scope thereof that does not break away from spirit and claim of the present utility model and limited, when making various changes and modification.
Claims (40)
1. an image integrated circuit is connected to image playing device, it is characterized in that comprising:
Processor;
The image capture unit responds the signal of this processor and receives data image signal and produce processing signals;
The watermark generation unit responds the signal of this processor and receives this processing signals, and watermark is embedded image that should processing signals to produce integrated signal;
Coding decoder responds the signal of this processor and receives and compress this integrated signal to produce compressed signal; And
The image output unit, the signal that responds this processor exports this compressed signal to this image playing device.
2. image integrated circuit according to claim 1 is characterized in that also comprising image identification unit, responds the signal of this processor and discerns this image and produce judged result, and this image identification unit also is sent to this processor with this judged result.
3. image integrated circuit according to claim 1, it is characterized in that also comprising video encoder, between this image output unit and this image playing device, coding is from this compressed signal of this image output unit, and the back compressed signal of should encoding exports this image playing device to.
4. image integrated circuit according to claim 3 it is characterized in that this video encoder is the Video Graphics Array encoder, and this image playing device is the Video Graphics Array display.
5. image integrated circuit according to claim 3 it is characterized in that this video encoder is the Video Graphics Array encoder, and this image playing device is a LCD.
6. image integrated circuit according to claim 3 it is characterized in that this video encoder is a television encoder, and this image playing device is a TV.
7. image integrated circuit according to claim 1 is characterized in that also being connected to memory, and this image integrated circuit also comprises Memory Controller, and the signal that responds this processor is stored to this memory with this compressed signal.
8. image integrated circuit according to claim 7 it is characterized in that this memory is a static memory, and this Memory Controller is the static memory controller.
9. image integrated circuit according to claim 7 it is characterized in that this memory is a double data rate memory, and this Memory Controller is the double data rate memory controller.
10. image integrated circuit according to claim 1 is characterized in that also being connected to hard disk, and this image integrated circuit also comprises integrated driving electronic controller, and the signal that responds this processor is stored to this hard disk with this compressed signal.
11. image integrated circuit according to claim 1, it is characterized in that also being connected to the peripheral controller interface bus, this image integrated circuit also comprises the peripheral controller interface unit, and the signal that responds this processor exports this compressed signal to this peripheral controller interface bus.
12. image integrated circuit according to claim 1, it is characterized in that also being connected to the Serial Advanced Technology Attachment interface, this image integrated circuit also comprises the Serial Advanced Technology Attachment controller, and the signal that responds this processor exports this compressed signal to this Serial Advanced Technology Attachment interface.
13. image integrated circuit according to claim 1, it is characterized in that also being connected to USB (universal serial bus) port, this image integrated circuit also comprises the USB unit, and the signal that responds this processor exports this compressed signal to this USB (universal serial bus) port.
14. image integrated circuit according to claim 1, it is characterized in that also being connected to the Ethernet physical layer, this image integrated circuit also comprises the Ethernet medium access control layer, and the signal that responds this processor exports this compressed signal to this Ethernet physical layer.
15. image integrated circuit according to claim 1 is characterized in that also comprising ciphering unit, responds the signal of this processor and encrypts this compressed signal.
16. image integrated circuit according to claim 15 is characterized in that this ciphering unit is a kind of in data encryption standard unit and the triple DES unit.
17. image integrated circuit according to claim 1 is characterized in that this animation compression standard coding decoder compresses with form H.264.
18. image integrated circuit according to claim 1 is characterized in that this animation compression standard coding decoder compresses with the MPEG-4 form.
19. image integrated circuit according to claim 1 is characterized in that this animation compression standard coding decoder compresses with jpeg format.
20. image integrated circuit according to claim 1 is characterized in that also comprising advanced efficient bus, in order to transmit this signal and this compressed signal.
21. an image processing apparatus is connected to image playing device, it is characterized in that this image processing apparatus comprises the first image integrated circuit and the second image integrated circuit, this first image integrated circuit and this second image integrated circuit comprise respectively:
Processor;
The image capture unit comprises the first input end and second input, the signal of this this processor of image capture cell response and certainly this first input end receive a data image signal and produce processing signals;
The watermark generation unit responds the signal of this processor and receives this processing signals, and watermark signal is embedded this processing signals to produce integrated signal;
Coding decoder responds the signal of this processor and receives and compress this integrated signal to produce compressed signal; And
The image output unit comprises first output and second output, and the signal that this image output unit responds this processor exports this compressed signal to this image playing device from this first output;
Wherein, this second output of this image output unit of this first image integrated circuit is connected to this second input of this image capture unit of this second image integrated circuit, and this compressed signal of this first image integrated circuit inputs to this second image integrated circuit.
22. image processing apparatus according to claim 21, it is characterized in that respectively this image integrated circuit also comprises image identification unit, respond the signal of this processor and discern this image and produce judged result, this image identification unit also is sent to this processor with this judged result.
23. image processing apparatus according to claim 21, it is characterized in that this second image integrated circuit also comprises video encoder, between this image output unit and this image playing device, in order to coding this compressed signal from this image output unit, and the back compressed signal of should encoding exports this image playing device to.
24. image processing apparatus according to claim 23 it is characterized in that this video encoder is the Video Graphics Array encoder, and this image playing device is the Video Graphics Array display.
25. image processing apparatus according to claim 23 it is characterized in that this video encoder is the Video Graphics Array encoder, and this image playing device is a LCD.
26. image processing apparatus according to claim 23 it is characterized in that this video encoder is a television encoder, and this image playing device is a TV.
27. image processing apparatus according to claim 21, it is characterized in that also being connected to memory, it is characterized in that this first and second image integrated circuit also comprises Memory Controller respectively, the signal that responds this processor is stored to this memory with this compressed signal.
28. image processing apparatus according to claim 27 it is characterized in that this memory is a static memory, and this Memory Controller is the static memory controller.
29. image processing apparatus according to claim 27 it is characterized in that this memory is a double data rate memory, and this Memory Controller is the double data rate memory controller.
30. image processing apparatus according to claim 21 is characterized in that also being connected to hard disk, this first and second image integrated circuit also comprises integrated driving electronic controller respectively, and the signal that responds this processor is stored to this hard disk with this compressed signal.
31. image processing apparatus according to claim 21, it is characterized in that also being connected to the peripheral controller interface bus, this first and second image integrated circuit also comprises the peripheral controller interface unit respectively, and the signal that responds this processor exports this compressed signal to this peripheral controller interface bus.
32. image processing apparatus according to claim 21, it is characterized in that also being connected to the Serial Advanced Technology Attachment interface, this first and second image integrated circuit also comprises the Serial Advanced Technology Attachment controller respectively, and the signal that responds this processor exports this compressed signal to this Serial Advanced Technology Attachment interface.
33. image processing apparatus according to claim 21, it is characterized in that also being connected to USB (universal serial bus) port, this first and second image integrated circuit also comprises the USB unit respectively, and the signal that responds this processor exports this compressed signal to this USB (universal serial bus) port.
34. image processing apparatus according to claim 21, it is characterized in that also being connected to the Ethernet physical layer, this first and second image integrated circuit also comprises the Ethernet medium access control layer respectively, and the signal that responds this processor exports this compressed signal to this Ethernet physical layer.
35. image processing apparatus according to claim 21 is characterized in that this first and second image integrated circuit also comprises ciphering unit respectively, responds the signal of this processor and encrypts this compressed signal.
36. image processing apparatus according to claim 35 is characterized in that this ciphering unit is a kind of in data encryption standard unit and the triple DES unit.
37. image processing apparatus according to claim 21 is characterized in that this animation compression standard coding decoder compresses with form H.264.
38. image processing apparatus according to claim 21 is characterized in that this animation compression standard coding decoder compresses with the MPEG-4 form.
39. image processing apparatus according to claim 21 is characterized in that this animation compression standard coding decoder compresses with jpeg format.
40. image processing apparatus according to claim 21 is characterized in that this first and second image integrated circuit also comprises advanced efficient bus respectively, in order to transmit this signal and this compressed signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620139031 CN200962621Y (en) | 2006-08-31 | 2006-08-31 | Image integrated circuit and its image processing device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620139031 CN200962621Y (en) | 2006-08-31 | 2006-08-31 | Image integrated circuit and its image processing device |
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| CN200962621Y true CN200962621Y (en) | 2007-10-17 |
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