CN1983225A - Device and method for transmitting data in asynchronous clock domain - Google Patents
Device and method for transmitting data in asynchronous clock domain Download PDFInfo
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- CN1983225A CN1983225A CN 200610078321 CN200610078321A CN1983225A CN 1983225 A CN1983225 A CN 1983225A CN 200610078321 CN200610078321 CN 200610078321 CN 200610078321 A CN200610078321 A CN 200610078321A CN 1983225 A CN1983225 A CN 1983225A
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Abstract
A method for transmitting data in asynchronous clock domain includes storing data into storage unit and generating a data ready indication signal being sent to receiving party by sending party when energized writing signal is valid, generating data indication signal by receiving party when edge of said indication signal is detected, regulating phase of the first counter according to said indication signal and fetching data from storage unit when phase of the first counter is on preset phase.
Description
Technical field
The present invention relates to technical field of data transmission, particularly a kind of in asynchronous clock domain apparatus for transmitting data and method thereof.
Background technology
In most systems, serial mode is adopted in the transmission of data between different veneers, and is asynchronous clock between the different veneer.But, even the asynchronous clock of different veneers is homologies, but because they are to obtain through different phaselocked loop (PLL) or different approach, clock signal shake (Jitter) separately is different, and all can there be frequency difference in they in any one short time, just be synchronized on the clock source from long statistics, therefore two clocks of different veneers phase drift can occur within a certain period of time, and the maximal value of phase drift depends on the quality of parts such as clock source, PLL.
Most at present systems all are to use push-up storage (FIFO) to be implemented in Data transmission between two clock zones.Typical FIFO is the storer of a twoport visit, and as shown in Figure 1, FIFO comprises storage unit, write address counter, read address counter, write address gray code generator, reads address gray code generator and clear detection and overflows the detection logic.Wherein storage unit is used for data cachedly, can adopt random-access memory (ram) or register to realize, its degree of depth has determined maximum clock shake, phase drift and the frequency jitter that FIFO can tolerate; Write address counter and read address counter are used for producing the address of storage unit access, and they are cycle counter, and promptly the address count down to behind the maximum address of storage unit since 0 counting again; Write address gray code generator and read the address gray code generator, when whenever writing data or reading data just with the write address Gray code with read the address Gray code and increase by 1, and with the write address Gray code or read address Gray code input clear detection and overflow the detection logic; Clear detection and overflow and detect logical foundation write address Gray code and read the address Gray code and imminent read-write operation judges whether FIFO has taken place to be cleared or to have overflowed, send and empty indication or overflow the signal of indication, the read-write control end is then made corresponding operation according to these signals, as stops to write or stop to read.
FIFO can pass to data stabilization ground on another clock zone from a clock zone when frequency generation deviation or read-write shake of clock and phase drift.But when arbitrary port takes place to cause reading, writing address generation saltus step unusually in the reading and writing port of FIFO, FIFO can not detect, also can not adjust the transmission delay of data, so FIFO can not satisfy the application scenario to transmission delay error sensitivity at FIFO.
Summary of the invention
In view of this, the present invention proposes a kind ofly in the asynchronous clock domain apparatus for transmitting data, its purpose is, realizes data between asynchronous clock domain in the stable transfer, effectively the control transmission delay error.Another object of the present invention is to provide a kind of method in asynchronous clock domain transmission data.
According to above-mentioned purpose, the invention provides a kind ofly in the asynchronous clock domain apparatus for transmitting data, this device comprises: storage unit is used for data cached; The write data end, be used for write enable signal when effective with metadata cache in storage unit; Data ready indicator signal generation circuit is used for producing the data ready indicator signal when effective writing enable signal; Along testing circuit, be used to detect the edge of the data ready indicator signal that data ready indicator signal generation circuit produces, when detecting the edge of described data ready indicator signal, produce the data indicator signal; The phase place monitoring and the data acquisition phase generator that comprise first counter are used for adjusting according to described data indicator signal the phase place of first counter, and produce the data acquisition enable signal when the phase place of first counter reaches predefined phase place; The read data end is used for data acquisition enable signal according to phase place monitoring and the generation of data acquisition phase generator from the storage unit reading of data; Wherein write data end, data ready indicator signal generation circuit working with the road clock zone, are operated in system works clock zone along testing circuit, phase place monitoring and data acquisition phase generator and read data end in data.
This device further comprises at data ready indicator signal generation circuit and along the signal delay circuit between the testing circuit, and input is described along testing circuit after being used for described data ready indicator signal latched at least two clock period.
Described signal delay circuit is made up of the d type flip flop of a plurality of polyphones.
Described data ready indicator signal generation circuit comprises first selector, second selector, d type flip flop and chronotron.Wherein, 1 input end of first selector is transfused to 0,0 input end and links to each other with the output terminal of described d type flip flop, and control end links to each other with the output terminal of described chronotron, and output terminal links to each other with 0 input end of second selector; 1 input end of second selector is transfused to 1,0 input end and is linked to each other with the output terminal of first selector, and control end is transfused to writes enable signal, and output terminal links to each other with the D input end of described d type flip flop; The D input end of described d type flip flop links to each other with the output terminal of second selector, and output terminal links to each other along 0 input end of testing circuit, first selector and the input end of described chronotron with described; The input end of described chronotron links to each other with the output terminal of described d type flip flop, and output terminal links to each other with the control end of first selector.
Described chronotron is made up of the d type flip flop of a plurality of polyphones, perhaps for waiting for the counter of a plurality of clock period output signals.
Described phase place monitoring and data acquisition phase generator further comprise third selector, the 4th selector switch, the 5th selector switch, first d type flip flop, second d type flip flop and second counter.Wherein, 1 input end of third selector is transfused to 1,0 input end and links to each other with the output terminal of first d type flip flop, and control end is transfused to described data indicator signal, and output terminal links to each other with the D input end of first d type flip flop; 1 input end of the 4th selector switch is transfused to described data indicator signal, and 0 input end is transfused to 0, and control end links to each other with the output terminal of first counter, and output terminal links to each other with the input end of the 5th selector switch; 1 input end of the 5th selector switch is transfused to described data indicator signal, and 0 input end links to each other with the output terminal of the 4th selector switch, and control end links to each other with the output terminal of first d type flip flop, and output terminal links to each other with the clear terminal of first counter; The D input end of first d type flip flop links to each other with the output terminal of third selector, and output terminal links to each other with 0 input end of third selector, the control end of the 5th selector switch and the Enable Pin of first counter; The D input end of second d type flip flop links to each other with the output terminal of first counter, and Enable Pin is transfused to described data indicator signal, and output terminal links to each other with the clear terminal of second counter; The clear terminal of first counter links to each other with the output terminal of the 5th selector switch, Enable Pin links to each other with the output terminal of first d type flip flop, output terminal links to each other with the control end of the 4th selector switch and the D input end of second d type flip flop, and the output terminal output data of first counter is gathered enable signal; The clear terminal of second counter links to each other with the output terminal of its output terminal and second d type flip flop, and Enable Pin is transfused to described data indicator signal, and output terminal links to each other with its clear terminal.
Described storage unit is Random Access Storage Unit or register.
The present invention also provides a kind of method in asynchronous clock domain transmission data, wherein transmit leg is positioned at data with the road clock zone, the take over party is positioned at the system works clock zone and comprises first counter, this method may further comprise the steps: the A. transmit leg is being write enable signal when effective, metadata cache in storage unit, is produced a data ready transport indicator simultaneously and sends to the take over party; B. the take over party produces the data indicator signal when detecting described data ready indicator signal edge; C. adjust the phase place of first counter according to described data indicator signal, and reach when setting phase place from the storage unit reading of data in the phase place of first counter.
Step B takes a step forward and comprises the step that described data ready indicator signal is latched an above clock period.
The step of adjusting the phase place of first counter according to described data indicator signal described in the step C comprises: whether the current phase place of first counter equaled its maximum phase when the judgment data indicator signal arrived, under situation about being not equal to, whether that judges described current phase place and maximum phase differs absolute value greater than 1, if greater than 1, then when next data indicator signal arrives, triggering described first counter counts again, if smaller or equal to 1, then under the situation that the difference of the current phase place of described first counter and its maximum phase remains unchanged when continuous a plurality of data indicator signals arrive, trigger described first counter and count again.
Reach in the phase place of first counter described in the step C that the step from the storage unit reading of data comprises when setting phase place: when the phase place of first counter arrives predefined phase place, produce the data acquisition enable signal; According to described data acquisition enable signal from the storage unit reading of data.
From technique scheme as can be seen, because the present invention adopts the mode of Data transmission indicator signal to realize the locking of asynchronous clock domain time data phase place, thereby realize data transmission stably between asynchronous clock domain, and the transmission delay error control in take over party's a clock period, so only need just can be reduced the absolute value of error effectively by the frequency that promotes take over party's system works clock.Compare with the FIFO of prior art, do not need complicated Gray code conversion and overflow zero clearing to judge, realize fairly simple.
Description of drawings
Fig. 1 is the structural representation of FIFO in the prior art.
The structural representation of Fig. 2 for installing in the embodiment of the invention.
Fig. 3 is the sequential chart of each signal in the embodiment of the invention.
Fig. 4 is the structural representation of phase place monitoring and data acquisition phase generator in the device of the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in more detail by the following examples.
With reference to figure 2, the device that the present invention adopts comprises write data end, storage unit, data ready indicator signal generation circuit, signal delay circuit, monitors and data acquisition phase generator and read data end along testing circuit, phase place.Wherein, the write data end of transmit leg and data ready indicator signal generation circuit working with road clock zone Clk_in, take over party's signal delay circuit, all are operated in system works clock zone Clk_sys along the monitoring of testing circuit, phase place and data acquisition phase generator and read data end in data.Introduce the structure and the function of each several part below respectively.
The write data end comprises a d type flip flop, writing enable signal Data_wt_en when effective, writes data Data_in, is about to metadata cache in storage unit.
Storage unit is RAM or register, is used for buffer memory from the data of write data end input, and reads these data of output by the read data end.
Data ready indicator signal generation circuit produces a data ready transport indicator Data_rdy according to writing enable signal Data_wt_en, and signal Data_rdy is used for notifying take over party's current data ready.In order to guarantee to collect the Data_rdy signal at the system works clock zone, the high-low level pulse width of Data_rdy signal must be greater than the width of a clock period in the system works clock zone.Referring to Fig. 3, the high-low level pulse width of the Data_rdy signal shown in Fig. 3 can guarantee like this that much larger than the width of the clock period of system works clock zone Clk_sys the module of system works clock zone can collect the Data_rdy signal.
Continuation is with reference to figure 2, and this data ready indicator signal generation circuit comprises the selector switch of two alternatives, a d type flip flop and a chronotron, and the selector switch of described two alternatives is first selector and second selector.Wherein, first selector and second selector are 0 or 1 according to the control signal of self control end respectively, correspondingly export the signal of 0 input end or 1 input end; D type flip flop is exported the input of D end when the input signal of Enable Pin (En end) is effective, when the En end does not have input signal, and the D end input signal when exporting a clock period; Chronotron was used for N clock period of Data_rdy signal delay, and it can be made of the d type flip flop of N polyphone, also can be realized by the counter of output input signal after waiting for N clock period.In data ready indicator signal generation circuit, 1 input end of first selector is transfused to 0,0 input end and links to each other with the output terminal of described d type flip flop, and control end links to each other with the output terminal of described chronotron, and output terminal links to each other with 0 input end of second selector; 1 input end of second selector is transfused to 1,0 input end and is linked to each other with the output terminal of first selector, and control end is transfused to writes enable signal, and output terminal links to each other with the D input end of described d type flip flop; The D input end of described d type flip flop links to each other with the output terminal of second selector, and output terminal links to each other along 0 input end of testing circuit, first selector and the input end of described chronotron with described; The input end of described chronotron links to each other with the output terminal of described d type flip flop, and output terminal links to each other with the control end of first selector.
In the course of the work, first selector 1 input end is transfused to 0,0 input end is transfused to the Data_rdy signal, and postpone the control of Data_rdy signal of N clock period to 0 input end output signal of second selector according to being counted device, 1 input end of second selector is 1, it is according to writing enable signal Data_wt_en to the d type flip flop output signal, and d type flip flop is exported the Data_rdy signal to 0 input end of signal delay circuit, first selector and as the counter of chronotron then.
Signal delay circuit is used for the Data_rdy signal latch is imported along testing circuit after two system works clock zone clock period at least again, and its purpose is to reduce as much as possible the probability that metastable state occurs.The signal delay circuit is here realized by a plurality of d type flip flops of polyphone.Signal delay circuit shown in Fig. 2 comprises 3 d type flip flops, and the Data_rdy signal latch after three clock period, is input to along testing circuit again.
Be used for that along testing circuit the Data_rdy signal is carried out the edge and detect, when detecting the rising edge of Data_rdy, be created in the data indicator signal Data_rdy_sync in system clock territory, the Data_rdy_sync signal has only a clock period width.Present embodiment adopts the method that current Data_rdy signal is compared with the Data_rdy signal before the clock period that the Data_rdy signal is carried out the edge and detects, be last d type flip flop of comparison signal delay circuit signal (a clock period Data_rdy signal before) and signal afterwards (current Data_rdy signal) before, obviously be 1 at current Data_rdy signal, a clock period Data_rdy signal before is 0 o'clock, the Data_rdy signal has rising edge, produce the Data_rdy_sync signal according to this rising edge then, and with monitoring of Data_rdy_sync signal input phase and data acquisition phase generator.
Phase place monitoring and data acquisition phase generator are used for transmission delay was controlled in the clock period, and produce a data collection enable signal Data_sample_en, and with Data_sample_en signal input read data end.As shown in Figure 3, the Data_sample_en signal that is produced is just in the centre position of former and later two change points of metadata cache register signal Data_tmp, makes shake between asynchronous clock domain and phase drift that the influence of data transmission is reached minimum like this.Shake between asynchronous clock domain and phase drift can equivalence for Clk_sys with respect to stablizing constant Clk_in move left and right, in the middle of obviously before and after data, changing constantly image data can obtain the most stable laser propagation effect.
As shown in Figure 4, phase place monitoring and data acquisition phase generator comprise selector switch and two d type flip flops of three alternatives of counter A (first counter), counter B (second counter) and auxiliary their realization functions, the selector switch of described three alternatives is third selector, the 4th selector switch and the 5th selector switch, and described two d type flip flops are first d type flip flop and second d type flip flop.Wherein, 1 input end of third selector is transfused to 1,0 input end and links to each other with the output terminal of first d type flip flop, and control end is transfused to described data indicator signal, and output terminal links to each other with the D input end of first d type flip flop; 1 input end of the 4th selector switch is transfused to described data indicator signal, and 0 input end is transfused to 0, and control end links to each other with the output terminal of counter A, and output terminal links to each other with the input end of the 5th selector switch; 1 input end of the 5th selector switch is transfused to described data indicator signal, and 0 input end links to each other with the output terminal of the 4th selector switch, and control end links to each other with the output terminal of first d type flip flop, and output terminal links to each other with the clear terminal of counter A; The D input end of first d type flip flop links to each other with the output terminal of third selector, and output terminal links to each other with 0 input end of third selector, the control end of the 5th selector switch and the Enable Pin of counter A; The D input end of second d type flip flop links to each other with the output terminal of counter A, and Enable Pin is transfused to described data indicator signal, and output terminal links to each other with the clear terminal of counter B; The clear terminal of counter A links to each other with the output terminal of the 5th selector switch, Enable Pin links to each other with the output terminal of first d type flip flop, output terminal links to each other with the control end of the 4th selector switch and the D input end of second d type flip flop, and the output terminal output data of counter A is gathered enable signal; The clear terminal of counter B links to each other with the output terminal of its output terminal and second d type flip flop, and Enable Pin is transfused to described data indicator signal, and output terminal links to each other with its clear terminal.
Counter A receives the Receive_start signal enabling counting that data begin according to indication when first Data_rdy_sync signal arrives, i.e. zero clearing begins counting.As shown in Figure 4, produce above-mentioned Receive_start signal by the third selector and first d type flip flop according to the Data_rdy_sync signal, third selector 1 input end is transfused to 1,0 input end is transfused to the Receive_start signal, control according to the Data_rdy_sync signal is imported corresponding signal to first d type flip flop, first d type flip flop output Receive_start signal, this Receive_start signal is imported 0 input end of above-mentioned third selector, the Enable Pin of counter A and the control end of the 5th selector switch respectively.
The count cycle PH_A of counter A equals to import the clock periodicity of cycle correspondence on the system works clock zone of data.Counter A also produces data acquisition enable signal Data_sample_en at a fixing phase place CON_A, wherein CON_A is that preliminary election is set, in order to satisfy the condition of foregoing Data_sample_en, preferably CON_A is set at about half of PH_A in the centre position of former and later two change points of Data_tmp.And counter A also in the logical expression (1), exports a Phase_error signal below satisfying, and the Phase_error signal is used for control with counter A zero clearing.
{(|Cnt_A-PH_A|＞1)‖(|Cnt_A-PH_A|＝1&&Cnt_B＞＝CON_B)}&&Data_rdy_sync＝＝1 (1)
In the logical expression (1), if | the absolute value of the phase differential of the count cycle PH_A of the phase place Cnt_A of counter A and counter A was greater than the situation of 1 clock period when Cnt_A-PH_A|＞1 was illustrated in the arrival of Data_rdy_sync signal.| Cnt_A-PH_A|=1﹠amp; ﹠amp; Cnt_B＞=CON_B represents that by counter B the absolute value of the phase differential of the count cycle PH_A of the phase place Cnt_A that arrives hour counter A at the Data_rdy_sync signal and counter A being equaled the continuous incident of 1 clock period counts, and the phase place Cnt_B of counter B is more than or equal to the situation of predefined CON_B.Data_rdy_sync==1 represents that current Data_rdy_sync signal is effective, when promptly Data_rdy_sync arrives.To sum up, one of above-mentioned two situations of generation and the effective situation of Data_rdy_sync are satisfied in logical expression (1) expression.
With reference to figure 4, the Phase_error signal is realized counter A zero clearing by the 4th selector switch and the 5th selector switch, 1 input end of the 4th selector switch is transfused to Data_rdy_sync, 0 input end is transfused to 0, imports corresponding signal according to the control of Phase_error to 1 input end of the 5th selector switch; 0 input end of the 5th selector switch is transfused to the Data_rdy_sync signal, and it is according to the control of the above-mentioned Receive_start signal clear terminal input control signal to counter A, and control counter A carries out zero clearing.The priority of the clear terminal clr of counter A is higher than Enable Pin en, and high level is effective.
Counter B, whether all the phase differential that is used for adding up in the time of given CON_B data sampling point the count cycle PH_A of the phase place Cnt_A of Data_rdy_sync arrival hour counter A and counter A all equal 1, and the value of counter A all equates each time.If then counter B constantly adds up, behind the CON_B that the value of counter B equals to set in advance, stop and with counter A zero clearing, this realizes by above-mentioned Phase_error signal; Be cleared if not counter B then, this realizes that by following reset signal promptly counter B exports a reset signal in the logical expression (2) below satisfying, and the clear terminal of this reset signal enter counter B is used for the zero clearing with counter B.The priority of the clear terminal clr of counter B is higher than Enable Pin en, and high level is effective.
Cnt_A！＝Cnt_A_back&&|Cnt_A-PH_A|＝＝1&&Data_rdy_sync＝＝1 (2)
=Cnt_A_back represents that current Data_rdy_sync arrives the different situation of phase place Cnt_A_back of phase place Cnt_A_ with the Data_rdy_sync arrival last time hour counter A of hour counter A; | Cnt_A-PH_A|==1 represents that the absolute value of phase differential that Data_rdy_sync arrives the count cycle PH_A of the phase place Cnt_A of hour counter A and counter A is 1 situation; Data_rdy_sync==1 represents that current Data_rdy_sync signal is effective, when promptly Data_rdy_sync arrives.To sum up, above-mentioned two situations and the effective situation of Data_rdy_sync are satisfied in above-mentioned logical expression (2) expression simultaneously.
The course of work of phase place monitoring and data acquisition phase generator is as follows:
Step 10, enabling counting when counter A arrives at first Data_rdy_sync.
Step 20, when each Data_rdy_sync signal of back arrived, counter A judged whether the phase place of self equals the count cycle maximal value, if then expression is normal, counter A continues counting; Otherwise execution in step 30.
Step 30, counter A judge self phase place and the absolute value of peaked difference of count cycle whether greater than a clock period, if greater than a clock period, show that then abnormality has taken place makes phase place that bigger saltus step arranged, the phase place of refresh counter A immediately when next Data_rdy_sync signal arrives so, be about to counter A zero clearing and count again, the interval of the Data_out of output data at this moment changes.If absolute values of both differences are smaller or equal to a clock period, execution in step 40, have this moment two kinds may: 1, the clock of two clock zones all is in normal condition, this error since shake cause; 2, skew has taken place in the phase place of at least one clock in two clock zones.
Step 40, whether the phase place of the counter A of correspondence all equals identical value when arriving with counter B (being above-mentioned CON_B data sampled point) the interior Data_rdy_sync that adds up continuous a period of time, change has taken place if then represent data phase, and when next Data_rdy_sync arrives the phase place of refresh counter A, i.e. zero clearing is counted again; Otherwise, counter B zero clearing execution in step 2 is restarted to judge.
In said process, when CON_A that the phase place of counter A equals to set in advance, produce data acquisition enable signal Data_sample_en, and input read data end.
The read data end is when data acquisition enable signal Data_sample_en is effective, from storage unit reading of data and output.
It is as follows to adopt said apparatus of the present invention to transmit the process of data in asynchronous clock domain:
Step 100 writing enable signal Data_wt_en when effective, in storage unit, produces metadata cache simultaneously a data ready transport indicator Data_rdy and sends to the take over party;
Step 200, the take over party carries out the edge to it and detects after described data ready indicator signal Data_rdy is postponed at least two clock period, produces data indicator signal Data_rdy_sync when detecting described data ready indicator signal rising edge;
Step 300 when described data indicator signal Data_rdy_sync arrives, is judged the relation of the count cycle PH_A of the phase place Cnt_A of this hour counter A and counter A,
Cnt_A equals under the situation of its count cycle PH_A in counter A phase place, and when promptly both differences equalled zero, counter A normally counted, and reaches in the phase place of counter A and to produce data acquisition enable signal Data_sample_en when preestablishing phase place CON_A;
The absolute value of both differences greater than the system works clock zone situation of a clock period under, when next Data_rdy_sync arrives, counter A zero clearing is counted again.During this period, reach in the phase place of counter A and to produce data acquisition enable signal Data_sample_en when preestablishing phase place CON_A;
Under the situation of absolute value smaller or equal to a clock period of both differences, further judge whether all to equal identical value in the phase place that continuous CON_B Data_rdy_sync signal arrives hour counter A, if then when next Data_rdy_sync arrives, counter A zero clearing is counted again; Otherwise counter B zero clearing and execution in step C are rejudged.During this period, reach in the phase place of counter A and to produce data acquisition enable signal Data_sample_en when preestablishing phase place CON_A.
Step 400, read data end according to described data acquisition enable signal from the storage unit reading of data.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1, a kind ofly it is characterized in that in the asynchronous clock domain apparatus for transmitting data this device comprises:
Storage unit is used for data cached;
The write data end, be used for write enable signal when effective with metadata cache in storage unit;
Data ready indicator signal generation circuit is used for producing the data ready indicator signal when effective writing enable signal;
Along testing circuit, be used to detect the edge of the data ready indicator signal that data ready indicator signal generation circuit produces, when detecting the edge of described data ready indicator signal, produce the data indicator signal;
The phase place monitoring and the data acquisition phase generator that comprise first counter are used for adjusting according to described data indicator signal the phase place of first counter, and produce the data acquisition enable signal when the phase place of first counter reaches predefined phase place;
The read data end is used for data acquisition enable signal according to phase place monitoring and the generation of data acquisition phase generator from the storage unit reading of data;
Wherein write data end, data ready indicator signal generation circuit working with the road clock zone, are operated in system works clock zone along testing circuit, phase place monitoring and data acquisition phase generator and read data end in data.
2, device according to claim 1, it is characterized in that, this device further comprises at data ready indicator signal generation circuit and along the signal delay circuit between the testing circuit, and input is described along testing circuit after being used for described data ready indicator signal latched at least two clock period.
3, device according to claim 2 is characterized in that, described signal delay circuit is made up of the d type flip flop of a plurality of polyphones.
4, device according to claim 1 is characterized in that, described data ready indicator signal generation circuit comprises first selector, second selector, d type flip flop and chronotron, wherein,
1 input end of first selector is transfused to 0,0 input end and links to each other with the output terminal of described d type flip flop, and control end links to each other with the output terminal of described chronotron, and output terminal links to each other with 0 input end of second selector;
1 input end of second selector is transfused to 1,0 input end and is linked to each other with the output terminal of first selector, and control end is transfused to writes enable signal, and output terminal links to each other with the D input end of described d type flip flop;
The D input end of described d type flip flop links to each other with the output terminal of second selector, and output terminal links to each other along 0 input end of testing circuit, first selector and the input end of described chronotron with described;
The input end of described chronotron links to each other with the output terminal of described d type flip flop, and output terminal links to each other with the control end of first selector.
5, device according to claim 4 is characterized in that, described chronotron is made up of the d type flip flop of a plurality of polyphones, perhaps for waiting for the counter of a plurality of clock period output signals.
6, device according to claim 1, it is characterized in that, described phase place monitoring and data acquisition phase generator further comprise third selector, the 4th selector switch, the 5th selector switch, first d type flip flop, second d type flip flop and second counter, wherein
1 input end of third selector is transfused to 1,0 input end and links to each other with the output terminal of first d type flip flop, and control end is transfused to described data indicator signal, and output terminal links to each other with the D input end of first d type flip flop;
1 input end of the 4th selector switch is transfused to described data indicator signal, and 0 input end is transfused to 0, and control end links to each other with the output terminal of first counter, and output terminal links to each other with the input end of the 5th selector switch;
1 input end of the 5th selector switch is transfused to described data indicator signal, and 0 input end links to each other with the output terminal of the 4th selector switch, and control end links to each other with the output terminal of first d type flip flop, and output terminal links to each other with the clear terminal of first counter;
The D input end of first d type flip flop links to each other with the output terminal of third selector, and output terminal links to each other with 0 input end of third selector, the control end of the 5th selector switch and the Enable Pin of first counter;
The D input end of second d type flip flop links to each other with the output terminal of first counter, and Enable Pin is transfused to described data indicator signal, and output terminal links to each other with the clear terminal of second counter;
The clear terminal of first counter links to each other with the output terminal of the 5th selector switch, Enable Pin links to each other with the output terminal of first d type flip flop, output terminal links to each other with the control end of the 4th selector switch and the D input end of second d type flip flop, and the output terminal output data of first counter is gathered enable signal;
The clear terminal of second counter links to each other with the output terminal of its output terminal and second d type flip flop, and Enable Pin is transfused to described data indicator signal, and output terminal links to each other with its clear terminal.
7, device according to claim 1 is characterized in that, described storage unit is Random Access Storage Unit or register.
8, a kind of method in asynchronous clock domain transmission data, wherein transmit leg is positioned at data with the road clock zone, and the take over party is positioned at the system works clock zone and comprises first counter, it is characterized in that, and this method may further comprise the steps:
A. transmit leg in storage unit, produces metadata cache simultaneously a data ready transport indicator and sends to the take over party writing enable signal when effective;
B. the take over party produces the data indicator signal when detecting described data ready indicator signal edge;
C. adjust the phase place of first counter according to described data indicator signal, and reach when setting phase place from the storage unit reading of data in the phase place of first counter.
9, method according to claim 8 is characterized in that, step B takes a step forward and comprises the step that described data ready indicator signal is latched an above clock period.
10, method according to claim 8 is characterized in that, the step of adjusting the phase place of first counter according to described data indicator signal described in the step C comprises:
Whether the current phase place of first counter equaled its maximum phase when the judgment data indicator signal arrived, under situation about being not equal to, whether that judges described current phase place and maximum phase differs absolute value greater than 1, if greater than 1, then when next data indicator signal arrives, trigger described first counter and count again; If smaller or equal to 1, then under the situation that the difference of the current phase place of described first counter and its maximum phase remains unchanged when continuous a plurality of data indicator signals arrive, trigger described first counter and count again.
11, method according to claim 8 is characterized in that, reaches in the phase place of first counter described in the step C that the step from the storage unit reading of data comprises when setting phase place:
When arriving predefined phase place, the phase place of first counter produces the data acquisition enable signal;
According to described data acquisition enable signal from the storage unit reading of data.
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