CN1972168B - Programmable variable-length bit-stream processor - Google Patents
Programmable variable-length bit-stream processor Download PDFInfo
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- CN1972168B CN1972168B CN2005100617021A CN200510061702A CN1972168B CN 1972168 B CN1972168 B CN 1972168B CN 2005100617021 A CN2005100617021 A CN 2005100617021A CN 200510061702 A CN200510061702 A CN 200510061702A CN 1972168 B CN1972168 B CN 1972168B
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Abstract
This invention relates to one programmable variable bit processor, which comprises main controller, address generator, bit flow data memory, register set and data channel to process bit data, wherein, the main controller controls whole programmable bit processor to provide operation information and times; the data channel is processor execution unit to fulfill lone various bit flow processing and writing results to main controller.
Description
(1) technical field
The bit stream (BITSTREAM) that the present invention relates to quicken multimedias such as audio frequency, video, image and network service is packed or is unpacked the circuit and the technology of processing, relates in particular to programmable variable-length bit-stream processor.
(2) background technology
Along with the development of the multimedia technology and the network communications technology, carry out packing and unpack the task of variable length bitstream data very general, and more and more higher to the requirement of real-time operation.But when packing variable length bitstream data, a certain numerical value need be generated the variable length bitstream data usually, need a large amount of displacement and bit concatenation; When unpacking the variable length bitstream data, have only the length and the semanteme of the previous data of cicada, just may handle the next data in the variable length bitstream data.Therefore, the variable length bitstream data serial process process of this bit level is compared with the parallel computation processing of data, and the time that is consumed is longer relatively.
For the time of the serial process process that reduces this variable length bitstream data, with the packing of effective realization variable length bitstream data or separate package operation, need the hardware circuit of development and Design special use to quicken the packing of variable length bitstream data or separate package operation.The special hardware circuit scheme, although efficient, range of application is little, does not have a versatility.It generally is that variable length bitstream data at certain particular type designs, be used for this particular type of special disposal the variable length bitstream data packing or separate package operation, so, when being applied in the variable length bitstream data of other type, treatment effeciency may can not normally carry out the packing of this variable-length bit-stream or unpack operational processes very low or at all.
Another kind of scheme is to adopt the packing of processor realization variable length bitstream data or separate package operation.Yet the instruction manipulation of general processor does not possess the bit-level operational capacity, realize the bit-level operation, needs a large amount of displacement and logical operation.So in the packing of handling the variable length bitstream data or when unpacking this series process, processing speed is relatively slow, is difficult to satisfy the packing of handling the variable length bitstream data in real time or the requirement of separating package operation.
(3) summary of the invention
Slow for the processing speed that overcomes existing variable length bit-stream processor, as can not to satisfy enforcement processing demands deficiency, the invention provides a kind of can speed up processing, effectively satisfy the programmable variable-length bit-stream processor of handling the packing of variable length bitstream data in real time or separating package operation.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of programmable variable-length bit-stream processor, this processor comprises: bit stream memory, the variable length bitstream data that inputs or outputs that is used to store programmable variable-length bit-stream processor; Address generator is used for the address that reads or writes that calculates the bit stream memory of increasing or decreasing; Described processor also comprises: handle the data path of variable-length bit-stream, be used for the instruction according to master controller, handle the variable length bitstream data:
From the variable length bitstream data of input, extract bitstream data;
" 0 " bit prefix of variable length bitstream data of input or the number of " 1 " bit prefix are added up;
Change the current bit pointer of the variable length bitstream data that inputs or outputs;
And, according to the data value and the data bits length scale generation output variable length bitstream data of input;
Master controller is used to dispose, the data path and the address generator of control and treatment variable-length bit-stream, and the state and the data of their feedbacks are handled:
During configuration, earlier data path and the address generator of handling variable-length bit-stream is configured, specifies the mode of operation of programmable variable-length bit-stream processor, and bit bit pointer position and bit stream are inputed or outputed data carry out initialization operation;
Separating under the pack mode, master controller produces operation and operand information, and the read operation of control bit stream memory, from the bit stream memory read to the variable length bitstream data as the input of the data path of handling variable-length bit-stream;
Under the packing pattern, master controller produces operation and operand information, and described operation and operand information comprise the data value and the data bit bit length of input, and the write operation of control bit stream memory;
Registers group is used for the data path of stores processor variable-length bit-stream and the various data messages between the master controller.
Further, described registers group comprises:
Configuration register is used to deposit master controller to the data path of processing variable-length bit-stream and the configuration information of address generator;
General purpose register set is used to deposit the operand information of the data path of handling variable-length bit-stream, comprises the data value and the data bit bit length that input or output;
Bit stream inputs or outputs the fifo register group, links to each other with the data path of handling variable-length bit-stream with the bit stream memory, be used to deposit the processing variable-length bit-stream data path input or output bitstream data;
Control and status register, be used to deposit the work control information and the feedback states information of the data path of handling variable-length bit-stream;
The bit pointer register is used to deposit current bit stream and inputs or outputs fifo register bit bit position.
Further again, described configuration register comprises:
Bit stream memory base register is used for depositing the base address of variable length bitstream data at the bit stream memory;
Bit stream bit number register is used to the bit stream total number of bits of depositing the bit stream total number of bits of required input or exporting altogether;
The mode of operation position is used to indicate programmable variable-length bit-stream processor to work in and unpacks or the packing pattern.
Further, the data path of described processing variable-length bit-stream comprises:
The pointer treatment circuit is used to calculate the bit pointer value of input bit flow data or output bit flow data, and controls and select the scope of input bit flow data or output bit flow data;
Bit stream inputs or outputs fifo register and selects circuit, is used for inputing or outputing the register that inputs or outputs that the fifo register group is selected the data path of handling variable-length bit-stream from bit stream;
The data shift circuit is used to select the input bit flow data or the output bit flow data of predetermined bit bit length;
The bit string connecting circuit is used for sequentially connecting input bit flow data or the output bit flow data that the predetermined bit bit length comes out from the data shift circuit;
The prefix counting circuit is used to add up " 0 " bit prefix of bitstream data of predetermined length or the bit number of " 1 " bit prefix.
Described bit stream inputs or outputs the fifo register group and comprises at least two registers, inputs or outputs from bit stream according to the value of bit pointer register and selects a pair of register the fifo register successively; The data shift circuit of described data path comprises two independently shifting processing unit, is used for 2 circuit-switched data that input or output from bit stream the register pair that register FIFO selects are carried out shifting processing respectively; Separating under the pack mode, give two independently shifting processing unit the data of two-way output register successively according to order, the variable length bitstream data that extracts earlier predetermined length from current register successively unpacks, when pointer when current register moves on to another register, produce write signal and require master controller when next clock arrives, the content of current register to be upgraded with the new data in the bit stream memory; Under the packing pattern, two independently the output of shifting processing unit write back respectively to selected input register, beginning little-endian from pointer position successively earlier pushes the variable length bitstream data that generates the current register, when pointer when current register moves on to another register, and produce write signal and feed back to master controller, master controller is write current content in the bit stream memory when next clock arrives gone.
Described data shift circuit has 5 ranks of switches, is used to realize the displacement of the predetermined bit bit length of input bit flow data, and the bit of vacating after the displacement is with filling up number of bits according to filling up.
Described master controller also comprises the aborted request circuit, is used for when separating pack mode or packing pattern, and the aborted request of the data path of variable-length bit-stream is handled in corresponding and solution.
Described master controller also comprises the normal termination request circuit, is used for when separating pack mode or packing pattern, and the normal termination request of the data path of variable-length bit-stream is handled in corresponding and solution.
Separating under the pack mode, finishing following operation:
When the bit length of uncertain variable length bitstream data, repeat the extraction operation that data bits is uneven in length, extract the variable length bitstream data of predetermined length, the value of bit stream memory base register and bit stream bit number register remains unchanged;
When determining the bit length of variable length bitstream data, carry out the extraction operation of fixed bit bit length, extract the variable length bitstream data of predetermined length, and the value of update bit stream memory base register and bit stream bit number register;
When determining the bit length of variable length bitstream data, carry out the pointer movement operation, directly skip the variable length bitstream data, and the value of update bit stream memory base register and bit stream bit number register;
When calculating the bit prefix feature of variable length bitstream data, set bit prefix bit length scope, carry out " 0 " bit prefix or " 1 " bit prefix counting operation, statistics obtains " 0 " bit prefix of next variable length bitstream data or the bit number of " 1 " bit prefix, and the value of bit stream memory base register and bit stream bit number register remains unchanged.
Described master controller is microprocessor or finite state machine.
Operation principle of the present invention is: when programmable variable-length bit-stream processor works in the packing pattern, master controller produces operation and operand information-the comprise data value and the data bit bit length of input, and the write operation of control bit stream memory, operation and operand information that the data path of processing variable-length bit-stream transmits according to master controller, to generate the variable length bitstream data by the data shift circuit and push, be spliced to bit stream and input or output the fifo register group, write after the byte-aligned in the bit stream memory.
Programmable variable-length bit-stream processor works in when separating pack mode, the variable length bitstream data all leaves in the bit stream memory, master controller produces operation and operand information, and the read operation of control bit stream memory, from the bit stream memory read to the variable length bitstream data deposit in bit stream and input or output the fifo register group, input as the data path of handling variable-length bit-stream, operation information and data length operand that the data path of processing variable-length bit-stream then transmits according to master controller, by the pointer treatment circuit, bit stream inputs or outputs fifo register and selects circuit, the data shift circuit, the bit string connecting circuit, the prefix computation circuit extracts the variable length bitstream data or counts " 0 " bit prefix or the bit number of " 1 " bit prefix.Can finish following operation:
When the bit length of uncertain variable length bitstream data, repeat the extraction operation that data bits is uneven in length, extract the variable length bitstream data of predetermined length, but do not change the value of bit stream memory base register and bit stream bit number register;
When determining the bit length of variable length bitstream data, carry out the extraction operation of fixed bit bit length, extract the variable length bitstream data of predetermined length, and the value of update bit stream memory base register and bit stream bit number register;
When determining the bit length of variable length bitstream data, carry out the pointer movement operation, directly skip the variable length bitstream data, and the value of update bit stream memory base register and bit stream bit number register;
When needs are understood the bit prefix feature of variable length bitstream data, set bit prefix bit length scope, carry out " 0 " bit prefix or " 1 " bit prefix counting operation, statistics obtains " 0 " bit prefix of next variable length bitstream data or the bit number of " 1 " bit prefix, but does not change the value of bit stream memory base register and bit stream bit number register.
Programmable variable-length bit-stream processor works in when separating pack mode or packing pattern, main controller response and the aborted request or the normal termination request that solve the data path of handling variable-length bit-stream.
When the operation of the bit of " 0 " bit prefix or " 1 " bit prefix counting, master controller can be given the operand of a data bit length, generally is the maximal bit bit length of variable length bitstream data, plays the length restriction effect.When for example carrying out the operation of bit number statistics of " 0 " bit prefix, the value of data bit bit length is 16 o'clock, can be used for distinguishing the situation of bitstream data for " 0,000 0,000 0,000 0001 " and " 00,000,000 0,000 0000 ".Bitstream data be " 0X8000 " and " 0X0000 " situation in other words bitstream data be the situation of " 1,000 0,000 0,000 000 " and " 0,000 0,000 0,000 0000 "
Can efficiently handle the operation of relevant variable length bitstream data according to programmable variable-length bit-stream processor of the present invention, for the packing of the variable length bitstream data in limiting length range, unpack and the operations such as bit calculating of " 0 " bit prefix or " 1 " bit prefix all can be finished in a clock.
Beneficial effect of the present invention mainly shows: 1, can speed up processing; 2, effectively satisfy and handle the packing of variable length bitstream data in real time or separate package operation; 3, workflow adopts pipeline mode, packs, unpacks and operation such as prefix computation can be finished in a clock.
(4) description of drawings
Fig. 1 is the composition block diagram of programmable variable-length bit-stream processor;
Fig. 2 is a block diagram of handling the data-path elements of variable-length bit-stream;
Fig. 3 inputs or outputs the state exchange schematic diagram that fifo register is selected circuit;
Fig. 4 is the schematic diagram of data shift circuit;
Fig. 5 is the schematic diagram of bit stream memory in the programmable variable-length bit-stream processor example;
Fig. 6 is the example schematic that the job contract of programmable variable-length bit-stream processor proper solution is done;
Fig. 7 is normally the pack example schematic of work of programmable variable-length bit-stream processor.
(5) embodiment
Below in conjunction with accompanying drawing the present invention is further described.
As shown in Figure 1, programmable variable-length bit-stream processor comprises master controller 102, address generator 104, handles data path 106, the bit stream memory 108 of variable-length bit-stream, and registers group 120.
During configuration, earlier data path 106 and the address generator 104 of handling variable-length bit-stream is configured, specifies the mode of operation of programmable variable-length bit-stream processor, and bit bit pointer position and bit stream are inputed or outputed data carry out initialization operation;
Separating under the pack mode, master controller 102 produces operation and operand information, and the read operation of control bit stream memory 108, and the variable length bitstream data of reading from bit stream memory 108 is as the input of the data path 106 of handling variable-length bit-stream;
Under the packing pattern, master controller 102 produces operation and operand information, and described operation and operand information comprise the data value and the data bit bit length of input, and the write operation of control bit stream memory 108;
Handle the data path 106 of variable-length bit-stream, can be used for:
From the variable length bitstream data of input, extract the bitstream data of certain-length;
" 0 " bit prefix of variable length bitstream data of input or the number of " 1 " bit prefix are added up;
Change the current bit pointer of the variable length bitstream data that inputs or outputs;
Data value and data bits length scale according to input generate output variable length bitstream data.
General purpose register set is used to deposit 102 pairs of operand information of handling the data path 106 of variable-length bit-stream of master controller, comprises the data value and the data bit bit length of input;
Bit stream inputs or outputs the fifo register group, links to each other with the data path 106 of handling variable-length bit-stream with bit stream memory 108, be used to deposit the processing variable-length bit-stream data path 106 input or output bitstream data, and have the FIFO pooling feature;
Control and status register are used to deposit 102 pairs of work control informations of handling the data path 106 of variable-length bit-stream of master controller, and handle the work state information of 106 pairs of master controllers of data path, 102 feedbacks of variable-length bit-stream;
The bit pointer register is used to deposit current bit stream and inputs or outputs fifo register bit bit position;
Configuration register is used to deposit 102 pairs of master controls and handles the data path 106 of variable-length bit-stream and the configuration information of address generator 104.
Wherein configuration register is defined as follows shown in the table 1:
| Bit | Function |
| 31-16 | Be bit stream memory base register, when unpacking from the bit stream memory read in or when packing to the plot of bit stream memory stores variable length bitstream data |
| 15-1 | Be bit stream bit number register, total bit number of the variable length bitstream data that total bit number of required variable length bitstream data of reading in or packing the time have been packed when unpacking |
| 0 | Be the pattern position, be defaulted as and separate pack mode, if be provided with then be the packing pattern |
Table 1
As shown in Figure 2, shown the block diagram of handling the data path 106 of variable-length bit-stream in detail.Data path 106 comprises with the lower part:
(1) the pointer treatment circuit 110:
The value of bit pointer register and master controller 102 pass the data bits size operand of coming and add up, and input or output fifo register figure place delivery with bit stream.When the value of pointer register inputs or outputs the fifo register figure place above bit stream, pointer treatment circuit 110 can input or output fifo register to bit stream and select circuit 112 to produce a mobile logo position, selects bit stream to input or output the state of registers group thereby change.
The value of bit stream bit number register also is will pass the data bits size operand of coming with master controller 102 do plus and minus calculation, is to successively decrease when separating pack mode, and is to increase progressively during the packing pattern.And some the sign position in control and the status register need be provided with by the value of judging bit stream bit number register, when separating pack mode, if the value of bit stream bit number register is 0, then need be provided with and finishes the sign position; If the value of bit stream bit number register is a negative, being the bit stream bit length that inputs or outputs remaining variable length bitstream data in the fifo register group unpacks overflow exception sign position less than passing the data length operand of coming from master controller 102, then need being provided with.
Finishing sign position under the packing pattern, instruct by a specific arrangement to be provided with.Because will do special processing and can be smoothly the variable length bitstream data of last packing be stored in the bit stream memory 108 guaranteeing, but can not change the value of bit stream bit number register with arranging instruction.
(2), bit stream inputs or outputs fifo register and selects circuit 112:
Bit stream inputs or outputs fifo register and selects circuit 112, is used to select a pair of bit stream to input or output fifo register and inputs or outputs as the first via and the second tunnel of the data path 106 of handling variable-length bit-stream.
When programmable variable-length bit-stream processor works in when separating pack mode, the variable length bitstream data is stored in the bit stream memory 108 in advance.Master controller 102 is put into bit stream successively with the variable length bitstream data in the bit stream memory 108 and is inputed or outputed the fifo register group by control address generator 104.
The bit stream of programmable variable-length bit-stream processor inputs or outputs the fifo register group and is made of one group of register, is used to the variable length bitstream data that at every turn unpacks the storage q.s, so that guarantee can sky or overfill in the proper solution packet procedures.With reference to Fig. 2 and Fig. 3, the bit stream of supposing programmable variable-length bit-stream processor inputs or outputs the fifo register group and comprises at least two registers, for example is 3 registers, i.e. register 0 or 1 or 2.
First value according to the bit pointer register inputs or outputs from bit stream selects a pair of register successively the fifo register, it can be register 0 and 1, or register 1 and 2, or register 2 and register 0, give in the data shift circuit 114 two independently shifting processing unit 140 and 141 these 2 tunnel input data according to order successively as data 0 and data 1 again.The state conversion process of selected register pair as shown in Figure 3, when register 0 or 1 state, the variable length bitstream data that extracts earlier predetermined length from register 0 successively unpacks, when pointer when register 0 moves on to register 1, state will be transformed into register 1 or 2 states, and the generation write signal requires master controller 102 when next clock arrives the content of register 0 to be upgraded with the new data in the bit stream memory 108.Equally from register 1 or 2 state exchanges to register 2 or 0, or from register 2 or 0 state exchange to register 0 or 1 o'clock, all can produce write signal requirement master controller 102 and respectively the content in register 1 and the register 2 be upgraded with the new data in the bit stream memory 108.
When programmable variable-length bit-stream processor works in the packing pattern, also be that value according to the bit pointer register inputs or outputs from bit stream and selects a pair of register the fifo register group successively, not only input has had the good variable length bitstream data of packing as input register, also as the destination register of packing variable length bitstream data, because splice generating the variable length bitstream data that existing packing is good in new variable length bitstream data and the input register through shift circuit 114, write back selected input register again, and in storing bit stream memory 108 after the byte-aligned into.With reference to Fig. 2 and Fig. 3, suppose that the register number that bit stream inputs or outputs registers group is at 3 o'clock, 2 tunnel inputs of choosing can be register 0 and 1, or register 1 and 2, or register 2 and register 0, the state conversion process of selected register pair also is as shown in Figure 3.In the data shift circuit 114 2 tunnel output writes back respectively to selected input register, as when register 0 or 1 state, beginning little-endian from pointer position successively pushes the variable length bitstream data that generates the register 0, when pointer when register 0 moves on to register 1, state will be transformed into register 1 or 2 states, and produce write signal and feed back to master controller 102, master controller 102 is write the content of register 0 in the bit stream memory 108 when next clock arrives gone.Equally from register 1 or 2 state exchanges to register 2 or 0, or from register 2 or 0 state exchange to register 0 or 1 o'clock, all can produce write signal and feed back to master control 102, the content in register 1 and the register 2 is write in the bit stream memory 108 is gone.
(3), the data shift circuit 114:
Data shift circuit 114 is used to select the input bit flow data or the output bit flow data of predetermined bit bit length.
Data shift circuit 114, have two independently data shift unit 140 and 141 respectively 2 circuit-switched data that input or output from bit stream in the register pair of selecting the register FIFO are carried out shifting processing respectively, boundary-intersected with the permission pointer can jump to the second tunnel first place of importing from the position, end of first via input, guarantees that 2 tunnel each that import all are accessible for pointer.As Fig. 2, shown in Figure 4, data shift unit 140 and 141 all can be regarded 32 special barrel shifters as, with the input bit flow data with fill up bitstream data (FILLIN) as importing, have 5 ranks of switches, can realize 0 to 16 displacement of input bit flow data, and bit the filling up of vacating after the displacement with the corresponding bit of FILLIN.
When separating pack mode, the logic ' 0 ' that bit stream inputs or outputs the fifo register figure place is as the bitstream data of filling up of 2 independent transfer processing units 140 in the data shift circuit 114 and 141; In packing during pattern, according to the operand of controller 102 forward data values and data bit bit length, the variable length bitstream data that is generated is as the bitstream data of filling up of 2 independent transfer processing units 140 in the data shift circuit 114 and 141.
(4), bit string connecting circuit 116 and prefix counting circuit 118:
Bit string connecting circuit 116 is used for sequentially connecting input bit flow data or the output bit flow data that the predetermined bit bit length comes out from data shift circuit 114.
Prefix counting circuit 118 is used to add up " 0 " bit prefix of bitstream data of predetermined length or the bit number of " 1 " bit prefix.
Programmable variable-length bit-stream processor works in when separating pack mode, and 2 independent transfer processing units 140 and 141 the output processing by bit string connecting circuit 116 can obtain the variable length bitstream data from predetermined length in the data shift circuit 114.Control and the status register that is provided with according to master controller 102 again, when extracting the variable length bitstream data of predetermined length, with the output of its semantic data path 106 as the processing variable-length bit-stream, and be returned to master controller 102 by a general register; When the bit number of " 0 " bit prefix or " 1 " bit prefix is calculated, with the input of the variable length bitstream data of the predetermined length that obtains as prefix counting circuit 118, the number of " 0 " or " 1 " bit prefix that obtains after the process statistical computation also is returned to master controller 102 by a general register as the output of the data path 106 of handling variable-length bit-stream.
When programmable variable-length bit-stream processor worked in the packing pattern, 2 independent transfer processing units 140 and 141 output directly write back selected bit stream successively to input or output fifo register right in the data shift circuit 114.When first via bit stream input or output fifo register write full after, when next clock arrives, master controller 102 will be write data content wherein in the bit stream memory 108, and change the state that bit stream inputs or outputs the fifo register group simultaneously.
When the packing pattern, last the variable length bitstream data that generates is write back at selected first via bit stream to input or output in the fifo register, but the length of this variable length bitstream data can not input or output bit stream fifo register just and writes full usually, we need do special processing with the arrangement instruction the vacant high position of bit stream input and output fifo register is full of with ' 0 ', can be smoothly the variable length bitstream data of last packing be stored in the bit stream memory 108 guaranteeing, but can not change the value of bit stream bit number register.
The course of work of programmable variable-length bit-stream processor:
Use programmable variable-length bit-stream processor to handle the unpacking of variable length bitstream data or the method for operating of packing, comprise following step:
Before the programmable variable-length bit-stream processor operate as normal, master controller needs 102 are configured data path 106 and the address generator 104 of handling variable-length bit-stream earlier according to application requirements, give the configuration register assignment, specify the programmable variable-length bit-stream processor mode of operation, and bit bit pointer register and bit stream are inputed or outputed fifo register group etc. carry out initialization operation;
When programmable variable-length bit-stream processor works in the proper solution pack mode, predetermined variable length bitstream data all leaves in the bit stream memory 108, master controller 102 produces operation and operand information, and the read operation of control bit stream memory 108, the variable length bitstream data of reading from bit stream memory 108 is deposited in bit stream and is inputed or outputed the fifo register group, input as the data path 106 of handling variable-length bit-stream, handle 106 operation information and data length operands that transmit according to master controller of data path of variable-length bit-stream, by pointer treatment circuit 110, bit stream inputs or outputs fifo register and selects circuit 112, data shift circuit 114, bit string connecting circuit 116, prefix computation circuit 118 can obtain extracting the variable length bitstream data of predetermined length or counting " 0 " the bit number of bit prefix or " 1 " bit prefix.
When programmable variable-length bit-stream processor works in normal packing pattern, master controller 102 produces operation and operand information-the comprise data value and the data bit bit length of input, and the write operation of control bit stream memory 108, operation and operand information that the data path 106 of processing variable-length bit-stream transmits according to master controller 102, the variable length bitstream data of the predetermined length that generates can be pushed, is spliced to bit stream by data shift circuit 114 and input or output the fifo register group, write after the byte-aligned in the bit stream memory 108.
Programmable variable-length bit-stream processor works in when separating pack mode or packing pattern, and main controller 102 can respond and solve the aborted request or the normal termination request of the data path 106 of handling variable-length bit-stream.
The structure of present embodiment is identical with embodiment 1 with the course of work.
Programmable variable-length bit-stream processor is controlled by master controller 102, is divided into layoutprocedure and packing or unpacks the course of work.With reference to Fig. 5, the simple examples shown in 6 and 7 can be easier to understand the course of work of programmable variable-length bit-stream processor 10.The bit stream of all supposing programmable variable-length bit-stream processor inputs or outputs the fifo register group and is made of 3 registers, i.e. register 0 or 1 or 2.
(1), separate the course of work under the pack mode:
Suppose in the bit stream memory 108 that from the address 0 has begun to store the variable length bitstream data " 0XC190 0,FA5 8,011 8858 5A08 F00F ... " of 20KB, then master controller 102 is provided with register earlier for " 0X0,000 1000 ", the value that is bit stream memory base register is 0, the value of bit stream bit number register is 20K, the pattern position is 0, programmable variable-length bit-stream processor 10 is started working in separating pack mode, and with the value zero clearing of bit register.
At the rising edge of three clocks at first, master controller 102 is put into bit stream input and output fifo register group respectively with the variable length bitstream data " 0XC190 " " 0X0FA5 " " 0X8011 " of address 0 in the bit stream memory 108 or 1 or 2 the insides successively, after data initialization was good, programmable variable-length bit-stream processor 10 beginning proper solution jobs contract were done.
Rising edge at the 4th clock, shifting processing unit 140 and 141 input are that bit stream inputs or outputs register 0 and the register 1 in the fifo register group, the data length operand that master controller 102 transmits is that " 10 " are so that there is the initial displacement of " 10 " shifting processing unit 140, the output of shifting processing unit 141 all puts 0, its result can obtain successively from " 10 " number of bits that pointer position begins according to " 01 1,001 0000 " through bit string connecting circuit 114, and this data result also is " 4 " as the number that the input of prefix computation circuit 116 can calculate " 0 " prefix bits position.
Rising edge at the 5th clock, the value of bit pointer register is " 10 ", the value of bit stream bit number register successively decrease " 10 ", shifting processing unit 140 and 141 input are still bit stream and input or output register 0 and register 1 in the fifo register group, the data length operand that master controller 102 transmits is that " 15 " are so that shifting processing unit 140 and 141 has " 6 " and " 9 " initial displacement respectively, its result can obtain successively from " 15 " number of bits that pointer position begins according to " 110 1,001 01110000 " through bit string connecting circuit 114, and this data result also is " 4 " as the number that the input of prefix computation circuit 116 can calculate " 0 " prefix bits position.
Because the value of bit pointer register is summed into " 25 " and surpasses " 16 ", can produce a read signal to master controller 102, make master controller 102 from bit stream memory 108, read the data in the address " 3 ", for the register in the bit stream input and output fifo register group 120 0 is prepared next clock data updated.To change the state that bit stream inputs or outputs the fifo register group simultaneously, and the new value of bit pointer register is " 9 ".
At the rising edge of the 6th clock, handle the register 0 that bit stream in the data path 106 of variable-length bit-stream inputs or outputs the fifo register group and receive master controller 102 ready variable length bitstream data " 1,000 1,000 0,101 1000 ".The value of bit pointer register is " 9 ", the value of bit stream bit number register successively decrease " 15 ", shifting processing unit 140 and 141 input still are register 1 and the register 2 in the bit stream input and output fifo register group 120, the data length operand that master controller 102 transmits is that " 14 " are so that shifting processing unit 140 and 141 all has the initial displacement of " 7 " and " 7 " respectively, its result can obtain successively from " 14 " number of bits that pointer position begins according to " 00 1,000 10000111 " through bit string connecting circuit 114, and this data result also is " 0 " as the number that the input of prefix computation circuit 116 can calculate " 0 " prefix bits position.
Because the value of bit pointer register is summed into " 23 " and surpasses " 16 ", can produce a read signal to master controller 102, make master controller 102 from bit stream memory 108, read the data in the address " 4 ", for the register 1 that bit stream inputs or outputs in the fifo register group is prepared next clock data updated.To change the state that bit stream inputs or outputs the fifo register group simultaneously, and the new value of bit pointer register is " 7 ".
At the rising edge of the 7th clock, handle the register 1 that bit stream in the data path 106 of variable-length bit-stream inputs or outputs the fifo register group and receive master controller 102 ready variable length bitstream data " 0,101 1,010 0,000 1000 ".And in the data path 106 of handling variable-length bit-stream, the value of bit pointer register is " 7 ", the value of bit stream bit number register successively decrease " 14 ", shifting processing unit 140 and 141 input are still bit stream and input or output register 2 and register 0 in the fifo register group, the data length that master controller 102 transmits is that " 16 " are so that shifting processing unit 140 and 141 all has the initial displacement of " 9 " and " 7 " respectively, its result can obtain successively from " 16 " number of bits that pointer position begins according to " 1,011 0,001 0,000 0000 " through bit string connecting circuit 114, and this data result also is " 8 " as the number that the input of prefix computation circuit 116 can calculate " 0 " prefix bits position.
Because the value of bit pointer register is summed into " 23 " and surpasses " 16 ", can produce a read signal to master controller 102, make master controller 102 from bit stream memory 108, read the variable length bitstream data " 1,111 0,000 0,000 1111 " in the address " 5 ", for the register in the bit stream input and output fifo register group 120 2 is prepared next clock data updated.To change the state of bit stream input and output fifo register group 120 simultaneously, and the new value of bit pointer register is " 7 ".
From on can see, programmable variable-length bit-stream processor of the present invention clock moment of clock signal carry out separate package operation, thereby advantageously realized separating at a high speed package operation.
(2), the course of work of programmable variable-length bit-stream processor under the packing pattern:
Rising edge at first clock, the data length operand that master controller 102 transmits is " 5 ", the data value operand of input be " 15 ", and what shifting processing unit 140 and 141 input and destination register selected is that bit stream inputs or outputs register 0 and the register 1 in the fifo register group.All there is one " 5 " initial displacement shifting processing unit 140 and 141, and bit stream result " 01111XXX XXXX XXXX " and " 0111 1XXX XXXX XXXX " after shifting processing unit 140 and 141 displacements are write back register 0 and register 1 respectively.
At the rising edge of second clock, the value of bit stream bit number register is accumulated as " 5 ", and the value of bit register also can be updated to " 5 ".The data length operand that master controller 102 transmits is " 15 ", the data value operand of input is bitstream data " 101 0,000 0,111 1000 " for " 20600 ", and the bit stream that is still of shifting processing unit 140 and 141 input and destination register choosing inputs or outputs register 0 and register 1 in the fifo register group.Shifting processing unit 140 and 141 has one " 11 " and the initial displacement of " 15 " respectively, and bit stream result " 0,000 1,111 0,000 1111 " and " 10,100,000 1111 000X " after shifting processing unit 140 and 141 displacements are write back register 0 and register 1 respectively.
Because the value of bit pointer register is summed into " 20 " and surpasses " 16 ", can produce a write signal to master controller 102, make master controller 102 when the rising edge of next clock arrives, the bit stream result " 0,000 1,111 0,000 1111 " of shifting processing unit 140 be stored into the address " 0 " of bit stream memory 108.The bit stream that will change the choosing of selected input and destination register simultaneously inputs or outputs the state of fifo register group, and the new value of bit pointer register is " 4 ".
At the rising edge of the 3rd clock, the value of bit number register is accumulated as " 20 ", and the value of bit register is updated to " 4 ".Master controller 102 stores the bit stream result " 0,000 1,111 00001111 " of shifting processing unit 140 in the address " 0 " of bit stream memory 108 into.And the data length operand that the data path 106 of giving the processing variable-length bit-stream transmits is " 13 ", the data value operand of input is bitstream data " 0 0,000 0,101 0011 " for " 83 ", and the bit stream that is still of shifting processing unit 140 and 141 input and destination register choosing inputs or outputs register 1 and register 2 in the fifo register group.Shifting processing unit 140 and 141 has one " 12 " and the initial displacement of " 13 " respectively, and bit stream result " 0,000 0,101 0,011 1010 " and " 0,000 0,010 1001 1XXX " after shifting processing unit 140 and 141 displacements are write back register 1 and register 2 respectively.
Because the value of bit pointer register is summed into " 17 " and surpasses " 16 ", can produce a write signal to master controller 102, make master controller 102 when the rising edge of next clock arrives, the bit stream result " 0,000 0,101 0,011 1010 " of shifting processing unit 140 be stored into the address " 1 " of bit stream memory 108.To change the state of the bit stream input and output fifo register group 120 of selected input and destination register choosing simultaneously, and the new value of bit pointer register is " 1 ".
At the rising edge of the 4th clock, the value of bit number register is accumulated as " 33 ", and the value of bit register is updated to " 1 ".Master controller 102 stores the bit stream result " 0,000 0,101 00111010 " of shifting processing unit 1120 in the address " 1 " of bit stream memory 108 into.And the data length operand that the data path 106 of giving the processing variable-length bit-stream transmits is " 6 ", the data value operand of input is bitstream data " 10 0001 " for " 33 ", shifting processing unit 140 and 141 input and destination register choosing be that bit stream inputs or outputs register 2 and the register 0 in the fifo register group.Shifting processing unit 140 and 141 all has one " 6 " initial displacement respectively, and bit stream result " 1,000 01,000,000 1010 " and " 1,000 0,100 0,011 1100 " after shifting processing unit 140 and 141 displacements are write back register 2 and register 0 respectively.
When the rising edge of next clock arrives, the value of bit number register is accumulated as " 39 ", and the value of bit pointer register is updated to " 7 ", but can not send write signal, so will can not change the state that the bit stream of selected input and destination register choosing inputs or outputs the fifo register group to master controller.
Though here with embodiment invention has been described and the explanation, more the invention of broad aspect be not limited to successively specific detail, schematic apparatus and method and shown in and described illustrative examples.Person skilled in the art person obviously can make various changes and correction, does not break away from the defined scope of the invention in the aforesaid right claim.
Claims (10)
1. programmable variable-length bit-stream processor, this processor comprises:
The bit stream memory, the variable length bitstream data that inputs or outputs that is used to store programmable variable-length bit-stream processor;
Address generator is used for the address that reads or writes that calculates the bit stream memory of increasing or decreasing; It is characterized in that: described processor also comprises:
Handle the data path of variable-length bit-stream, be used for instruction, handle the variable length bitstream data according to master controller:
From the variable length bitstream data of input, extract bitstream data;
" 0 " bit prefix of variable length bitstream data of input or the number of " 1 " bit prefix are added up;
Change the current bit pointer of the variable length bitstream data that inputs or outputs;
And, according to the data value and the data bits length scale generation output variable length bitstream data of input; Master controller is used to dispose, the data path and the address generator of control and treatment variable-length bit-stream, and the state and the data of their feedbacks are handled:
During configuration, earlier data path and the address generator of handling variable-length bit-stream is configured, specifies the mode of operation of programmable variable-length bit-stream processor, and bit bit pointer position and bit stream are inputed or outputed data carry out initialization operation;
Separating under the pack mode, master controller produces operation and operand information, and the read operation of control bit stream memory, from the bit stream memory read to the variable length bitstream data as the input of the data path of handling variable-length bit-stream;
Under the packing pattern, master controller produces operation and operand information, and the write operation of control bit stream memory, and described operation and operand information comprise the data value and the data bit bit length of input;
Registers group is used for the data path of stores processor variable-length bit-stream and the various data messages between the master controller.
2. programmable variable-length bit-stream processor as claimed in claim 1 is characterized in that: described registers group comprises:
Configuration register is used to deposit master controller to the data path of processing variable-length bit-stream and the configuration information of address generator;
General purpose register set is used to deposit the operand information of the data path of handling variable-length bit-stream, comprises the data value and the data bit bit length that input or output;
Bit stream inputs or outputs the fifo register group, links to each other with the data path of handling variable-length bit-stream with the bit stream memory, be used to deposit the processing variable-length bit-stream data path input or output bitstream data;
Control and status register, be used to deposit the work control information and the feedback states information of the data path of handling variable-length bit-stream;
The bit pointer register is used to deposit current bit stream and inputs or outputs fifo register bit bit position.
3. programmable variable-length bit-stream processor as claimed in claim 2 is characterized in that: described configuration register comprises;
Bit stream memory base register is used for depositing the base address of variable length bitstream data at the bit stream memory;
Bit stream bit number register is used to the bit stream total number of bits of depositing the bit stream total number of bits of required input or exporting altogether;
The mode of operation position is used to indicate programmable variable-length bit-stream processor to work in and unpacks or the packing pattern.
4. as claim 2 or 3 described programmable variable-length bit-stream processors, it is characterized in that: the data path of described processing variable-length bit-stream comprises:
The pointer treatment circuit is used to calculate the bit pointer value of input bit flow data or output bit flow data, and controls and select the scope of input bit flow data or output bit flow data;
Bit stream inputs or outputs fifo register and selects circuit, is used for inputing or outputing the register that inputs or outputs that the fifo register group is selected the data path of handling variable-length bit-stream from bit stream;
The data shift circuit is used to select the input bit flow data or the output bit flow data of predetermined bit bit length;
The bit string connecting circuit is used for sequentially connecting input bit flow data or the output bit flow data that the predetermined bit bit length comes out from the data shift circuit;
The prefix counting circuit is used to add up " 0 " bit prefix of bitstream data of predetermined length or the bit number of " 1 " bit prefix.
5. programmable variable-length bit-stream processor as claimed in claim 4 is characterized in that: described bit stream inputs or outputs fifo register and selects circuit to input or output from bit stream according to the value of bit pointer register to select a pair of register the fifo register group successively;
The data shift circuit of described data path comprises two independently shifting processing unit, is used for 2 circuit-switched data that input or output from bit stream the register pair that the fifo register group selects are carried out shifting processing respectively; Separating under the pack mode, give two independently shifting processing unit the data of two-way output register successively according to order, the variable length bitstream data that extracts earlier predetermined length from current register successively unpacks, when pointer when current register moves on to another register, produce write signal and require master controller when next clock arrives, the content of current register to be upgraded with the new data in the bit stream memory;
Under the packing pattern, two independently the output of shifting processing unit write back respectively to selected input register, beginning little-endian from pointer position successively earlier pushes the variable length bitstream data that generates the current register, when pointer when current register moves on to another register, and produce write signal and feed back to master controller, master controller is write current content of registers in the bit stream memory when next clock arrives gone.
6. programmable variable-length bit-stream processor as claimed in claim 4, it is characterized in that: described data shift circuit has 5 ranks of switches, be used to realize the displacement of the predetermined bit bit length of input bit flow data, the bit of vacating after the displacement is with filling up number of bits according to filling up.
7. as the described programmable variable-length bit-stream processor of one of claim 1-3, it is characterized in that: described master controller also comprises the aborted request circuit, be used for when separating pack mode or packing pattern response and the aborted request that solves the data path of handling variable-length bit-stream.
8. as the described programmable variable-length bit-stream processor of one of claim 1-3, it is characterized in that: described master controller also comprises the normal termination request circuit, be used for when separating pack mode or packing pattern response and the normal termination request that solves the data path of handling variable-length bit-stream.
9. programmable variable-length bit-stream processor as claimed in claim 3 is characterized in that: separating under the pack mode, finishing following operation:
When the bit length of uncertain variable length bitstream data, repeat the extraction operation that data bits is uneven in length, extract the variable length bitstream data of predetermined length, the value of bit stream memory base register and bit stream bit number register remains unchanged;
When determining the bit length of variable length bitstream data, carry out the extraction operation of fixed bit bit length, extract the variable length bitstream data of predetermined length, and the value of update bit stream memory base register and bit stream bit number register;
When determining the bit length of variable length bitstream data, carry out the pointer movement operation, directly skip the variable length bitstream data, and the value of update bit stream memory base register and bit stream bit number register;
When calculating the bit prefix feature of variable length bitstream data, set bit prefix bit length scope, carry out " 0 " bit prefix or " 1 " bit prefix counting operation, statistics obtains " 0 " bit prefix of next variable length bitstream data or the bit number of " 1 " bit prefix, and the value of bit stream memory base register and bit stream bit number register remains unchanged.
10. programmable variable-length bit-stream processor as claimed in claim 9 is characterized in that: described master controller is microprocessor or finite state machine.
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| CN101635850B (en) * | 2008-08-11 | 2012-01-11 | 青岛海信信芯科技有限公司 | High-speed decoding method and device |
| CN112953681B (en) * | 2021-02-20 | 2022-03-29 | Tcl华星光电技术有限公司 | Decoding method, decoding apparatus, and computer-readable storage medium |
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| CN1129883A (en) * | 1994-11-17 | 1996-08-28 | 大宇电子株式会社 | High speed variable length decoder |
| CN1349353A (en) * | 2000-06-01 | 2002-05-15 | 松下电器产业株式会社 | Variable long code decoding device |
| EP1347650A1 (en) * | 2002-03-18 | 2003-09-24 | STMicroelectronics Limited | Compression circuitry for generating an encoded bitstream from a plurality of video frames |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1129883A (en) * | 1994-11-17 | 1996-08-28 | 大宇电子株式会社 | High speed variable length decoder |
| CN1349353A (en) * | 2000-06-01 | 2002-05-15 | 松下电器产业株式会社 | Variable long code decoding device |
| EP1347650A1 (en) * | 2002-03-18 | 2003-09-24 | STMicroelectronics Limited | Compression circuitry for generating an encoded bitstream from a plurality of video frames |
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