CN1851930A - Partial consumption SOI MOS transistor and making method - Google Patents
Partial consumption SOI MOS transistor and making method Download PDFInfo
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- CN1851930A CN1851930A CN 200610072506 CN200610072506A CN1851930A CN 1851930 A CN1851930 A CN 1851930A CN 200610072506 CN200610072506 CN 200610072506 CN 200610072506 A CN200610072506 A CN 200610072506A CN 1851930 A CN1851930 A CN 1851930A
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Abstract
This invention provides a MOS transistor partly using up a SOI structure and its manufacturing method, in which, the buried insulation layer of said MOS transistor has a concave structure, a semiconductor channel region is placed at the concavity of the buried insulation layer, the upper part is light doped or heavy doped and the lower part is heavy doped, the heavy dope of the channel region can effectively restrain the potential coupling of the drain end voltage to the source end so as to reduce the DIBL effect and short trench effect of the device, light doped or un-doped trench regions can prevent the threshold value voltage change due to the fluctuation of impurities at nm and increase the movability of electrons and adjust the performance of devices.
Description
Technical field:
The invention belongs to semiconductor integrated circuit and manufacturing technology field thereof, relate in particular to SOI MOS transistor of a kind of part depletion and preparation method thereof.
Background technology:
The core parts of semiconductor integrated circuit are the silicon base CMOS devices.The high speed development of IC industry is constantly scaled based on the size of MOS transistor, and constantly dwindling of its characteristic size not only can improve the integration density of integrated circuit greatly, can also improve the performance of circuit.Yet, along with the MOSFET device dimensions shrink to submicron-scale, various physics limits of convergence more and more, traditional MOSFET device architecture has run into increasing challenge.
Silicon on the insulator (SOI) structure is expected to substitute the integrated circuit production that traditional MOSFET device is used for inferior 50 nanometers.It not only can significantly reduce parasitic capacitance soi structure, and is particularly suitable for developing low pressure/low-power consumption application, and the SOI device also has splendid capability of resistance to radiation in addition.Utilize the two kinds of devices that have that soi structure grows up, a kind of is the SOI device of part depletion, and another kind is the SOI device that exhausts entirely.The channel region silicon fiml of the SOI device of part depletion is enough thick, and the width of raceway groove depletion region is less than the thickness of silicon fiml, and the device advantage of this structure is that its design and operation principle and traditional body silicon MOSFET device are very approaching.But its channel region may the substrate effect of floating occur owing to the accumulation of excessive hole, and this effect can cause the performance of device to be affected.The SOI device that exhausts entirely is a kind of structure of thin silicon films, and its channel region exhausts fully, because channel region is exhausted fully, has therefore reduced the electric field of channel region, has also reduced hot carrier's effect simultaneously, and its inhibition to the device short channel effect is also very effective.But after the grid length of device was reduced to 20 nanometers, the thickness of silicon fiml had only several nanometers, was difficult to control on so little thickness technology, therefore made it be difficult to the application of moving towards actual.
Summary of the invention:
The SOI MOS transistor that the purpose of this invention is to provide a kind of part depletion, this transistorized buried insulating layer has concave structure, and raceway groove is positioned at recess, light dope or not doping under the gate dielectric layer of channel region top, the district's heavy doping of channel region undercut.
Second purpose of the present invention provides above-mentioned buried insulating layer and has concave structure, raceway groove is positioned at recess, light dope or not doping under the gate dielectric layer of channel region top, the manufacture method of the MOSFET device of the heavily doped partial depletion SOI structure in channel region undercut district.
Technical scheme of the present invention is as follows:
A kind of MOS transistor of partial depletion SOI structure comprises a gate electrode, a gate dielectric layer, a gate electrode side wall medium layer, semiconductor channel region, a source region, a drain region, a buried insulating layer, semi-conductive substrate; Described buried insulating layer has concave structure on Semiconductor substrate; Described semiconductor channel area, source region and drain region are positioned on the buried insulating layer, semiconductor source region and drain region embed two projection inboards of concave structure buried insulating layer respectively, semiconductor channel area is positioned at buried insulating layer concavity place, its top light dope or not doping, bottom heavy doping; Described semiconductor channel area links to each other with the drain region with described source region respectively in the part at gate electrode two ends; Described gate dielectric layer is positioned on the semiconductor channel area; Described gate electrode is positioned on the gate dielectric layer; Described gate electrode side wall medium layer is positioned at the gate electrode both sides on gate dielectric layer.
The light dope of above-mentioned semiconductor channel area or not doped portion thickness be 10-50nm; The thickness of gate dielectric layer is 1-10nm; The thickness of gate electrode layer is 80-150nm; Gate electrode side wall medium layer width is 5-20nm.
The manufacture method of the MOS transistor of above-mentioned partial depletion SOI structure may further comprise the steps:
(1) semi-conducting material of employing soi structure, it has one deck buried insulating layer, the layer of semiconductor film, the layer of semiconductor substrate, buried insulating layer is between semiconductive thin film and Semiconductor substrate, and the photoetching isolation is formed with the source region, injects by ion to form a high doping semiconductor thin layer;
(2) adopt growth technology to form the new semiconductor lamella of one deck on highly doped semiconductor film layer, new semiconductor lamella does not mix or is low-doped;
(3) growth gate dielectric layer;
(4) deposit gate electrode layer, etching forms gate figure;
(5) side wall medium layer is sacrificed in deposit, and Hui Kehou forms side wall in the gate electrode both sides, be that mask corrosion falls gate dielectric layer with gate electrode and the side wall figure that forms, and both sides are not exposed on doped semiconductor thin layer surface;
(6) corrode the not doped semiconductor thin layer that is exposed, stop corrosion during to high-doped zone;
(7) selective etching high-doped zone stops corrosion when arriving grid covering place;
(8) deposit dielectric is filled the cavity that etching forms, and returns and carves the dielectric of removing the surface;
(9) erode after the sacrificial dielectric layer at gate electrode both sides and top deposit again or thermal oxide growth and form another film dielectric layer;
(10) ion implantation doping source-drain area and gate electrode return then to engrave and state film dielectric layer to form new gate electrode side wall, and according to circumstances, the source leak can adopt epitaxy method to form the source-drain structure of raising;
(11) enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make described MOS transistor.
In the above-mentioned manufacture method, the semiconductor substrate materials in the described step (1) is selected from Si, Ge, SiGe, GaAs or other II-VI, the binary or the ternary semiconductor of III-V and IV-IV family.
Above-mentioned manufacture method, the gate dielectric material in the described step (3) is selected from silicon dioxide, hafnium oxide, hafnium nitride etc.
Above-mentioned manufacture method, the method for described step (3) growth gate dielectric layer is selected from one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition, physical vapor deposition.
Above-mentioned manufacture method sacrifices that the side wall medium layer material is selected from silicon nitride, TEOS (silester) or other all has high corrosion to select the thin-film material of ratio with silicon and silica in the described step (5).
Above-mentioned manufacture method, the etchant solution that the selective etching in the described step (7) is selected for use is hydrofluoric acid, nitric acid and acetate mixture, its prescription is 40%HF: 70%HNO
3: 100%CH
3COOH mixes with volume ratio at 1: 3: 8, and perhaps other has high corrosion to select the etchant solution prescription of ratio to doped semiconductor materials.
Above-mentioned manufacture method, the injection energy that described ion injects is 30eV-200KeV, epitaxially grown semiconductor lamella (be the light dope of obtained MOS transistor semiconductor channel area or not doped portion) thickness is 10-50nm, and the thickness of the gate dielectric layer of growing on the semiconductor channel area is 1-10nm; The thickness of gate electrode layer is 80-150nm; The final lateral wall width that forms of gate electrode one side is 5-20nm.
Advantage of the present invention and good effect: the buried insulating layer of the SOI MOS transistor of part depletion of the present invention has concave structure, and raceway groove is positioned at recess, light dope or not doping under the gate dielectric layer of channel region top, the district's heavy doping of channel region undercut.The heavy doping of channel region can suppress the electromotive force coupling of drain terminal voltage to the source end effectively, thereby reduces the DIBL effect and the short-channel effect of device.Light dope or not doped channel regions can prevent under the nanoscale because the threshold voltage variation that the impurity fluctuation brings, simultaneously light dope or not doped channel can improve the mobility of electronics, heighten the performance of device.The technique manufacturing method of this structure devices and traditional MOSFET technology are compatible fully, and technology is simple simultaneously, has high practical value, is expected to be applied in the integrated circuit industry of nanoscale.
Description of drawings:
Fig. 1 is the process sequence diagram that forms high-doped zone on buried insulating layer;
Fig. 2 is the process sequence diagram of epitaxial growth silicon fiml on high-doped zone;
Fig. 3 is the process sequence diagram of growth gate dielectric layer;
Fig. 4 is gate electrode and sacrifices the process sequence diagram that side wall forms;
Fig. 5 is the process sequence diagram that the silicon fiml corrosion forms the silicon groove;
Fig. 6 is the process sequence diagram of the highly doped silicon layer of selective etching;
Fig. 7 is the process sequence diagram of filling the silicon groove;
Fig. 8 is the process sequence diagram that the gate electrode side wall forms and the source leakage is injected for the second time;
Among the figure:
1-silicon substrate 2-oxygen buried layer
3-silicon fiml 4-epitaxial growth silicon fiml
5-gate dielectric layer 6-silicon nitride side wall
7-polysilicon 8-silicon groove
9-cavity 10-silicon dioxide
11-silicon dioxide side wall 12-source region
The 13-drain region
Embodiment:
Following specific embodiment helps to understand the features and advantages of the present invention, but enforcement of the present invention never only is confined to described embodiment.
One specific embodiment of manufacture method of the present invention comprises extremely processing step shown in Figure 8 of Fig. 1:
1. as shown in Figure 1, used soi wafer adopts silicon substrate (1), and the crystal orientation of the monocrystalline silicon membrane (3) on the oxygen buried layer (2) is (100), silicon fiml (3) is initially light dope, carry out ion and inject on silicon fiml (3), the energy that ion injects is 80KeV, and implanting impurity ion is BF
2, make the silicon fiml (3) on the oxygen buried layer (2) form highly doped.
2. as shown in Figure 2, adopt the new epitaxial growth silicon fiml (4) of growth technology extension one deck on highly doped silicon fiml (3), this layer epitaxially grown silicon fiml (4) does not mix or is low-doped, and thickness is 10-50nm.
3. as shown in Figure 3, growth gate dielectric layer (5), gate dielectric layer (5) is a silicon dioxide, its thickness is 1-5nm.The formation method of gate medium can also be one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD).
4. deposit gate electrode layer polysilicon (7) and sacrificial dielectric layer silicon nitride as shown in Figure 4; The thickness of polysilicon layer is 80-150nm, and the thickness of silicon nitride layer is 20-40nm.Adopt the polysilicon layer and the sacrificial dielectric layer silicon nitride of conventional cmos technology photoetching and the deposit of etching institute, then use back quarter (etch-back) technology to form width in the gate electrode both sides be the silicon nitride side wall (6) of 25-150nm, be the exposed part that mask corrosion falls the grid silicon dioxide layer with gate electrode and silicon nitride side wall (6) figure that forms.
5. be that mask adopts the reactive ion etching RIE method corrosion part that silicon fiml was spilt to form silicon groove (8) with silicon nitride side wall (6) as shown in Figure 5; The degree of depth of silicon groove (8) is 20-80nm, arrives highly doped silicon layer.Owing to silicon groove (8) is that dielectric layer silicon nitride with the gate electrode both sides is that mask forms, so its structure and gate electrode are self aligned.
6. as shown in Figure 6, adopt selective etching technology corroded high doping silicon layer, etchant solution is hydrofluoric acid, nitric acid and acetate mixture, fills a prescription to be 40%HF: 70%HNO
3: 100%CH
3COOH mixes with volume ratio at 1: 3: 8, and by the control etching time, when arriving the grid boundary, corrosion stops, and forms the cavity (9) up to the grid border.
7. as shown in Figure 7, adopt CVD method deposit layer of silicon dioxide (10), leak beneath silicon groove (8) and cavity (9) in order to the source that the filling corrosion brings, the insulating barrier under the leakage of formation source returns and removes surperficial silicon dioxide (10) quarter.
8. as shown in Figure 8, hot phosphoric acid corrosion falls the sacrificial dielectric silicon nitride (6) of all gate electrode tops and both sides, and another thickness of heat growth is the silica dioxide medium layer of 5-20nm, and as resilient coating, low energy ion injects the tagma part of dope gate electrode and gate electrode both sides, form doping source region (12) and drain region (13) of dope gate electrode and device respectively, dopant is a phosphorus.The described ion of last anisotropic dry etch injects resilient coating to form silicon dioxide side wall (11) and the source region of device and drain region are exposed on the surface of gate electrode both sides.According to circumstances, the source leak can adopt epitaxy method to form the source-drain structure of raising.
Enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make the MOS transistor of described partial depletion SOI structure.
Claims (10)
1. the MOS transistor of a partial depletion SOI structure comprises a gate electrode, a gate dielectric layer, a gate electrode side wall medium layer, semiconductor channel region, a source region, a drain region, a buried insulating layer, semi-conductive substrate; Described buried insulating layer has concave structure on Semiconductor substrate; Described semiconductor channel area, source region and drain region are positioned on the buried insulating layer, semiconductor source region and drain region embed two projection inboards of concave structure buried insulating layer respectively, semiconductor channel area is positioned at buried insulating layer concavity place, its top light dope or not doping, bottom heavy doping; Described semiconductor channel area links to each other with the drain region with described source region respectively in the part at gate electrode two ends; Described gate dielectric layer is positioned on the semiconductor channel area; Described gate electrode is positioned on the gate dielectric layer; Described gate electrode side wall medium layer is positioned at the gate electrode both sides on gate dielectric layer.
2. MOS transistor as claimed in claim 1, it is characterized in that, the light dope of described semiconductor channel area or not doped portion thickness be 10-50nm, the thickness of gate dielectric layer is 1-10nm, the thickness of gate electrode layer is 80-150nm, and gate electrode side wall medium layer width is 5-20nm.
3. the manufacture method of the MOS transistor of a partial depletion SOI structure may further comprise the steps:
(1) semi-conducting material of employing soi structure, it has one deck buried insulating layer, the layer of semiconductor film, the layer of semiconductor substrate, buried insulating layer is between semiconductive thin film and Semiconductor substrate, and the photoetching isolation is formed with the source region, injects by ion to form a high doping semiconductor thin layer;
(2) adopt growth technology to form the new semiconductor lamella of one deck on highly doped semiconductor film layer, new semiconductor lamella does not mix or is low-doped;
(3) growth gate dielectric layer;
(4) deposit gate electrode layer, etching forms gate figure;
(5) side wall medium layer is sacrificed in deposit, and Hui Kehou forms side wall in the gate electrode both sides, be that mask corrosion falls gate dielectric layer with gate electrode and the side wall figure that forms, and both sides are not exposed on doped semiconductor thin layer surface;
(6) corrode the not doped semiconductor thin layer that is exposed, stop corrosion during to high-doped zone;
(7) selective etching high-doped zone stops corrosion when arriving grid covering place;
(8) deposit dielectric is filled the cavity that etching forms, and returns and carves the dielectric of removing the surface;
(9) erode after the sacrificial dielectric layer at gate electrode both sides and top deposit again or thermal oxide growth and form another film dielectric layer;
(10) ion implantation doping source-drain area and gate electrode return then to engrave and state film dielectric layer to form new gate electrode side wall, and according to circumstances, the source leak can adopt epitaxy method to form the source-drain structure of raising;
(11) enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make described MOS transistor.
4. manufacture method as claimed in claim 3 is characterized in that, the semiconductor substrate materials in the described step (1) is selected from: Si, Ge, SiGe, GaAs or other II-VI, the binary or the ternary semiconductor of III-V and IV-IV family.
5. manufacture method as claimed in claim 3 is characterized in that, the gate dielectric material in the described step (3) is selected from: silicon dioxide, hafnium oxide, hafnium nitride.
6. manufacture method as claimed in claim 3 is characterized in that, the method for described step (3) growth gate dielectric layer is selected from one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition, physical vapor deposition.
7. manufacture method as claimed in claim 3 is characterized in that, sacrifices that the side wall medium layer material is selected from silicon nitride, silester or other all has high corrosion to select the thin-film material of ratio with silicon and silica in the described step (5).
8. manufacture method as claimed in claim 3 is characterized in that, the etchant solution that the selective etching in the described step (7) is selected for use is selected the etchant solution of ratio for doped semiconductor materials there being high corrosion.
9. manufacture method as claimed in claim 8 is characterized in that, described etchant solution is hydrofluoric acid, nitric acid and acetate mixture, and its prescription is 40%HF: 70%HNO
3: 100%CH
3COOH mixes with volume ratio at 1: 3: 8.
10. manufacture method as claimed in claim 3, it is characterized in that, the injection energy that described ion injects is 30eV-200KeV, epitaxially grown semiconductor film layer thickness is 10-50nm, the thickness of the gate dielectric layer of growing on the semiconductor channel area is 1-10nm, the thickness of gate electrode layer is 80-150nm, and the final lateral wall width that forms of gate electrode one side is 5-20nm.
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| CNB2006100725069A CN100440537C (en) | 2006-04-11 | 2006-04-11 | Partial consumption SOI MOS transistor and making method |
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|---|---|---|---|
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100527371C (en) * | 2007-09-14 | 2009-08-12 | 北京大学 | Portion exhausted SOI MOS transistor preparation method |
| CN100561752C (en) * | 2007-10-23 | 2009-11-18 | 北京大学 | A kind of preparation method of quasi dual-gate MOS transistor |
| CN102157379A (en) * | 2010-02-11 | 2011-08-17 | 中国科学院微电子研究所 | High-performance semiconductor device and manufacturing method thereof |
| CN102412180A (en) * | 2010-09-25 | 2012-04-11 | 中国科学院微电子研究所 | Semiconductor on insulator (SOI) substrate, semiconductor device with SOI substrate and forming methods for SOI substrate and semiconductor device |
| CN103094343A (en) * | 2011-11-03 | 2013-05-08 | 台湾积体电路制造股份有限公司 | MOSFET structure with T-shaped epitaxial silicon channel |
| CN101599464B (en) * | 2008-06-06 | 2013-10-16 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor device |
| CN109314133A (en) * | 2016-06-30 | 2019-02-05 | 英特尔公司 | Integrated circuit die with rear road transistor |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01307268A (en) * | 1988-06-06 | 1989-12-12 | Nippon Telegr & Teleph Corp <Ntt> | Mis type transistor |
| JP2975213B2 (en) * | 1992-05-01 | 1999-11-10 | 川崎製鉄株式会社 | MOS memory device |
| JP2780670B2 (en) * | 1995-04-14 | 1998-07-30 | 日本電気株式会社 | Manufacturing method of epitaxial channel MOS transistor |
| JP3265569B2 (en) * | 1998-04-15 | 2002-03-11 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| CN100356528C (en) * | 2005-08-31 | 2007-12-19 | 北京大学 | Method for making MOS transistor with source-drain on insulating layer |
| CN100356527C (en) * | 2005-08-31 | 2007-12-19 | 北京大学 | Method for making MOS transistor with source-drain on insulating layer |
-
2006
- 2006-04-11 CN CNB2006100725069A patent/CN100440537C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100527371C (en) * | 2007-09-14 | 2009-08-12 | 北京大学 | Portion exhausted SOI MOS transistor preparation method |
| CN100561752C (en) * | 2007-10-23 | 2009-11-18 | 北京大学 | A kind of preparation method of quasi dual-gate MOS transistor |
| CN101599464B (en) * | 2008-06-06 | 2013-10-16 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor device |
| CN102157379A (en) * | 2010-02-11 | 2011-08-17 | 中国科学院微电子研究所 | High-performance semiconductor device and manufacturing method thereof |
| CN102412180A (en) * | 2010-09-25 | 2012-04-11 | 中国科学院微电子研究所 | Semiconductor on insulator (SOI) substrate, semiconductor device with SOI substrate and forming methods for SOI substrate and semiconductor device |
| CN103094343A (en) * | 2011-11-03 | 2013-05-08 | 台湾积体电路制造股份有限公司 | MOSFET structure with T-shaped epitaxial silicon channel |
| US9653545B2 (en) | 2011-11-03 | 2017-05-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | MOSFET structure with T-shaped epitaxial silicon channel |
| CN109314133A (en) * | 2016-06-30 | 2019-02-05 | 英特尔公司 | Integrated circuit die with rear road transistor |
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| CN100440537C (en) | 2008-12-03 |
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