CN1828573A - Multiple-CPU system and its control method - Google Patents
Multiple-CPU system and its control method Download PDFInfo
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Abstract
The disclosed multi-CPU system comprises: a main CPU, at least one auxiliary CPU, the connected interface devices for communication, and the management unit coupled between the main CPU and auxiliary CPU to manage auxiliary CPU. The opposite control method comprises: initialing the main CPU while Forbidding auxiliary CPU; enabling the auxiliary CPU to enter normal state; if failed, only resetting the auxiliary CPU; or else restarting the system if the main CPU failed. This invention can improve system reliability.
Description
Technical field
The present invention relates to communication, technical field of electronic equipment, be specifically related to a kind of multi-CPU system and control method thereof.
Background technology
Popular method is OO modular design in the soft project now, and its thought is that the system divides with complexity becomes the single module of task, helps the extensive software of the common exploitation of many people.Industrial computer also adopts modular design mostly, can form application system easily according to the industry control concrete condition.The also available single-chip microcomputer of little application system constitutes as the programming device module, is about to system divides and becomes the single module of task, and each device blocks programming is simple, dependable performance, and strong anti-interference performance, thus save design and programming time greatly.
Equally, in telecommunication apparatus, in order to strengthen the processing power of veneer, usually a plurality of CPU of design on same veneer make CPU disposable plates more than.Extraneous communication data is sent to each CPU by interface device, and each CPU carries out work such as related service processing alone.Respectively from being separate between cpu system and the main CPU system, main CPU system to from cpu system without any control ability.
Multi-CPU system as shown in Figure 1 is made up of from processor CPU1, CPU2 and CPU3 primary processor CPU0 and 3.Wherein,
CPU0 is the primary processor of veneer, the interface device on the control veneer etc.Behind the Board Power up, CPU0 starts, and the docking port device carries out initialization operation.After initialization was finished, CPU0 promptly entered normal operating conditions.
The control ability that does not have the docking port device from processor CPU1, CPU2, CPU3.Behind Board Power up, CPU1, CPU2, CPU3 be independent startup separately.At this moment, because CPU0 do not finish initialization as yet, CPU1, CPU2, CPU3 can't correspondence with foreign countries, and therefore before the CPU0 initialization was finished, CPU1, CPU2, CPU3 can reset repeatedly.And these 3 reset the process that starts at every turn from CPU, the capital carry out and interface device between the initialization of physical interface, because a lot of interface devices all have strict requirement to the startup sequential of institute's connection device, at random initialization procedure is difficult to satisfy this requirement between this a plurality of devices.
As seen, owing to can not link up mutually between each CPU, host CPU is unclear to the state from CPU, therefore when certain when the CPU existence may cause the unusual fault of communication link, can't make it withdraw from service, maybe can't keep regular traffic thereby cause other CPU on the veneer also can't keep operate as normal.This malfunction is in the bus-type interconnection system, and for example a plurality of CPU show particularly evidently when UTOPIA (universal test and the operating physical interface) bus interconnection, and promptly under the situation that a CPU resets repeatedly, error code can appear in the transmitting-receiving of other CPU.
Summary of the invention
The purpose of this invention is to provide a kind of multi-CPU system, can not link up between each CPU, thereby cause the shortcoming of system reliability difference to overcome in the existing multi-CPU system.
Another object of the present invention provides a kind of many CPU control method, to overcome the shortcoming of host CPU to not controlling from CPU in the prior art, coordinates the operation of each cpu system, improves system reliability.
Technical scheme provided by the invention is as follows:
A kind of multi-CPU system comprises: host CPU, at least one from CPU, respectively with described host CPU and the interface device that respectively links to each other from CPU, be used for communicating with described system outside, also comprise:
Administrative unit is coupled in described host CPU respectively and respectively from CPU, is used for according to the order management of described host CPU respectively from the duty of CPU.
Alternatively, described administrative unit specifically comprises:
The steering logic unit is coupled in described host CPU respectively and respectively from CPU, is used for order according to described host CPU to respectively carrying out reset operation from CPU; Interface between described host CPU and the described steering logic unit is a Microprocessor Interface; Described steering logic unit by reset signal to respectively carrying out reset operation from CPU.
House dog and reset circuit are coupled in described host CPU and described steering logic unit respectively, be used for to described host CPU reset and by described steering logic unit to respectively from the CPU control that resets.
Alternatively, described administrative unit specifically comprises:
The communication logic unit is coupled in described host CPU respectively and respectively from CPU, is used for according to the order control of described host CPU respectively from the duty of CPU; Described host CPU communicates by Microprocessor Interface and described communication logic unit; Described communication logic unit by Microprocessor Interface with respectively communicate from CPU.
House dog and reset circuit are coupled in described host CPU respectively and respectively from CPU, are used for described host CPU and respectively reset separately from CPU.
A kind of multi-CPU system control method, described system comprises: host CPU, at least one from CPU, respectively with host CPU and the interface device that respectively links to each other from CPU, be used for communicating with described system outside, it is characterized in that described method comprises step:
A, the described host CPU of initialization are forbidden simultaneously respectively from CPU;
B, after described host CPU initialization is finished, enable respectively to make described system enter normal operating conditions from CPU;
C, when described when CPU breaks down, it is described from CPU to reset separately;
D, when described host CPU breaks down, restart described system.
Preferably, described method also comprises:
Described host CPU regularly detects respectively the duty from CPU;
Described when CPU enters reset mode when detecting, control and describedly carry out reset operation from CPU.
Preferably, described method also comprises:
Describedly be in reset mode when described host CPU is consecutively detected in the given time, place illegal state from CPU described from CPU.
Alternatively, when CPU breaks down, reset described separately when described from CPU by house dog and reset circuit.
By above technical scheme provided by the invention as can be seen, the present invention is on existing multi-CPU system basis, increased host CPU to control function from CPU, by System Management Bus control the CPU of each operation power-on and power-off, reset etc., perhaps coordinate operation between each CPU by logic MPI interface communication, and host CPU can be at any time to detecting from the CPU current state, when continuous several times occurring from CPU and reset, take corresponding measure, no longer make its startup that resets, reduced influence, improved reliability of system operation other cpu systems.
Description of drawings
Fig. 1 is that existing multi-CPU system loads synoptic diagram;
Fig. 2 a is a bus interconnection type multi-CPU system synoptic diagram;
Fig. 2 b is point-to-point multi-CPU system synoptic diagram;
Fig. 2 c is a star multi-CPU system synoptic diagram;
Fig. 3 is a system principle diagram of the present invention;
Fig. 4 is the system of the present invention first embodiment theory diagram;
Fig. 5 is the system of the present invention second embodiment theory diagram;
Fig. 6 is the realization flow figure of the inventive method.
Embodiment
Core of the present invention is in multi-CPU system, increase host CPU to respectively from the control function of CPU, by System Management Bus control the CPU of each operation power-on and power-off, reset etc., perhaps coordinate operation between each CPU by logic MPI (Microprocessor Interface) interface communication, and host CPU can be at any time to detecting from the CPU current state, when continuous several times occurring from CPU and reset, take corresponding measure, no longer make its startup that resets, reduced influence, improved reliability of system operation other cpu systems.
The present technique field personnel know, multi-CPU system can have multiple connected mode, such as: bus interconnection mode, point-to-point interconnection and star interconnection etc.
Bus interconnection type multi-CPU system shown in Fig. 2 a, such as, the UTOPIA II of ATM (asynchronous transfer mode) (Universal Test ﹠amp; Operations PHY Interface for ATM, Universal Test ﹠ Operations PHY Interface for ATM) bus, can articulate a UTOPIA main equipment and a plurality of UTOPIA slave unit on the bus.
Point-to-point interconnection situation shown in Fig. 2 b is meant that two equipment directly dock, and for example the interface between the MAC of Ethernet interface (medium Access Control) device and PHY (Physical layer) device is to dock one by one each other, does not have other equipment.
Star interconnection situation shown in Fig. 2 c, a plurality of ports of a central apparatus link to each other with the port of slave unit respectively, for example, the annexation between the Lanswitch of Ethernet (LAN switch) and each ethernet nic.Each all is independently between connecting, and does not have influence each other.
To these different connected modes, can increase the control of main equipment by the present invention to each slave unit, coordinate the duty between each equipment.
In order to make those skilled in the art person understand the present invention program better, the present invention is described in further detail below in conjunction with drawings and embodiments.
Reference system principle diagram of the present invention shown in Figure 3: primary processor CPU0 is except the peripheral hardware to oneself manages, also manage other operations from processor: CPU1, CPU2 and CPU3 by administrative unit S1, interface device S2 is used for communicating with the system outside, the receiving system external data flows, and by data bus this data stream is sent to corresponding processor; Perhaps that each processor and outside is mutual data stream is dealt on the data bus.Each processor and interface device independently carry out data interaction.
Respectively manage by primary processor CPU0 from the reseting pin of processor, rather than by the startup that directly resets that powers on.Primary processor CPU0 will respectively directly move reset mode to from the reseting pin of processor by administrative unit S1 in the electrifying startup process, after primary processor CPU0 finishes a series of peripheral hardware initialization and setting operation, just make respectively to start from processor.
With reference to Fig. 4, Fig. 4 is the system of the present invention first embodiment theory diagram:
Steering logic cell S 11 respectively with primary processor CPU0 with respectively link to each other from processor, be used for order according to primary processor CPU0 to respectively carrying out reset operation from processor;
House dog links to each other with steering logic cell S 11 with primary processor CPU0 respectively with reset circuit S12, be used for primary processor CPU0 and respectively reset from processor, to respectively finishing by steering logic cell S 11 from resetting of processor, concrete operations are to carry out respectively from the reset operation of CPU according to the reset signal that house dog and reset circuit S12 provide.
Primary processor CPU0 communicates by MPI (Microprocessor Interface) interface and steering logic cell S 11, finishes respectively from the bookkeeping of processor running status.
The present technique field personnel know, the MPI interface is the be connected basic interface of device of processor operations, comprising: data line, address wire and control line, its function comprise certain address write data, from certain address read data, and response input look-at-me etc.By the MPI interface, primary processor CPU0 can write order in the register of steering logic cell S 11, the steering logic unit according to the content of this register to respectively controlling from processor; Equally, primary processor CPU0 can obtain other duties from processor by this interface.
The course of work of system of the present invention is as follows:
When 1, Board Power up started, veneer house dog and reset circuit at first triggered the electrifying startup of CPU0, and at this moment the reset circuit of CPU1, CPU2, CPU3 does not provide reset signal by the steering logic unit controls, and these 3 CPU all are in not starting state;
2, after the CPU0 initialization is finished, by MPI interface control steering logic unit, make the steering logic unit to required startup issue reset signal from processor, trigger the startup that resets of CPU1, CPU2, CPU3, make respectively and enter normal operating conditions from processor;
3, in system's operational process, CPU0 regularly sends feeding-dog signal to house dog and reset circuit.When CPU0 breaks down need reset the time, CPU0 stops dog feeding operation, house dog and reset circuit send reset signal after overtime, this reset signal sends to CPU0 and steering logic unit simultaneously, CPU0 finishes reset operation, steering logic is then moved CPU1, CPU2, CPU3 to reset mode again, after waiting for CPU 0 initialization is finished, enables CPU1, CPU2, CPU3 again;
4, steering logic provides watchdog function respectively to CPU1, CPU2, CPU3, the software of these 3 CPU all carries out the timing dog feeding operation, when a certain CPU operation goes wrong, when software can't be fed dog, the steering logic WatchDog Timer is overtime, then carry out this CPU is moved to the operation of reset mode, this CPU is placed DISABLE (forbidding) state, the visit of isolated its docking port device; Simultaneously, the CPU that breaks down is write corresponding register;
5, CPU0 inquires about (regularly or at any time) by the MPI interface to the steering logic unit, reads respectively the register from the processor correspondence, thereby obtains respectively from the current state of processor: in running order still reset mode.Detect when in the CPU0 operate as normal and a certainly enter the attitude that resets from CPU, then send this reset signal from CPU to the steering logic unit, by the steering logic unit this being resetted from CPU restarts operation;
If 6 CPU0 at the appointed time are consecutively detected repeatedly in the section and a certainly restart operation (for example be consecutively detected above the time that resets for 5 times less than 1 minute) from resetting of CPU, then judge and to have fault from CPU, can will should withdraw from service automatically from CPU, such as moving this CPU to reset mode by the steering logic unit, no longer it being resetted restarts operation, avoids this to reset repeatedly from CPU and restarts the docking port device and system impacts.
As seen, in this embodiment, when primary processor CPU0 resets, will draw extremely from CPU, and can not move from CPU software by steering logic.
With reference to Fig. 5, Fig. 5 is the system of the present invention second embodiment theory diagram:
Communication logic cell S 21 respectively with primary processor CPU0 with respectively link to each other from processor, be used for according to the order of primary processor CPU0 control respectively from the duty of CPU, house dog and reset circuit S12 respectively with primary processor CPU0 with respectively link to each other from processor, be used for primary processor CPU0 and respectively reset separately from processor, promptly the reset signal between each processor is independently.
Primary processor CPU0 communicates by MPI interface and communication logic cell S 21, finishes respectively from the bookkeeping of processor running status, and is same, communication logic cell S 21 with respectively also undertaken by the MPI interface from communicating by letter between the processor.
The course of work of system of the present invention is as follows:
When 1, Board Power up started, veneer house dog and reset circuit at first triggered the electrifying startup of CPU0, at this moment, CPU1, CPU2, CPU3 are also provided reset signal simultaneously, and these 3 CPU also enter starting state simultaneously;
2, in the communication logic unit, for each from CPU, all defined a Control on Communication position CS_bit, be used for realizing the communication between CPU0 and CPU1, CPU2, the CPU3, be respectively CS_bit1, CS_bit2, CS_bit3 corresponding to CPU1, CPU2, CPU3.When cpu reset starts, should at first be changed to 0 when a certain, should start-up course, read this CS_bit from CPU then from CPU by the MPI interface CS_bit that it is corresponding, if it is always 0, then should be from operation downwards of CPU;
3, primary processor CPU0 regularly reads from the communication logic unit respectively from the CS_bit position of CPU by the MPI interface, and when this position was 0, then CPU0 knew that this has taken place once to reset from CPU.CPU0 is written as 1 with this position, and then corresponding can move downwards from CPU.If CPU0 does not rewrite this position, then should be in waiting status all the time, not operation downwards from CPU.
4, in system's operational process, CPU0 and respectively respectively regularly send feeding-dog signal to house dog and reset circuit from CPU.When CPU0 breaks down need reset the time, CPU0 stops dog feeding operation, and house dog and reset circuit send reset signal in overtime back to CPU0, also send reset signal to other from CPU simultaneously, and each cpu reset is restarted.The communication logic unit also is reset simultaneously, be clearly 0 all to control bit CS_bit respectively in the communication logic unit from CPU, so respectively after startup, just be in the running status of waiting for that its corresponding CS_bit changes, at this moment can not carry out the visit of docking port device from CPU.Deng CPU0 finish reset and necessary initialization after, revise corresponding CS_bit from CPU, make and should can move downwards from CPU.
5, when some the breaking down among CPU1, CPU2, the CPU3, house dog and reset circuit send reset signal to this from CPU in overtime back, trigger this startup that resets from CPU.When being somebody's turn to do from cpu reset, at first the CS_bit with correspondence is changed to 0, after waiting for CPU 0 is rewritten this position then, enters follow-up normal operating conditions;
6, thereby CPU0 reads in the communication logic unit respectively from the CS_bit of CPU correspondence by the MPI interface and obtains respectively state from CPU.CPU0 can allow corresponding to carry out subsequent operation from CPU by rewriting CS_bit.
If 7 CPU0 at the appointed time are consecutively detected repeatedly in the section and a certainly restart operation (for example be consecutively detected and surpass time of resetting for 5 times less than 1 minute) from resetting of CPU, then judge and should have fault from CPU, can will be somebody's turn to do automatically and withdraw from service from CPU.When CPU starts, need from the communication logic unit, read control information, determine whether downwards operation of CPU by this control information.This control information is powering on and house dog is overtime when resetting for not moving downwards, and CPU0 can change it into downward operation by the MPI interface, if host CPU wishes that it withdraws from service, then this control word is not written as downward operation and gets final product.No longer it being resetted restarts operation, avoids this to reset repeatedly from CPU and restarts the docking port device and system impacts.
As seen, reset fully from CPU in this embodiment, software can bring into operation after resetting, and just needs in the software running process in the obtaining communication logical block from the state of the register of CPU correspondence, allow to walk downwards just to walk downwards, otherwise be in a circular wait state.
In the above-described embodiments, be that example has been done detailed description to the present invention mainly with bus-type interconnection multi-CPU system, the present invention is equally applicable to other interconnected type systems.
With reference to Fig. 6, Fig. 6 shows the realization flow of the inventive method:
At first, in step 601: during system start-up, the initialization host CPU is forbidden simultaneously respectively from CPU.
Step 602: after the host CPU initialization is finished, enable respectively to make system enter normal operating conditions from CPU.
Step 603:, reset this separately from CPU when when CPU breaks down.
Such as, reset separately from CPU by house dog and reset circuit; Perhaps when should by steering logic it being changed to illegal state when CPU breaks down.
Step 604: when host CPU breaks down, restart this system.
Can monitor host CPU separately by house dog and reset circuit.The present technique field personnel know, watchdog circuit is an independently timer in fact, a timer control register is arranged, can setting-up time (opening dog), want set (feeding dog) after time of arrival, promptly send feeding-dog signal to watchdog circuit, if in setting-up time, do not receive feeding-dog signal, then think program fleet or deadlock, at this moment, will send reset instruction, indicate monitored cpu reset.
In the methods of the invention, can also regularly detect respectively duty by host CPU from CPU, such as, by steering logic monitoring and record respectively from the duty of CPU, and host CPU is regularly inquired about to steering logic by the MPI interface, obtain respectively actual working state, thereby decision is to this bookkeeping from CPU from CPU.
When detecting certain when CPU enters reset mode, control should be carried out reset operation from CPU.If being consecutively detected this in the given time, host CPU is in reset mode from CPU, then judge and to have fault from CPU, can will be somebody's turn to do from CPU by steering logic and place illegal state this moment: send the order of forbidding this CPU to steering logic, steering logic is operated from CPU forbidden according to this order.Such as, by reset signal is dragged down all the time, do not uprise.
Though described the present invention by embodiment, those of ordinary skills know, the present invention has many distortion and variation and do not break away from spirit of the present invention, wish that appended claim comprises these distortion and variation and do not break away from spirit of the present invention.
Claims (11)
1, a kind of multi-CPU system comprises: host CPU, at least one from CPU, respectively with described host CPU and the interface device that respectively links to each other from CPU, be used for communicating with described system outside,
It is characterized in that described system also comprises:
Administrative unit is coupled in described host CPU respectively and respectively from CPU, is used for according to the order management of described host CPU respectively from the duty of CPU.
2, multi-CPU system according to claim 1 is characterized in that, described administrative unit specifically comprises:
The steering logic unit is coupled in described host CPU respectively and respectively from CPU, is used for order according to described host CPU to respectively carrying out reset operation from CPU;
House dog and reset circuit are coupled in described host CPU and described steering logic unit respectively, be used for to described host CPU reset and by described steering logic unit to respectively from the CPU control that resets.
3, multi-CPU system according to claim 2 is characterized in that, the interface between described host CPU and the described steering logic unit is a Microprocessor Interface.
4, multi-CPU system according to claim 2 is characterized in that, described steering logic unit by reset signal to respectively carrying out reset operation from CPU.
5, multi-CPU system according to claim 1 is characterized in that, described administrative unit specifically comprises:
The communication logic unit is coupled in described host CPU respectively and respectively from CPU, is used for according to the order control of described host CPU respectively from the duty of CPU;
House dog and reset circuit are coupled in described host CPU respectively and respectively from CPU, are used for described host CPU and respectively reset separately from CPU.
6, multi-CPU system according to claim 5 is characterized in that, described host CPU communicates by Microprocessor Interface and described communication logic unit.
7, multi-CPU system according to claim 5 is characterized in that, described communication logic unit by Microprocessor Interface with respectively communicate from CPU.
8, a kind of multi-CPU system control method, described system comprises: host CPU, at least one from CPU, respectively with host CPU and the interface device that respectively links to each other from CPU, be used for communicating with described system outside, it is characterized in that described method comprises step:
A, the described host CPU of initialization are forbidden simultaneously respectively from CPU;
B, after described host CPU initialization is finished, enable respectively to make described system enter normal operating conditions from CPU;
C, when described when CPU breaks down, it is described from CPU to reset separately;
D, when described host CPU breaks down, restart described system.
9, multi-CPU system control method according to claim 8 is characterized in that, described method also comprises:
Described host CPU regularly detects respectively the duty from CPU;
Described when CPU enters reset mode when detecting, control and describedly carry out reset operation from CPU.
10, multi-CPU system control method according to claim 9 is characterized in that, described method also comprises:
Describedly be in reset mode when described host CPU is consecutively detected in the given time, place illegal state from CPU described from CPU.
11, according to Claim 8 to 10 each described multi-CPU system control methods, it is characterized in that described step C is specially: when CPU breaks down, reset described separately from CPU by house dog and reset circuit when described.
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| CN111884892A (en) * | 2020-06-12 | 2020-11-03 | 苏州浪潮智能科技有限公司 | Data transmission method and system based on shared link protocol |
| CN114750774A (en) * | 2021-12-20 | 2022-07-15 | 广州汽车集团股份有限公司 | Safety monitoring method and automobile |
| CN114750774B (en) * | 2021-12-20 | 2023-01-13 | 广州汽车集团股份有限公司 | Safety monitoring method and automobile |
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