CN1788348A - Via and trench structures for semiconductor substrates bonded to metallic substrates - Google Patents
Via and trench structures for semiconductor substrates bonded to metallic substrates Download PDFInfo
- Publication number
- CN1788348A CN1788348A CN 200480006860 CN200480006860A CN1788348A CN 1788348 A CN1788348 A CN 1788348A CN 200480006860 CN200480006860 CN 200480006860 CN 200480006860 A CN200480006860 A CN 200480006860A CN 1788348 A CN1788348 A CN 1788348A
- Authority
- CN
- China
- Prior art keywords
- metal substrate
- compound semiconductor
- thickness
- substrate
- semiconductor materials
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
A compound semiconductor substrate, such as a GaAs substrate, is eutectically bonded to a metallic substrate (400). The semiconductor substrate is optionally thinned, and vias or trenches (601) are formed from the front side for making easily aligned interconnects to the metal substrate (400). The mechanical support given by the metallic substrate (400) permits the vias or trenches (601) to be any shape. Trenches (601) can surround a particular circuit element, to provide thermal isolation or heat spreading, or (in combination with metallic air bridges) to provide electromagnetic screening. Trench structures (601) also provide lower impedance ground connections at very high frequencies, in comparison to standard via holes. The metallic substrate (400) can be used as a ground plane or as a heat sink.
Description
The cross reference of related application
The application submitted on March 13rd, 2003, require the U.S. Patent application No.10/389 of Australian temporary patent application No.PS1122 priority that submit, that transfer same assignee on March 14th, 2002, the part continuation application of 278 (acting on behalf of case mark No.21498-000210US) is contained in this with its content by reference.
Background technology
Relate generally to of the present invention is produced substrate.More specifically, the invention provides a kind of method and the device of Semiconductor substrate that be used to improve with the formation advanced semiconductor devices.As just example, the present invention has been applied to be used for the metal substrate of production advanced semiconductor devices, and it comprises a plurality of panels and/or the piece (tile) of binding (bonded) to this substrate.But, recognize that the present invention has the wideer scope of application far away.
Along with technological progress, semiconductor manufacturers continues efforts be made so that with very large wafer and to reduce the cost of single semiconductor device thus to realize large-scale production.Usually, the silicon wafer piece can easily be grown up to the wafer that is enough to be cut into 12 inches of diameters.These 12 inches wafers are produced, are used for the single crystal silicon material of various applications.Though this monocrystalline silicon has many advantages, but still there are many deficiencies.
Many conventional industries more and more depend on the compound semiconductor device that is made by for example compound semiconductor of GaAs, indium phosphide and gallium nitride.Regrettably, the compare circuit that made by Si semiconductor of the integrated circuit that is made by these semiconductive compound is still expensive.This cost price difference is mainly owing to separately material cost and wafer process cost.Also there is other restriction in compound semiconductor materials.
The easier damage of compound semiconductor wafer.For example, they are more frangible than conventional silicon single crystal wafer.Compare with the monocrystalline silicon crystal block that growth is big, the big compound semiconductor materials crystal block of growing is extremely difficult.The maximum gauge of the compound semiconductor wafer of the GaAs of commodity production, indium phosphide and gallium nitride is respectively 6 inches, 4 inches and 2 inches in conventional commercialization.
Bigger compound semiconductor wafer is desired.Regrettably, the wafer of larger diameter is difficult to make efficiently.Promptly enable to produce bigger compound semiconductor materials crystal block, the major diameter compound semiconductor wafer of handling gained generally has problems.The compound semiconductor wafer of desired thickness and diameter is extremely frangible, breaks easily.At this moment, because the fragility of these semiconducting compounds, bigger wafer generally can break.Therefore, propose some technology and used the epitaxial growth layer, produced bigger compound semiconductor wafer.
Only as an example, the conventional method of making the compound semiconductor chip can be summarised as following step (i)-(vii).
(i) growing epitaxial device layer on single crystalline substrate.
(ii) use the dielectric layer and the metal level of these epitaxial loayers of photoetching technique patterning and other deposition.
(iii) after finishing positive technology, wafer face is attached on the interim support substrates down.
(iv) by mechanical polishing being carried out at the back side or brighten thins wafer.
(v) form " through hole " in substrate, these through holes provide and have connected the path that the back side and suitable front connect lead-in wire.
(vi) depositing metallic films is providing ground plane on chip back surface, and coating through-hole wall forms and contacts thereby connect lead-in wire with the front.
(vii) wafer is cut into each chip.
In above conventional method, in step (i), (ii) and (iii) in the process, wafer is thick 625 μ m usually, have enough mechanical strengths and come to avoid breaking by handled.Step (iv) in, usually wafer is thinned down to thick about 50-100 μ m.Thin wafer and have many advantages, as:
(i) reduced the degree of depth (and size) of through hole, and the stray inductance relevant with through hole;
(ii) will arrive the back side that is connected with hot pond (heat sink) usually from the heat conduction of front device; And
Prevented that (iii) the electromagnetism in the substrate shakes under high frequency.
The compound semiconductor wafer of processing through thinning often is difficult, and compound semiconductor wafer generally (iv) breaks later in step.The cost of breaking is huge, because most of treatment step (step (i)-(iii)) is finished.The fragility of compound semiconductor materials also causes the chip device of gained to break, and has limited the larger sized practical chip design of using compound semiconductor materials.At this moment, it is unactual efficiently to make larger sized compound semiconductor materials.
In the compound semiconductor wafer processing that routinizes, also require through hole that some the earthed circuit element on the front wafer surface is connected with the ground plane at the back side.Generally, from the chip back surface to the facade element, come these through holes of etching.There is some restriction in the through hole of handling compound semiconductor wafer.Owing to the parts of wafer one side need be aimed at the corresponding component of wafer opposite side, often be encountered difficulties.Therefore the alignment-tolerance of these through holes is relatively poor.In addition, often to limit the quantity and the shape of through hole, because they have reduced the mechanical strength of wafer.The application particularly hereinafter, has more specifically described these and other restriction in the whole text.
Thus, need the improvement technology to produce and process semiconductor wafers.Especially, need be suitable for the technology of practicality, cost savings ground production compound semiconductor devices.
Summary of the invention
According to the present invention, provide the technology of producing substrate.More specifically, the invention provides a kind of method and the device of Semiconductor substrate that be used to improve with the formation advanced semiconductor devices.As just example, the present invention has been applied to be used for the metal substrate of production advanced semiconductor devices, and it comprises a plurality of panels and/or the piece (tile) that is attached on this substrate.But, recognize that the present invention has the wideer scope of application far away.
In one embodiment, the invention provides a kind of method that links substrate of producing.This method comprises provides metal substrate.This metal substrate has preset thickness.This method also comprises the compound semiconductor materials of first thickness linked and is layed onto on the metal substrate, and the thickness of the compound semiconductor materials of this first thickness is reduced to second thickness.This method comprises the one or more through-hole structures of formation, and the part of passing the second thickness compound semiconductor materials is up to beneath metal substrate part, thereby through-hole structure is electrically connected with metal substrate.
In interchangeable specific embodiments, the invention provides the method that a kind of production is used for the compound substrate of semiconductor device.This method comprises provides the metal substrate with first diameter and connected surfaces.This method comprises and will be layed onto on this connected surfaces in a plurality of bindings.Each piece all is coupled to the part of this connected surfaces.The shape and size that each piece had can form array configuration.This method also comprises the temperature of these a plurality of of risings and metal substrate, and forms eutectic binding (eutectic bond) between this a plurality of wherein each piece and connected surfaces part.When each piece is static basically with respect to metal substrate, carries out temperature and raise.This method forms a plurality of active devices on this wherein each piece of a plurality of, and forms a plurality of openings that pass each piece.Each opening passes the part of one of them piece, passes the eutectic linking portion again up to the metal substrate part, forms through-hole structure.In addition, this method comprises the formation interconnection layer, with this one of them active device part by this piece part, link and partly be connected with metal substrate by eutectic.The present invention also provides interconnection layer, it with one of them active device part by one of them piece part, partly be connected with metal substrate by the eutectic linking portion.
In another interchangeable specific embodiments, the invention provides a kind of method that links substrate of producing.This method comprises provides the metal substrate with predetermined thickness.This method also comprises the compound semiconductor materials of first thickness linked and is layed onto on the metal substrate, and the thickness of the compound semiconductor materials of this first thickness is reduced to second thickness.This method also partly forms the ditch district around second thickness of compound semiconductor materials.In addition, this method forms electric conducting material in this ditch district, to be isolated in compound semiconductor second thickness part and beneath metal substrate part of using electric conducting material in the ditch district.
In another interchangeable embodiment, the invention provides a kind of substrat structure that is used for high-frequency apparatus.This substrat structure comprises metal substrate, and it is as the ground plane of the high frequency multiplying arrangement that can move under greater than the 10GHz frequency.Compound semiconductor materials is attached to metal substrate.In the part of this compound semiconductor materials, form one or more through-hole structures that ground connection connects that are used for.These one or more through-hole structures are electrically connected with metal substrate.These one or more through-hole structures are configured to the reactance that provides desired, so that general ground connection benchmark (ground reference) to be provided.This general ground connection benchmark is in predetermined value.
The present invention also provides a kind of integrated circuit device structure.This integrated circuit device structure comprises the metal substrate with predetermined thickness and predetermined thermal conductivity.Certain thickness compound semiconductor materials be linked to metal substrate on cover on the surface.In the compound semiconductor materials part of this thickness, the ditch district is set, and extends to the metal substrate part.In this ditch district, form Heat Conduction Material, and be thermally coupled to the metal substrate part.This Heat Conduction Material is coupled to the compound semiconductor part of this thickness, to redistribute the heat energy between this compound semiconductor part, Heat Conduction Material and the metal substrate.
Be attached to the semiconductor piece of metal substrate by use, can obtain various advantages.This semiconductor wafer composite members does not have semiconductor piece frangible like that, therefore can handle with more extensive.As a result, by more substantial manufacturing, can realize cost savings.Especially, by using a plurality of semiconductor pieces, can handle so far by compound semiconductor wafer with any effective dimensions than the wafer manufacture of minor diameter.Therefore, the existing manufacturing equipment of handling the silicon wafer of 12 inch diameters can be used for making the compound semiconductor device that uses described semiconductor wafer complex.Other advantage also can realize in one or more embodiments, and is as follows:
1) can there be more through hole, and do not reduce the structural strength of wafer;
2) through hole can be an arbitrary shape, comprises groove, and does not reduce structural strength;
3) groove can be arranged in almost all around specific circuit or circuit element, thereby electromagnetic shielding, thermal insulation or heat radiation are provided;
4) groove can be arranged with beneath metal substrate and the metal that overarches " air bridges ", with sidewall, bottom and the top of " can " on the core that forms electromagnetic shielding respectively, should " can " can be used to circuit element and interference source are isolated.
5) can utilize easily positive technology with other positive component alignment, formation through hole and groove.
According to embodiment, can realize these one or more advantages.The application particularly hereinafter, has more specifically described these and other advantage in the whole text.
Description of drawings
Fig. 1 is that the simplified schematic of the vertical view of semiconductor wafer complex is according to embodiments of the present invention represented, this complex comprises the circular metal substrate, and linking on it has 4 square semiconductor pieces.
Fig. 2 is the simplified cross-sectional view corresponding to Fig. 1.
Fig. 3 is the simplified flow chart that is prepared the method for semiconductor chip according to an embodiment of the present invention by the semiconductor wafer complex of Fig. 1 and 2.
Fig. 4-7 shows the method for simplifying that forms through-hole structure according to an embodiment of the present invention.
Fig. 8 is the reduced graph of the frequency characteristic of through-hole structure according to embodiments of the present invention; With
Fig. 9-15 shows the method for simplifying of the formation semiconductor device of the replaceable embodiment according to the present invention.
Embodiment
According to the present invention, provide the technology of producing substrate.More specifically, the invention provides a kind of method and the device of Semiconductor substrate that be used to improve with the formation advanced semiconductor devices.As just example, the present invention has been applied to be used for the metal substrate of production advanced semiconductor devices, and it comprises a plurality of panels and/or the piece (tile) that is attached on this substrate.But, recognize that the present invention has the wideer scope of application far away.
The semiconductor wafer complex is described here.This complex is very suitable for preparing compound semiconductor device.And this complex especially is applied in the large-scale production of this device.At first describe the semiconductor wafer complex for preparing single semiconductor device by it, then describe the operation of using described semiconductor wafer complex to produce semiconductor device in a large number.
Fig. 1 and 2 schematically shows vertical view and the end view of simplifying the semiconductor wafer complex according to embodiments of the present invention respectively.This figure only is an example, should not limit the scope of claim here inadequately.Those skilled in the art can recognize many variations, modification and replacement.This semiconductor wafer complex has replaced the existing semiconductor wafer of preparation semiconductor chip effectively.
The semiconductor wafer complex of representing among described Fig. 1 and 2 comprises metal substrate 210, and linking on it has many semiconductor pieces 220.
It is rounded that Fig. 1 expresses the shape of metal substrate 210, and show 4 rectangular semiconductor pieces 220 that adjoin.Also represent rectangular semiconductor piece 220 by 4 rectangles shown in the dotted line, they can be attached near the periphery of metal substrate 210 on the metal substrate 210, more effectively to utilize the surface of metal substrate 210.This substrate preferably makes by having the material that good electrical conductivity, thermal conductivity and its thermal coefficient of expansion and semiconductor piece be complementary.For example, CuMo, AlSi and Mo are suitable materials.Preferably, according to a particular, this substrate height conduction, resistivity is 1-10 micro-ohm cm (1-10 * 10
-6Ω cm).Perhaps, according to other embodiment, this material can be a semiconductor.Piece 220 is provided with to such an extent that be close together, and may not have directly to adjoin.Fine pitch between the wafer piece 220 has reduced the requirement to piece size accuracy, and allows small expansion gap, if necessary.Tell-tale gap size for example can be less than 5 μ m.Preferably, each piece should have small gap separating each other, thereby considers any tolerance limit difference.Perhaps, according to other embodiment, these pieces adjoin each other, to prevent or to reduce the zone that impurity (for example photoresist) enters interblock.
Fig. 2 is and the corresponding end view of Fig. 1.The peripheral semiconductor piece 220 that dotted line is painted among Fig. 1 does not illustrate in Fig. 2.Metal substrate 210 comprises metal-based layer 240, is formed with metal binder couse 250 on it.Metal-based layer 240 can be formed by suitable metal or alloy, and the thermal coefficient of expansion of these metal or alloy and compound semiconductor materials (CTE) is complementary.For GaAs (GaAs) compound semiconductor piece 220, the suitable selection of metal substrate 210 is copper molybdenum (CuMo).Metal binder couse 250 is wished by tin (Sn) or indium (In) and gold (Au), or other fusing point is lower, the suitable metal through adding the thermosetting acolite forms.In preferred embodiments, acolite provides by compression fully, and does not have relative transverse movement between piece and substrate.
Around metal-based layer 240 and metal binder couse 250 is the thin metal coating 290 that is formed by noble metal.Preferred gold (Au) or the platinum (Pt) of using.Coating 290 is metal substrate 210 sealing, is damaged in the process that is prepared semiconductor device subsequently by this semiconductor wafer complex preventing.For example can pass through evaporation/deposition technique, or be coated with application layer 290 by electroplating.
Above the composition of semiconductor wafer complex is described with reference to Fig. 1 and 2 in, below various other correlated characteristics and the advantage of this semiconductor wafer complex are described with reference to the method for producing the semiconductor wafer complex.Here the step 310-330 with reference to Fig. 3 describes this production method.The step 340-370 of Fig. 3 remainder describes the step that is prepared semiconductor device subsequently by the semiconductor wafer complex.
In specific embodiment, each piece all has specific size and dimension.Metal substrate also has desired shape and size.That is to say that the diameter of metal substrate " dm " ability of wafer processing apparatus is on the estimation selected.This gravel size decision is selected from one group of industry diameter, for example 2 inches, 3 inches, 4 inches, 5 inches, 6 inches, 8 inches, 12 inches.The shape of substrate will satisfy serving as provides one " plane " on a part of circumference of alignment fiducials, this is similar to conventional wafer.
And, can carry out patterning to substrate, to provide the hole of the signal coupling that helps packaging operation or conveniently leave chip.For example, this hole can be used for forming the slit that the high-frequency signal of chip is left in emission.
These pieces are to be cut into for the circular compound semiconductor wafer of " ds " by radius, and wherein the integral multiple of wafer diameter " ds " equals the diameter " dm " of metal substrate, i.e. dm=n * ds, and n be the possible integer of minimum.This relation has guaranteed to use the piece of minimum number, and in the waste minimum of the expensive compounds semi-conducting material that is cut into piece in the suitable shape to be caused.For example, 4 foursquare diagonal-size are that 3 inches piece can be cut into by 3 inches semiconductor wafer, and the block array with 2 * 2 covers 6 inches metal substrate.If have only the semiconductor wafer of 2 inch diameters, can make 9 foursquare diagonal-size and be 2 inches piece, the block array with 3 * 3 covers 6 inches metal substrate.Certainly, can carry out various modifications, replacement and variation.
Though utilize specific embodiment that above-mentioned semiconductor wafer is described, can carry out many variations, substitutions and modifications.For example, metal substrate can be made by alloy or other material and other multilayer material etc., and these materials all have desired electricity and thermal characteristic.According to application, metal substrate also can be a multilayer.In addition, these one or more pieces can be made on substrate by different materials.Can find these and other variation in the application in the whole text, and hereinafter this carried out describing more specifically.
In specific embodiment, the method general introduction ground that is used for preparing compound semiconductor device comprises the step that following table 1 is listed.Fig. 3 has provided these steps in a flowchart, below further describes.
Table 1
Step 310 thins a plurality of semiconductor wafers 220
Step 320 is cut into semiconductor piece with wafer 220
Step 330 is attached to semiconductor piece 220 on the metal substrate 210
Step 340 uses the front treatment technology of standard to come fabricate devices
Step 350 is got from the front to the metal substrate 210 through hole
Step 360 plated-through hole is connected to form ground connection with metal substrate 210
Step 370 is cut into independently single chip with metal substrate 210
As implied above, above step only illustrates.Depend on embodiment, some step can further decompose or even with the combination of other step.Depend on embodiment, can add other step.Other step can replace above some step.Thus, can carry out many variations, modification and replacement.Can find the further details of each step in the whole text in the application, and more specifically following.
Thin semiconductor piece---step 310
Thin each wafer piece 220 according to existing treatment technology.If this moment wafer breakage, then relevant cost is lower, because does not also handle in the front of semiconductor piece 220.According to particular, use brighten/polishing and/or polishing operation to thin these pieces.According to some embodiment, the thickness of these pieces can be thinned down to about 50-100 micron.According to particular, use brighten/polishing and/or polishing operation to thin these pieces.
Form semiconductor piece---step 320
Semiconductor wafer is cut into semiconductor piece 220.Preferably, use line and disruption process that each piece is provided.More preferably, can rule by diamond scriber, laser cutting etc.Preferably, these are " standard " wafers, and growth has epitaxial loayer on their front, and has been ready for fabricate devices.Semiconductor piece 220 is shaped to and makes these semiconductor pieces 220 to cover flat surfaces with the gap of minimum.According to particular, form each piece along crystal face, accurate shape is provided like this.This accurate shape allows to aim between each piece, to reduce the possibility that occurs the gap between each piece.This also makes with identical crystal orientation all pieces to be arranged in subsequently becomes possibility on the metal substrate.
These pieces are attached on the substrate---step 330
Select metal substrate to make its thermal coefficient of expansion (CTE) and selected semi-conductive CTE in required temperature ranges, be complementary.Also according to its intensity, thermal conductivity and conductance and become the original backing material of selecting.Preferably, substrate also has high thermal conductivity, removes with the heat of self-forming in future integrated device thereon.According to some embodiment, the thermal conductivity of metal substrate can be 165W/mK or bigger.
For example, the alloy of about 80% molybdenum and 20% bronze medal is suitable mutually with the CTE of GaAs, and has suitable conductance and thermal conductivity.The advantage of using metal substrate 210 is by changing the composition of metal alloy, can regulating CTE.If use for example crystalline state substrate of silicon, can not carry out this adjusting.
With a mirror polish of metal substrate 210, its periphery is shaped to and is fit to large diameter wafer processing apparatus.Preferably, polishing has reduced to form the possibility of air gap between substrate surface and piece.In certain embodiments, the surface roughness of metal substrate is not more than predetermined value, and the uniformity on the entire substrate is worth with the convenient technology that links less than certain.According to some embodiment, this surface also can comprise a series of patterns and/or texture, and they prevent to form air bubble etc., and has strengthened binding technology.This often means that metal substrate 210 rounded (as illustrated in fig. 1 and 2).For compatible, can provide than facet in a side with existing wafer processing apparatus.
If in semiconductor technology chemistry subsequently, may have influence on substrate 210, then on metal substrate 210, deposit inert coatings 290.For this purpose, generally use the noble metal thin layer (thickness is less than 1 μ m usually) of gold for example or platinum.Preferably, coating can not reacted in semiconductor processes step subsequently.Also can use other material (for example silicon nitride), as long as this material has enough tolerances to used process chemistry and temperature in the processing of wafers step of estimating.
Deposition binder couse 250 on the polished surface of metal substrate 210.This metal binder couse 250 is preferably got by the two or more metallic that add the thermosetting acolite.Outermost layer is noble metal (for example gold) preferably, prevented bottom before linking and during oxidation takes place.Bottom can be formed by tin or indium.Selected these metals will make and form acolite down at lower temperature (for example 200 ℃), and after having formed, can not melt under the high temperature that meets with during crystal is handled.This binder couse also can serve as the inert coatings of metal substrate.
On the back side of the semiconductor wafer piece 220 that each thins, also deposit complementary binder couse 270.This complementation binder couse 270 is metal preferably also, and the maximum adhesion that provides in temperature ranges subsequently semiconductor piece 220 will be provided its composition.A preferred layer structure is titanium/gold or titanium/platinum/gold, but do not depart from the scope of the present invention with mental condition under, the combination of many other metals is fine.
Many other binder couses compositions are fine, and can select to require (for example maximum temperature) to be complementary with the particular procedure of different semi-conducting materials.For example, in certain embodiments, forming indium on the semiconductor wafer rather than on metal substrate or the tin binder couse may be favourable.This advantage may come from has simplified the production technology that is used for the production metal substrate, thereby has reduced total cost.In this case, the golden passivation layer of metal substrate also plays binder couse.
The advantage that the use of metal binder couse provided is to allow to be attached under the lower temperature (for example 200 ℃) to take place.This epitaxial layer structure of having guaranteed wafer piece 220 can deterioration.Also can use for example nonmetal complementary binder couse 290 of silicon, polysilicon, silicon dioxide or silicon nitride.
Big gap between the semiconductor piece 220 wishes to avoid, because this gap may influence the rotating and depositing of photoresist unfriendly.Semiconductor piece 220 is square or rectangular preferably.This shape allows the rectangle chip array to be included in effectively in the semiconductor piece 220, also allows by ruling along crystal face (normally rectangle) and breaking cutting semiconductor piece 220.
But, also can use other block-shaped.For example, the hexagon piece can more effectively cover the surface of circular substrate 210 than rectangular blocks.Embodiment preferred is used the square block or the rectangular blocks of one group of non-homogeneous as illustrated in fig. 1.The selected pattern of semiconductor piece 220 depends on the size of available semiconductor wafer and the size of metal substrate 210.
In specific embodiment, by being provided with, each piece overlays on the metal substrate, link.Also provide for example described here and other binder couse.Between each piece and substrate, use mechanical force to press binder couse, link.Also heat.In specific embodiments, application of heat and pressure (perpendicular to piece surface and substrate) keep each piece not have transverse movement with respect to substrate simultaneously, to form for example eutectic binder couse between each piece and metal substrate.Certainly, can carry out many variations, substitutions and modifications.
Handle in the front of complex---step 340
Handle the front of composite crystal now according to the standard semiconductor technology of preparing.On each piece 220, the benchmark alignment mark is set, to consider the slight misalignment between the semiconductor piece 220.Each chip preferably is arranged on the semiconductor piece 220, so that these chips all are included in the piece 220, can not exceed the border of semiconductor piece.
Open hole---step 350
Be different from from the existing semiconductor technology of chip back surface to front formation through hole, can be from just making through holes towards metal substrate 210.Thereby simplified the aligning of through hole, because this aligning carries out with respect to other visible front parts.
Plated-through hole---step 360
The existence of metal substrate 210 allows to remove the large area region of semiconductor piece 220 in via process, and can not damage the structural strength of composite crystal.This means and on semiconductor piece 220, to form through hole " groove ".These grooves can provide following feature:
(i) compare with common round tube hole, lower inductance ground connection connects;
(ii) form electromagnetic shielding between proximate circuitry, this rises along with current densities and seems important;
The (iii) profile that separates of chip; And
The (iv) contour semiconductor wafer that is provided with is to realize local heat dissipation characteristics.
Be cut into each device---step 370
The ability that depends on processing machine by from the front or back side cutting metal substrate 210, is isolated each chip.
Because each chip is being supported by the part of metal substrate 210, so reduced chip rupture during handling.And, can prepare bigger chip.As a result, can be on single chip with greater functionality/system integration.By simplifying engineering and production requirement, this chip has been saved great amount of cost.
The existence of metal substrate 210 also plays radiator on each chip, and this is favourable in high power applications.
Other variation
A kind of variation of above-mentioned preparation section is to be attached on the metal substrate 210 without the wafer piece 220 that thins.Can when being attached to semiconductor piece 220 on the metal substrate 210, thin subsequently.The advantage that this variation provides is the semiconductor surface of " planarization " wafer complex in thinning technical process.As a result, growing epitaxial device layer on the wafer complex.
The operation of this modification can be brought economic benefit in some cases.And, because semiconductor piece 220 is thicker in this stage, so the processing requirements of wafer piece 220 is looser before binding.
Here describe metal binder couse 250, but can use other technology that semiconductor piece 220 is fixed on the metal substrate 210.For example, can use the temperature that is fit in the semiconductor fabrication and the adhesive of chemical treatment conditions that semiconductor piece 220 is adhered on the metal substrate 210.
Technology described here is fit to produce semiconductor device, comprises the device that those use composite semiconductor major diameter composition metal substrate.Described technology has been improved radio-frequency performance potentially by large-scale production, has improved productivity ratio, has reduced cost, and other benefit described here is provided.
The method for preparing the contact zone according to an embodiment of the present invention in Semiconductor substrate can be summarized as follows.
1. the metal substrate with first diameter and connected surfaces is provided;
2. will overlay in a plurality of bindings on this connected surfaces, these pieces wherein each all is coupled to a part of connected surfaces, these pieces wherein each all has the shape and size that can form array configuration;
3. the temperature of these a plurality of and the metal substrate of raising;
4. between this wherein each and part connected surfaces of a plurality of, form eutectic and link, these pieces wherein each with respect to metal substrate static substantially in, carry out temperature and raise;
This a plurality of wherein form a plurality of active devices on each;
6. pass each piece and form a plurality of openings, each opening all passes one of them part of these pieces, passes the eutectic linking portion until the metal substrate part, forms through-hole structure;
7. formation interconnection layer is with the part by this piece, be connected to the metal substrate part by the eutectic linking portion with one of them part of active device.
The method of replaceable embodiment can be summarized as follows according to the present invention.
1. the metal substrate with predetermined thickness is provided;
2. overlay on the metal substrate in the compound semiconductor materials binding with first thickness;
3. the thickness with the compound semiconductor materials of first thickness reduces to second thickness;
4. the compound semiconductor materials that passes second thickness partly forms one or more through-hole structures to beneath metal substrate part, and through-hole structure is electrically connected to metal substrate (using positive the processing) thus;
5. as wishing, carry out other step.
Above sequence of steps provides the mode that forms through-hole structure in MULTILAYER SUBSTRATE according to embodiments of the present invention.As directed, these steps comprise forming passes the through-hole structure of compound semiconductor materials on beneath metal substrate part.This through-hole structure preferably partly contacts with metal substrate.Preferably, the present invention is by forming through hole from the front of wafer, easier thus aligning, thus can overcome the restriction of some conventional method.By using metal substrate, for wafer provides mechanical support, can increase the quantity of through-hole structure or the density of this structure, to overcome any routine restriction about number of openings and shape.According to embodiment, can carry out many variations, substitutions and modifications.
According to particular, can provide the following method for preparing through-hole structure.
1. utilize one or more technologies described here, the preparation compound semiconductor structure.
2. deposition photoresist, exposure, development is with the front of cover wafers, except needing the place of through hole.
3. use the reactive ion etching technology to remove semi-conducting material downwards, form opening up to metal substrate.(, can change the profile (gradient) of the wall of these openings by regulating etch process parameters.Regulate gradient, make the diameter of through hole reduce in the metal liner bottom side.)
4. utilize evaporation, sputter or chemical vapour deposition technique, plated metal on the whole surface of wafer (metal coated is in the side of through hole, and contacting between some front parts and the ground plane that is provided by metal substrate is provided).
5. utilize second photoresist layer and suitable etching or ion milling technology, remove excessive metal.
As directed, according to application, through-hole structure can form almost Any shape and size.This method provides the opening (for example hole) of the lengthening that a kind of manufacturing has low-down inductance (promptly less than 2pH) or the mode of groove, this high frequency at for example amplifier or oscillator (＞10GHz) provide low impedance earth to connect in the circuit.Same feature can be used for forming the ground connection spaced portions on the chip, this in the proximate circuitry of isolating for example transmitting set and receiver in order to avoid useful in interfering with each other.Can find the further details of this method in the whole text in the application, and hereinafter more specifically.
The method for simplifying of Fig. 4-7 explanation formation according to an embodiment of the present invention through-hole structure.This method only is an example, should not limit the scope of claim here inadequately.Person of skill in the art will appreciate that many variations, substitutions and modifications.As directed, this method starts from providing metal substrate 400, and this substrate is similar to above-mentioned, but also can be other.Compound semiconductor material layer 401 has been attached on the metal substrate.Depend on embodiment, compound semiconductor materials 401 can be described here any and other, comprise sandwich construction, depend on embodiment.A plurality of integrated device structures have formed and have overlayed on the compound semiconductor materials.These device architectures comprise transistor, diode, resistor, capacitor, inductor and the circuit that is made by these parts, for example amplifier, blender, interchanger etc.Certainly, concrete integrated device structure depends on application.
As further shown, on the upper surface of integrated circuit device structure, cover formation light-sensitive material 501.This light-sensitive material can comprise photoresist, Shipley MEGAPOSITTM SPRTM 600 series for example, but also can be other.The photoresist material is exposed and develops, and forms one or more patterns 503.These patterns wherein each makes beneath regional exposure, will form through-hole structure.The compound semiconductor materials that preferably exposes in the exposure area.As directed, light-sensitive material is provided at the front of substrate in specific embodiments, rather than the back side.
With reference to Fig. 6, this method has been removed the exposed portion of compound semiconductor materials, forms the opening 601 that extends to metal substrate.Depend on embodiment, opening almost can be Any shape and size.The for example rectangle that shape preferably extends or other analogous shape.Depend on embodiment, be of a size of 50 microns and following or 500 microns and more than.In addition, the present invention allows to have more through-hole structure on the unit are, promptly higher through-hole structure density.As just example, use the gallium arsenide compound semi-conducting material of 100 micron thickness, in about 1 square millimeter zone, can form 25 through-hole structures.This method then by the stripping technology of standard, removes photoresist.
This method then forms metal contact structure 701 in the exposed portion of compound semiconductor materials.This metal structure is preferably formed by the adhesion layer of for example titanium etc. with by the contact layer that gold or other suitable material make, and wherein the diffusion impervious layer that made by platinum of adhesion layer covers.Other metal can replace mentioned metal, for example replaces gold with copper.The technology of for example plating, sputter and/or vapour deposition is used for forming metal level.This metal level can also comprise a plurality of metal levels.Depend on embodiment, can be with metal layer patternization to form metal interconnect structure.
Fig. 8 is the reduced graph of through-hole structure frequency characteristic according to embodiments of the present invention.This curve chart only is an example, should not limit the scope of claim here inadequately.Person of skill in the art will appreciate that many variations, substitutions and modifications.As directed, transverse axis is represented frequency, and the longitudinal axis is represented decay.Article one, curve representation comprises the low pass filter that 16pH through-hole structure ground connection connects.Second curve representation 1.6pH through-hole structure ground connection connects, and it has improved stopband attenuation.These are simple low pass filter, utilize single through hole to connect filter and ground connection benchmark.Though the inductance of through hole has improved at a specific frequency the filtering performance under (that is, the frequency when dark V word mouth occurring), the filtering performance (decay) when it has reduced greater than this dark V word mouth frequency.The benefit that reduces the through hole inductance has been to increase the decay of filter under high frequency.
Producing the method that links substrate according to an embodiment of the present invention can be summarized as follows.
1. metal substrate is provided;
2. overlay on the metal substrate in the compound semiconductor materials binding with first thickness;
3. the thickness with the compound semiconductor materials of first thickness reduces to second thickness;
4. the compound semiconductor materials around second thickness partly forms the ditch district;
5. in this ditch district, form electric conducting material, to isolate the compound semiconductor part and the beneath metal substrate part of this second thickness that in the ditch district, uses electric conducting material; And
6. if wish, carry out other step.
As directed, this method provides a kind of mode that links substrate of producing.As just example, this method forms the metal isolation structure, and it seals the part of compounds semi-conducting material.This isolated metal structure either has the performance of improvement, for example with better insulation and adiabatic of peripheral circuits.Can find the further details of this method and the device of gained in the application in the whole text, and more specifically following.
The method for simplifying of Fig. 9-15 expression interchangeable embodiment formation semiconductor device according to the present invention.This method only is an example, should not limit the scope of claim here inadequately.Person of skill in the art will appreciate that many variations, substitutions and modifications.As directed, this method starts from providing metal substrate 900, and it is similar to above-mentioned, but also can be other.Compound semiconductor material layer 901 has been attached on the metal substrate.Depend on embodiment, compound semiconductor materials 901 can be described here any and other, comprise sandwich construction, depend on embodiment.A plurality of integrated device structures 902 have formed and have overlayed on the compound semiconductor materials.These device architectures comprise transistor, diode, resistor, capacitor, inductor and the circuit that is made by these parts, for example amplifier, blender, interchanger etc.Certainly, concrete integrated device structure depends on application.
As further shown, isolated material 1001 forms and overlays on the upper surface of integrated circuit device structure, as shown in figure 10.This isolated material can comprise dielectric medium, polyimide material for example, but also can be other.This polyimide material patterning is formed one or more patterns 1001.Polyimides forms and overlays on the integrated circuit (IC)-components, and is not attached on other zone 1002 of compound semiconductor materials.With reference to Figure 11, this method forms metal level 1103, and this layer has been patterned with sealing polyimide layer and compound semiconductor materials part.The other parts of metal optionally remove, shown in label 1105.
This method is with zone 1201 patternings around the polyimide metal interlayer, as shown in figure 12.This zone is the ditch district around polyimide metal interlayer periphery, overlays on the integrated circuit (IC)-components on it.Depend on embodiment, this method can be used photoetching and etching technique.This ditch district is wide to be about 50 microns, and being about is 500 microns.The degree of depth is 50 microns approximately, but this depends on embodiment.Then, this method forms metal level 1301, and its contact overlays on metal level and the part metals substrate 901 on the polyimides.Alternatively, the polyimide layer under this metal level is removed, reduced to form the electric capacity of active circuit thereon with integrated circuit (IC)-components or other to form " air bridges ".Figure 15 shows this end view that comprises the device of air bridges.As directed, this device is included in the air bridges 1401 between metal level 1103 and the device architecture 902.This device is arranged on the compound semiconductor layer 901, and layer 901 is attached on the metal substrate 900.Form through-hole structure, metal substrate 900 is connected with metal level 1103 through metal level 1301.As directed, this method forms the box structure around the device periphery zone, utilizes this can structure, and this zone is isolated.Depend on embodiment, can carry out many variations, modification and replacement.
As directed, metal level also can serve as conducting-heat elements, below will introduce in more detail.Here, the invention provides a kind of integrated circuit device structure.This integrated circuit device structure comprises the metal substrate with predetermined thickness and predetermined thermal conductivity.Certain thickness compound semiconductor materials is attached on the surface that overlays on the metal substrate.In the part of the compound semiconductor materials of this thickness, the ditch district is set, and extends to the metal substrate part.Heat Conduction Material (for example metal level) forms in this ditch district, and with this portion of hot coupling of metal substrate.This part coupling of the compound semiconductor of Heat Conduction Material and this thickness (for example direct and its physical connection) is to redistribute heat energy between this part, Heat Conduction Material and the metal substrate of compound semiconductor.Preferably, prevented from any hot-zone to occur at the integrated circuit (IC)-components run duration of gained.Metal substrate has been served as hot pond.
According to the disclosure content, under the situation that does not depart from scope and spirit of the present invention, obviously those skilled in the relevant art can carry out various variations, modification and replacement to structure described here and technology.
Claims (32)
1. a production is used for the method for the compound substrate of semiconductor device, and this method comprises:
Metal substrate is provided, and described metal substrate has first diameter and connected surfaces;
To be layed onto in a plurality of bindings on the described connected surfaces, described wherein each all with the coupling of the part of described connected surfaces, described wherein each all has the shape and size that can form array configuration;
The temperature of described a plurality of and the metal substrate of raising;
Between the part of a plurality of wherein each and described connected surfaces, form eutectic and link, wherein described wherein each with respect to described metal substrate static substantially in, elevated temperature;
Wherein form a plurality of active devices on each described a plurality of;
Form a plurality of openings by each piece, described opening wherein each passes one of them described part, pass described eutectic linking portion up to described metal substrate part, to form through-hole structure;
Form interconnection layer, with one of them described active device partly by described part, partly be connected with described metal substrate by described eutectic binding;
So described interconnection layer partly by one of them described part, partly is connected one of them described active device with described metal substrate by described eutectic binding.
2. according to the process of claim 1 wherein that the described a plurality of openings that wherein form in each at described also comprise and use photoetching material to be coated with described a plurality of active device, and this coating of patterning is to form the zone corresponding to described opening.
3. according to the method for claim 2, wherein said patterning comprises etch process.
According to the process of claim 1 wherein described wherein each all comprises the entity that is selected from GaAs, indium phosphide, gallium nitride and carborundum.
5. according to the process of claim 1 wherein that each described opening is a through-hole structure.
6. according to the process of claim 1 wherein that using the alloy be selected from the low melting temperature metal that comprises indium, tin and resistance to oxidation metal to carry out described eutectic links.
7. according to the process of claim 1 wherein that described array configuration is N * M array of described, described wherein each all is coupled with another piece.
8. according to the process of claim 1 wherein that each described opening is characterised in that aspect ratio was greater than 2: 1.
9. according to the process of claim 1 wherein that described interconnection layer comprises gold/platinum/titanium.
10. according to the process of claim 1 wherein that described interconnection layer is included in the barrier metal layer under the conductive layer.
11. according to the process of claim 1 wherein that described metal substrate provides ground plane.
12. produce the method that links substrate for one kind, this method comprises:
Metal substrate is provided, and this metal substrate has predetermined thickness;
Overlay on the described metal substrate in the compound semiconductor materials binding with first thickness;
The thickness of the compound semiconductor materials of described first thickness is reduced to second thickness; And
The compound semiconductor materials that passes described second thickness partly forms one or more through-hole structures to beneath metal substrate part, and described thus through-hole structure is electrically connected to described metal substrate.
13. according to the method for claim 12, second thickness of wherein said compound semiconductor materials is less than 100 microns.
14. according to the method for claim 13, it is unsettled that the compound semiconductor materials of wherein said second thickness does not have described metal substrate.
15. according to the method for claim 13, the aspect ratio of wherein said through-hole structure was greater than 2: 1.
16. according to the method for claim 12, wherein said metal substrate has first thermal coefficient of expansion, described compound semiconductor has second thermal coefficient of expansion, and described first thermal coefficient of expansion is in the predetermined value of described second thermal coefficient of expansion.
17. according to the method for claim 12, wherein said predetermined value is chosen to be any damage that will prevent in the temperature range of about room temperature to 550 degree centigrade described compound semiconductor.
18., also comprise the compound semiconductor of handling described second thickness by one or more production technologies that is used for integrated circuit according to the method for claim 12.
19. according to the method for claim 18, wherein said one or more production technologies comprise alloying technology at least, to contact forming between described compound semiconductor and the metal level.
20. according to the method for claim 19, wherein said alloying technology is an annealing process.
21. produce the method that links substrate for one kind, this method comprises:
Metal substrate is provided, and described metal substrate has predetermined thickness;
Overlay on the described metal substrate in the compound semiconductor materials binding with first thickness;
The thickness of the compound semiconductor materials of described first thickness is reduced to second thickness; And
Form one or more compound semiconductor parts of passing described second thickness, pass the groove structure of described metal substrate back side opposition side;
In described one or more groove structures, form one or more metal structures, to form one or more corresponding through-hole structures to beneath metal substrate part in the compound semiconductor materials part of described second thickness, described thus through-hole structure is electrically connected to described metal substrate.
22. produce the method that links substrate for one kind, this method comprises:
Metal substrate is provided, and described metal substrate has predetermined thickness;
Overlay on the described metal substrate in the compound semiconductor materials binding with first thickness;
The thickness of the compound semiconductor materials of described first thickness is reduced to second thickness; And
Compound semiconductor materials part around described second thickness forms the ditch district; And
In described ditch district, form electric conducting material, to isolate described compound semiconductor part and the beneath metal substrate part of in the ditch district, using second thickness of electric conducting material.
23., wherein exposed in the compound semiconductor top partly of described second thickness according to the method for claim 22.
24., also comprise forming the separator that overlays on the described exposure top according to the method for claim 22.
25., also comprise overlaying in the formation on the described separator and being connected with electric conducting material in the described ditch district with the metal level of the compound semiconductor part that seals described second thickness according to the method for claim 24.
26. a substrat structure that is used for high-frequency apparatus, described structure comprises:
Metal substrate, described metal substrate are the ground planes of the high frequency multiplying arrangement that can move under greater than the 10GHz frequency;
Be attached to the compound semiconductor materials on the described metal substrate;
The one or more through-hole structures that are used for the ground connection connection that in described compound semiconductor materials part, form, described one or more through-hole structures are electrically connected to described metal substrate;
The reactance that described thus one or more through-hole structures are configured to provide desired is to provide general ground connection benchmark, and described general ground connection benchmark is in predetermined value.
27. according to the structure of claim 26, wherein said predetermined value is less than 1/4 of the wavelength of circuit running frequency.
28. according to the structure of claim 26, about 0.01 ohm to about 1 ohm of wherein desired reactance.
29. an integrated circuit device structure, described integrated circuit device structure comprises:
Metal substrate, described metal substrate have predetermined thickness and predetermined thermal conductivity;
Be attached to the certain thickness compound semiconductor materials of described metal substrate upper surface;
Be arranged on the interior ditch district of compound semiconductor materials part of described thickness, it extends to described metal substrate part; With
The Heat Conduction Material that is thermally coupled to described metal substrate part that in described ditch district, forms, the compound semiconductor materials of described Heat Conduction Material and described thickness partly is coupled, to redistribute heat energy between described compound semiconductor part, Heat Conduction Material and metal substrate.
30. according to the structure of claim 29, wherein said ditch district is round the compound semiconductor materials part of described thickness.
31. according to the structure of claim 29, wherein said substrate is hot pond.
32. according to the structure of claim 29, the wherein said heat energy of redistributing provides the compound semiconductor part of neither one or a plurality of hot-zones.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/389,278 US6919261B2 (en) | 2002-03-14 | 2003-03-13 | Method and resulting structure for manufacturing semiconductor substrates |
| US10/389,278 | 2003-03-13 | ||
| US10/634,512 | 2003-08-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1788348A true CN1788348A (en) | 2006-06-14 |
Family
ID=36785141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200480006860 Pending CN1788348A (en) | 2003-03-13 | 2004-03-15 | Via and trench structures for semiconductor substrates bonded to metallic substrates |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1788348A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111048581A (en) * | 2019-12-23 | 2020-04-21 | 电子科技大学 | Diamond field effect transistor with air-bridge-like source field plate structure |
-
2004
- 2004-03-15 CN CN 200480006860 patent/CN1788348A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111048581A (en) * | 2019-12-23 | 2020-04-21 | 电子科技大学 | Diamond field effect transistor with air-bridge-like source field plate structure |
| CN111048581B (en) * | 2019-12-23 | 2022-03-22 | 电子科技大学 | Diamond field effect transistor with air-bridge-like source field plate structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1309285C (en) | High frequency circuit block member, its manufacturing method, high refrequency module device and its manufaturing method | |
| CN1260789C (en) | Circuit board, semiconductor device mfg. method, and electroplating system | |
| CN1151542C (en) | Electronic device and its mfg. method | |
| US20060035438A1 (en) | Method and resulting structure for manufacturing semiconductor substrates | |
| CN1237854C (en) | Method of making microwave, multifunction modules using fluoropolymer substrates | |
| US20050160972A1 (en) | Method and resulting structure for manufacturing semiconductor substrates | |
| CN1277309C (en) | Semiconductor device and manufacturing method thereof | |
| CN1976014A (en) | Semiconductor device and its production method | |
| CN1187806C (en) | Method for producing electric circuit device | |
| CN1722370A (en) | The manufacture method of semiconductor device | |
| CN1521847A (en) | Electronic parts packaging structure and method of manufacturing the same | |
| CN1957464A (en) | Semiconductor device, wiring board and manufacturing method thereof | |
| CN1819176A (en) | Interconnecting substrate and semiconductor device | |
| CN1976015A (en) | Semiconductor device and method for manufacturing same, and semiconductor wafer | |
| CN1705108A (en) | Circuit device and manufacturing method thereof | |
| CN1499590A (en) | Semiconductor device and its mfg. method | |
| CN1367540A (en) | GaN group III-V family nitride light-emitting diode and its production method | |
| WO2015077623A1 (en) | Led submount with integrated interconnects | |
| CN1758431A (en) | Wafer package with integrated heat dissipating base on chip and heat sink method oa chip | |
| CN1230013A (en) | Mfg. method of semiconductor device and semiconductor device | |
| CN1433072A (en) | Wiring structure and its making process, semiconductor device with the wiring structure and its wiring base board | |
| CN102544310A (en) | Mounting substrate and manufacturing method thereof | |
| CN1228824C (en) | Method for producing semiconductor device and semiconductor device | |
| CN1685507A (en) | Method for producing a component comprising a conductor structure that is suitable for use at high frequencies | |
| CN1830083A (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |