CN1734437B

CN1734437B - Multi-processor controlling equipment, its controlling method and integrated circuit thereof

Info

Publication number: CN1734437B
Application number: CN2005100980458A
Authority: CN
Inventors: 西冈伸一郎
Original assignee: 松下电器产业株式会社
Current assignee: SK Hynix Inc
Priority date: 2004-07-01
Filing date: 2005-07-01
Publication date: 2011-10-05
Anticipated expiration: 2025-07-01
Also published as: CN1734437A; US7398403B2; US20060005056A1

Abstract

Provided is a multiprocessor control apparatus that restrains impairment of processing speed of entire operations, while pursuing power consumption saving for a multiprocessor. The multiprocessor control apparatus has: an execution control unit operable to control a processor to, when processors other than the processor have ended respective operations performed in parallel, start performing an operation that uses a result of the operations; and a power control unit operable to control power supply to the processor, where when the processor has been under power-supply restriction, the power control unit cancels the power-supply restriction before one of the other processors, which is the last of all the other processors to end a corresponding operation, ends the corresponding operation.

Description

Multiprocessor opertaing device, its control method and integrated circuit

Technical field

The present invention relates to a kind of opertaing device that is used for multiprocessor.The present invention relates to a kind of technology that is used for being reduced by opertaing device power consumption particularly.

Background technology

In distributed treatment, multiprocessor sometimes must carry out synchronously so that Data transmission between the processor therein, or keep the consistance between the processing sequence and the value that produces by operation between consistance.At this, synchronization representation has finished the processor of its processing and has waited for up to other their processing of processor end.When all processors (should keep the consistance of operating value between them) when finishing their operation, each processor that is under the waiting status can both be proceeded follow-up operation respectively.

In this class multicomputer system, by stopping to attempt energy-conservation (for example, Japanese laid-open patent application No.H7-146846) to processor power supply that enters waiting status and the mode of when all processors have finished their operation, having restarted to power.

Yet this energy-conservation in the multicomputer system has following point.When restoring electricity, before supply voltage is stable, need a certain amount of time for the processor that is in waiting status.This means that follow-up operation can not begin immediately, thereby reduced the processing speed of whole operation.

In addition, in the process of stopping power supply, each processor must be saved to storer or the like with the environment (context) (for example, operating result or treatment state) that so far is stored in its register, with anti-lost this environment.Therefore, synchronously and after restoring electricity, processor must read the environment of being preserved so that its register reflects this environment, and this also will take some times.In addition, owing to this class environment recovery is carried out, thereby will further reduce the processing speed of whole operation after supply voltage is stable.

Summary of the invention

The present invention proposes in view of the above problems, and its purpose is pursuing weakening of the processing speed that suppresses whole operation when saving power consumption in aforementioned multiprocessor.

In order to realize described purpose, the invention provides a kind of multiprocessor opertaing device, it comprises: carry out control module, it can operate the operation that is used to control the result who begins to carry out these operations of use when a processor has finished the operation of executed in parallel separately with the processor of box lunch except that this processor; And power control unit, it can operate the power supply that is used to control to processor, wherein when this processor has been subjected to the power supply restriction, the cancellation power supply limits before the corresponding operation of an end of this power control unit in other processor, and one in described other processor is that last will finish the processor of corresponding operating in all other processors.

At this, restriction means supply voltage that reduction will provide, stops power supply and stops any one in the clock supply.

According to described structure, the processor that last that the multiprocessor opertaing device relevant with the present invention can be in all processors will finish its operation finishes to restore electricity or environment recovery before its operation.By doing like this, stablizing of supply voltage and stablizing the needed time of environment recovery will have been hidden obviously.Owing to can realize power stability faster like this, thereby might be just in time transfer in the subsequent operation from the moment that last processor finishes its operation, this will eliminate time waste.

At this, it also may be such structure, promptly the multiprocessor opertaing device further comprises this processor and other processor in this structure, wherein each other processor comprises the synchronous request signal output unit, it can operate the synchronous request signal that is used to export the end of indicating corresponding operating, carry out control module and comprise the cancelling signal output unit, output was used to cancel the cancelling signal of power supply restriction when it can be operated the synchronous request signal that is used for when many outputs and has been less than the predetermined number of number of other processor, and power control unit cancel powering when receive cancelling signal and limited.

According to described structure, signal is from each processor output, and this signal instruction processorunit has arrived lock in time.When the number of the signal of having exported has reached predetermined number, the cancellation Power Limitation.Therefore, processor can be just in time begins to carry out subsequent operation from the moment that last processor finishes its operation, and this can eliminate the time loss of whole operation.

At this, it also may be such structure, promptly in this structure the cancelling signal output unit a) comprise be used for synchronous counter that the number of the synchronous request signal that begun at other processor to be exported after the operation is separately counted and b) output cancelling signal when the number counted when described synchronous counter has become number than other processor and lacks one number.

According to described structure, when the only surplus next one does not finish the point of the processor of its operation as yet in all processors of arrival, cancel the restriction of powering.This structure has prevented to cause owing to the restriction of cancellation power supply too early the reduction of energy-saving effect.For example, do not suppose when finishing their operation as yet for four in a plurality of processors to restore electricity, and suppose that its operation of execution in the middle of four processors is extremely slow.In this case, will cancel the power supply restriction before processor has any will carrying out of task, this is a waste of electric energy.This structure has prevented this waste.

At this, it also may be such structure, promptly in this structure, carry out control module and comprise the processor information output unit, wherein when last or penult in all other processors during with any other processor output synchronous request signal the processor of end operation, the processor information output unit is exported the processor information about any other processor of exporting synchronous request signal, and in a single day power control unit receives processor information, just limit, and when cancellation is controlled the power supply of described processor, cancel power supply restriction any other processor to power supply by indicated any other processor of processor information.

It also may be such structure, promptly each other processor all further comprises the synchronous request signal output unit in this structure, it can be operated and be used to export the synchronous request signal that the indication corresponding operating finishes, carry out control module and comprise the processor information output unit, wherein when in all other processors last during with any other processor output synchronous request signal the processor of end operation, the processor information output unit is exported the processor information about any other processor of exporting synchronous request signal, and in a single day power control unit receives processor information, just limit, and when cancellation is controlled the power supply of described processor, cancel power supply restriction any other processor to power supply by indicated any other processor of processor information.

According to described structure, the multiprocessor opertaing device can inerrably limit the power supply to the processor of the operation that finishes them.This brings further energy-conservation for whole multiprocessor opertaing device.

In addition, also may be such structure, promptly power control unit a) comprising in this structure: the low-power power supply unit, it can be operated and be used to described processor and other processor that the power lower than normal power is provided; With the normal power supply unit, it can be operated and be used for normal power supply and b) limit power supply to processor and c by means of the low-power power supply unit) cancel the power supply restriction by means of the normal power supply unit.

According to described structure, will power by low-power and produce energy-saving effect.

At this, it also may be such structure, promptly power control unit stops described processor power supply in this structure, and each other processor all comprises: preserve the unit, it can be operated and be used for after respective processor is exported synchronous request signal and before respective processor is stopped power supply, will be saved to storer about the information of the register that comprised in the respective processor; And recovery unit, it can be operated and be used for reading the information of being preserved to recover from storer.

According to described structure, will produce energy-saving effect by stopping power supply up hill and dale.In addition, according to described structure, because the environment of respective processor is saved (otherwise will lose) and is restored when restoring electricity when outage, so the consistance in the whole operation will be held.

At this, it also may be such structure, promptly the multiprocessor opertaing device further comprises this processor and other processor in this structure, wherein each other processor all comprises accurate synchronous request signal output unit, it can be operated and be used to export accurate synchronous request signal, this accurate synchronous request signal indication this respective processor before corresponding operating finishes has arrived the point of the instruction of residue predetermined number, carry out control module and comprise the cancelling signal output unit, it can be operated and be used for exporting the cancelling signal that is used to cancel the power supply restriction when all other processors are exported accurate synchronous request signal respectively, and power control unit is cancelled the power supply restriction when receiving cancelling signal.

At this, the predetermined number of instruction is corresponding to following summation: the needed time of the power stability of processor; With the needed time of the environment recovery of processor, if any.

According to such configuration, each other processor is exported accurate synchronous request signal in its EO before all can operating and being used for slightly, and the sequential of service restoration can limit according to this accurate synchronous request signal.Therefore, processor can be carried out its operation under the situation that is connecting power supply during the minimum required time.

At this, also may be such structure, promptly each other processor a) comprising in this structure: the address information output unit, it can operate the address information that is used to export about the address of the current instruction of being carried out by respective processor; And address storaging unit, it can operate the address that is used for storing predetermined justice, and b) when exporting accurate synchronous request signal when address in being stored in address storaging unit is consistent by the address information of address information output unit output.

According to described structure, when the address of the instruction that can just carry out is consistent with predefined address, export accurate synchronous request signal in present program in processor.

At this, also may be such structure, promptly in this structure, when being explained, the special instruction that is used to export accurate synchronous request signal exports accurate synchronous request signal, and this special instruction is described in the program of being carried out by each other processor.

According to described structure, the instruction that will be used for exporting accurate synchronous request signal in advance is incorporated into program.Therefore, accurate synchronous request signal is to export under the situation that is not used in conforming any circuit of checking the address.

At this, it also may be such structure, promptly the multiprocessor opertaing device further comprises this processor and other processor in this structure, wherein this processor utilization is carried out second operation by the result of each operation of other processor executed in parallel and first result who operates who carries out in this processor, this processor comprises the first synchronous request signal output unit, it can operate the synchronous request signal that is used for output indication first EO when first EO, each other processor all comprises the second synchronous request signal output unit, can operate a corresponding output when finishing that is used for when operating separately and indicate the synchronous request signal of EO separately, and when all processors that comprise this processor and other processor had not also all finished separately operation, the power control unit restriction was to the power supply of the processor of exporting synchronous request signal.

According to described structure, this processor is also with the appropriate section of the shared distributed treatment of other processor.In addition, the concluding time of first operation can be set to the start time to the Power Limitation of processor.

In addition, it also may be such structure, promptly power control unit a) comprises the clock supply unit in this structure, it can be operated each that be used in this processor and other processor clock is provided, and b) when all processors that comprise processor and other processor have not also all finished separately operation, limit clock is provided to the processor of exporting synchronous request signal.

According to described structure, can cut off clock supply to processor.If there is not clock supply, processor just can not begin to operate.Therefore, clock supply stop can be energy-conservation.

In addition, the invention provides a kind of multiprocessor control method that is used in the multiprocessor opertaing device, it is used for processor controls begins to carry out the result who uses these operations when the processor except that this processor has finished the operation of executed in parallel separately operation, this multiprocessor control method comprises: the Power Limitation step, and it is used to limit the power supply to processor; Cancellation step, it is used for cancellation power supply restriction before an end corresponding operating of other processor, and one in described other processor is that last will finish the processor of corresponding operating in all other processors; With carry out controlled step, it is used to control this processor begins to carry out the result who uses these operations when other processor has finished the operation of executed in parallel separately operation.

According to described method, the multiprocessor opertaing device can be carried out power control to processor.

In addition, the invention provides a kind of integrated circuit that is used to control multiprocessor, this integrated circuit comprises: carry out control module, it can be operated and be used for processor controls begins to carry out the result of these operations of use when the processor except that this processor has finished the operation of executed in parallel separately operation; And power control unit, it can operate the power supply that is used to control to this processor, wherein when this processor has been subjected to the power supply restriction, cancellation power supply restriction before the end corresponding operating of this power control unit in other processor, one in described other processor is that last will finish the processor of corresponding operating in all other processors.

According to described structure, the integrated circuit that will be loaded on the multiprocessor opertaing device can be carried out power control to processor.

Description of drawings

Illustrate the description of the accompanying drawing of specific embodiments of the invention by following combination, these and other purpose of the present invention, advantage and feature will be apparent.In the drawings:

Fig. 1 is the block diagram that illustrates about the functional structure of the multicomputer system of first embodiment;

Fig. 2 is the block diagram that illustrates about the functional structure of the synchronous control unit of first embodiment;

Fig. 3 is the truth table of an example that the power supply state of each PE (processor elements) that is kept by power control unit is shown;

Fig. 4 is the figure that illustrates by an example of the structure of the performed program of PE;

Fig. 5 is the process flow diagram that illustrates by about the performed operation of the multiprocessor opertaing device of first embodiment;

Fig. 6 illustrates the sequential chart that is included in about the operational instances of each PE in the multiprocessor opertaing device of first embodiment and synchronous control unit;

Fig. 7 is the block diagram that illustrates about the functional structure of the multiprocessor opertaing device of the modification example of first embodiment;

Fig. 8 is the block diagram that illustrates about the functional structure of the synchronous control unit of the modification example of first embodiment;

Fig. 9 is the process flow diagram that illustrates by about the performed operation of the multiprocessor opertaing device of the modification example of first embodiment;

Figure 10 illustrates the sequential chart that is included in about the operational instances of each PE in the multiprocessor opertaing device of the modification example of first embodiment and synchronous control unit;

Figure 11 is the block diagram that illustrates about the functional structure of the multiprocessor opertaing device of second embodiment;

Figure 12 is the block diagram that illustrates about the functional structure of the synchronous control unit of second embodiment;

Figure 13 is the block diagram that illustrates about the functional structure of the accurate synchronous request signal generation unit of second embodiment;

Figure 14 is the process flow diagram that illustrates by about the performed operation of the multiprocessor opertaing device of second embodiment;

Figure 15 is the process flow diagram that illustrates by the performed operation of accurate synchronous request signal generation unit;

Figure 16 is the sequential chart about the example in time sequential routine of each PE and synchronous control unit that illustrates in a second embodiment;

Figure 17 is the block diagram that illustrates about the functional structure of the multiprocessor opertaing device of the modification example of second embodiment;

Figure 18 is the block diagram that illustrates about the functional structure of the synchronous control unit of the modification example of second embodiment;

Figure 19 is the process flow diagram that illustrates by about the performed operation of the multiprocessor opertaing device of the modification example of second embodiment;

Figure 20 is the sequential chart that illustrates about the operational instances of the multiprocessor opertaing device of the modification example of second embodiment;

Figure 21 is the figure that illustrates by about the example of the performed program of the multiprocessor opertaing device of second embodiment;

Figure 22 is the block diagram that illustrates about the modification example of the functional structure of synchronous control unit;

Figure 23 illustrates synchronous prediction judging unit, sets up the block diagram of example of the functional structure of judging unit or the like synchronously; With

Figure 24 is the block diagram of modification example that the functional structure of first embodiment is shown.

Embodiment

Embodiment about multiprocessor opertaing device of the present invention is described below with reference to the accompanying drawings.

＜the first embodiment 〉

＜structure 〉

Fig. 1 is the block diagram that illustrates about the functional structure of the multiprocessor opertaing device of first embodiment.

As shown in Figure 1, multiprocessor opertaing device 100 comprise PE 110a, PE 110b, PE 110c ..., PE 110n, synchronous control unit 120 and power control unit 130.

Each PE carries out the operation of distributing to it.Each PE output synchronous request signal SYNC otherwise during the point that can not further handle when arriving on program that unless other PE finishes their operation.This PE waits for then till receiving synchronous wait cancelling signal ACK.In this instructions hereinafter in the middle of, such point is called " synchronous points ".

As shown in Figure 2, synchronous control unit 120 comprise synchronous counter 201, synchronously set up judging unit 202, Power Limitation judging unit 203, predict judging unit 204 and sequencer 205 synchronously.

Synchronous counter 201 receives synchronous request signal SYNC from each PE, and reduces the synchronous number that the storer that is comprised in the itself is used as default.Subtract 1 whenever receive the synchronous request signal hour counter from PE.As acquiescence, synchronous counter 201 is set to the same number of number with PE.Whenever synchronous counter 201 reaches at 0 o'clock, it is reset and is updated to the number of the synchronously related PE of next round.Synchronous counter 201 also possesses function from the information of the synchronous request signal that is received to Power Limitation judging unit 203 which PE of output indication that exported.

Set up judging unit 202 synchronously and continuously monitor number on the synchronous counter 201.When this number reaches 0, set up judging unit 202 synchronously and set up signal ESTABLISH synchronously to sequencer 205 outputs.

Power Limitation judging unit 203 continuously monitors the number on the synchronous counter 201.When this number is shown as 2 or more for a long time, Power Limitation judging unit 203 is according to the information of the relevant PE that receives from synchronous counter 201, to the signal SUPPRESS of the Power Limitation of sequencer 205 output request PE.

Prediction judging unit 204 continuously monitors the number on the synchronous counter 201 synchronously.When this number becomes 1, predict that synchronously judging unit 204 is to the synchronous prediction signal ALMOST of sequencer 205 outputs.

Sequencer 205 is waited for cancelling signal ACK synchronously to each PE output, and output control signal CTRL is so that power controlling control module 130.When receiving when setting up signal ESTABLISH synchronously from setting up judging unit 202 synchronously, cancelling signal ACK is waited in output synchronously.Sequencer 205 also is one to receive SUPPRESS from Power Limitation judging unit 203, just to power control unit 130 output signal CTRL to reduce power consumption.When synchronous prediction judging unit 204 receives ALMOST, sequencer 205 to each the PE output signal CTRL that just is subjected to Power Limitation with the cancellation Power Limitation.

Power control unit 130 comprises the step-down transformer of the step-down that is used to carry out supply voltage and is used to make the voltage of decline to get back to the step-up transformer of initial voltage.Power control unit 130 switches between low-power consumption and normal power consumption with respect to each PE.There are two kinds of low-power consumption modes.Low-power consumption mode 1 is the degree that stops clock supply and supply voltage is reduced to the information (for example, operating result) that can not lose in the register.Low-power consumption mode 2 is only to stop clock supply, keeps the supply voltage under the normal condition.Power control unit 130 also provides processing clock to each PE.In addition, power control unit 130 is according to the request that comes from synchronous control unit 120, and which PE of output indication just is being subjected to the status signal STATUS of Power Limitation at present.

＜data 〉

Below describe by multiprocessor opertaing device 100 handled data.

At first, utilize the Power Limitation table 300 of Fig. 3 to describe the Power Limitation state how power control unit 130 manages PE.Power Limitation table 300 shows the supply of the clock supply 302 that is associated with PE number 301/do not supply and power supply state 303.

The supply of clock supply 302/do not supply is literal goes up indication to the clock supply of corresponding PE well afoot whether.Power supply state 303 each PE of indication are provided normal power or low-power.At this, for easy to understand, the supply of clock supply 302/do not supply is by " cut-out " and " unlatchings " the two one of illustrate, and power supply state 303 is low by " normally " with " " the two one of illustrate.Yet in fact, they are to be managed by the data in the corresponding registers " 1 " and " 0 ".

Next, an example of the program of being carried out by each PE is described with reference to Fig. 4.Fig. 4 shows the program example 400 that PE handles.Program example 400 comprises procedure incarnation 401 (describing in detail in the drawings), sends SYNC instruction 402 and the cycle criterion 403 of synchronous request signal SYNC when arriving synchronous points after finishing all processing.At this, cycle criterion 403 is always necessary, but describe it be because usually in multicomputer system a PE carry out a cycling.In program example 400, begin to carry out processing from higher instruction.When arriving synchronous points, PE is to synchronous control unit 120 output SYNC instructions 402.Then, PE enters waiting status.In a single day PE receives synchronous wait cancelling signal ACK, just begins to carry out follow-up processing from cycle criterion 403.

＜operation 〉

Below describe in detail by about the performed operation of the multiprocessor opertaing device 100 of first embodiment.

At first, utilize the process flow diagram of Fig. 5 to describe by about the performed operation of the multiprocessor opertaing device 100 of first embodiment.The operation of multiprocessor opertaing device 100 corresponds essentially to the operation of synchronous control unit 120.Therefore, hereinafter, the operation of synchronous control unit 120 is known as the operation of multiprocessor opertaing device 100.At this, illustrate to concentrate on operation upward till all PE arrive synchronous points and therefore cancel wait synchronously.

Each PE in the multiprocessor opertaing device 100 carries out the processing of giving itself.When its processing finished, PE was to synchronous control unit 120 output synchronous request signal SYNC, and this synchronous request signal indication PE has finished its processing and has been in waiting status to treat synchronously.

Synchronous control unit 120 receives the synchronous request signal SYNC (step S501) that is exported, and the synchronous counter in the synchronous control unit 120 201 is subtracted 1 (step S503).Set up judging unit 202 synchronously and judge whether synchronous counter 201 shown numbers are 0 (step S505).When judged result when being sure (step S505: be), setting up judging unit 202 synchronously sends and sets up signal ESTABLISH synchronously, and based on this, sequencer 205 is to power control unit 130 output control signal CTRL, providing clock, and wait for cancelling signal ACK (step S507) synchronously to each PE output to each PE.Handle by the counting on the replacement synchronous counter 201, make it then to be back to the number of PE and finish (step S509).

When synchronous counter 201 does not indicate 0 in step S505 (step S505: not), predict that synchronously judging unit 204 judges whether synchronous counter 201 indicates 1 (step S511).When judged result when being sure (step S511: be), predict that synchronously judging unit 204 sends synchronous prediction signal ALMOST (step S513).Sequencer 205 receives synchronous prediction signal ALMOST, obtain status signal STATUS from power control unit 130, this status signal is relevant information of carving the state of the PE that is subjected to Power Limitation at this moment, and is used to cancel the control signal CTRL (step S515) of Power Limitation to PE output.Then, sequencer 205 is used to stop clock stop signal CTRL (step S517) to the clock supply of the PE that exporting synchronous request signal SYNC to power control unit 130 output.Then, control turns back to step S501 so that carry out follow-up processing.

(step S511: not), Power Limitation judging unit 203 information according to the relevant PE that is received are not sent the power limit signal SUPPRESS that is used to ask Power Limitation (step S519) that points to PE when synchronous counter 201 indicates 1 in step S511.Then, sequencer 205 points to the CTRL signal that is used for power-limiting of PE to power control unit 130 outputs.Then, power control unit 130 reduces the power of the PE that points to appointment according to the CTRL signal that is received, and stops the clock supply for this PE.Then, control turns back to step S501 so that carry out follow-up processing.

As following, the operation of multiprocessor opertaing device 100 is described by the mode of example.

Fig. 6 is the sequential chart that operational instances is shown.In this sequential chart, PE 110a is the PE that at first finishes its processing, and PE 110b finishes its processing after following PE 110a closely.PE 110n is the PE that penult finishes its processing, and PE 110c is that last finishes its processing among all PE.

PE 110a at first arrives the synchronous points of program, and output synchronous request signal SYNCa (step S611).The n that the synchronous control unit 120 of reception synchronous request signal SYNCa will be provided with on synchronous counter 201 subtracts 1 to obtain n-1 (step S651).Synchronous control unit 120 is used to limit the control signal CTRL (step S652) of power that the PE 110a of synchronous request signal SYNCa has been exported in sensing to power control unit 130 output.According to the instruction that comes from synchronous control unit 120, the power that offers PE 110a from power control unit 130 is reduced to low, and stops the clock supply (step S613) to PE 110a.

Next, PE 110b arrives synchronous points, and to synchronous control unit 120 output synchronous request signal SYNCb (step S621).The synchronous control unit 120 that receives synchronous control signal SYNCb subtracts 1 to obtain n-2 (step S653) with the n-1 of synchronous counter 201.Synchronous control unit 120 is used to carry out the control signal (step S654) of Power Limitation that the PE 110b of synchronous request signal SYNCb has been exported in sensing to power control unit 130 output.Then, the power that offers PE 110b from power control unit 130 is reduced to low, and stops the clock supply (step S623) to PE 110b.

After this, all the other PE except that PE 110c and PE 110n export synchronous request signal SYNC respectively and enter low-power consumption mode 1.

Meanwhile, PE 110n arrives synchronous points, and to synchronous control unit 120 output synchronous request signal SYNCn (step S641).The synchronous control unit 120 that receives synchronous request signal SYNCn subtracts 1 with synchronous counter 201, makes synchronous counter 201 indications 1 (step S655) thus.Synchronous control unit 120 is used to stop control signal CTRL (step S656) to the clock supply of the PE 110n that exporting synchronous request signal SYNCn to power control unit 130 output.Then, PE 110n enters low-power consumption mode 2, is cut off (step S642) to the clock supply of PE110n from power control unit 130 under this low-power consumption mode.In addition, confirm that number on the synchronous counter 201 has become 1 synchronous prediction judging unit 204 and sent synchronous ready signal ALMOST to sequencer 205.Sequencer 205 comes 130 cancellations of indicated power control module according to status signal STATUS, and those have been subjected to the Power Limitation (step S657) of the PE of Power Limitation.

Be subjected to the PE of Power Limitation to begin to obtain normal power supply (step S661) once more, yet clock supply is not provided.Notice that power control unit 130 only stops the clock supply to the PE 110n that exports synchronous request signal SYNCn, and do not make PE 110n be in (step S642) under the low-power power supply state.

Then, each PE waits for till PE 110c arrives synchronous points.

When arriving synchronous points, PE 110c is to synchronous control unit 120 output synchronous request signal SYNCc (step S631).Then, synchronous control unit 120 subtracts 1 with synchronous counter 201, to obtain 0 (step S658).Confirm that number on the synchronous counter 201 has become 0 the judging unit 202 of setting up synchronously and set up signal ESTABLISH synchronously to sequencer 205 outputs.Receive the sequencer 205 of setting up signal ESTABLISH synchronously and be used to restart control signal CTRL, and wait for cancelling signal ACK (step S659) synchronously to each PE output to the clock supply of each PE to power control unit 130 outputs.When each PE received synchronous wait cancelling signal ACK, its waiting status was cancelled.Then, each PE carries out the operation (step S671) of back.In addition, the synchronous control unit 120 of having exported synchronous wait cancelling signal is reset to the number of PE with synchronous counter 201 (that is, n) (step S660) carries out follow-up processing then.

Attention is in the above-mentioned explanation of the sequential chart that uses Fig. 6, and wherein arrow is represented by dotted line, and its expression corresponding instruction is not directly carried out from synchronous control unit 120, but carries out via power control unit 130.

The modification example of＜the first embodiment 〉

In first embodiment, attempt energy-conservation by reducing the power that points to each PE.Yet in this modification example, power is stopped fully rather than is lowered.Can expect to realize further energy-saving effect by cutting off power supply up hill and dale.

＜structure 〉

Fig. 7 is the block diagram that illustrates according to the functional structure of the multiprocessor opertaing device 700 of the modification example of first embodiment.

Main function is identical with major function among first embodiment.Therefore, below concentrate on the difference with first embodiment.

At first, the PE difference of the appropriate section of first embodiment is together described.In the modification example of first embodiment, power supply is stopped under power save mode up hill and dale.Therefore, when having any other PE still in executable operations when PE arrives synchronous points, this PE must preserve environment (mainly being register value) with anti-lost environment.Given this, each PE possesses the function that its environment is saved to (not shown in FIG.) in separately the nonvolatile memory, unless this PE last or penult output synchronous request signal SYNC.Each PE also possesses reading and reflects the function of the environment of being preserved.

In addition, synchronous control unit 720 is by following executable operations.When reaching the state that only is left two PE that are not powered, sequencer 805 is in response to sending ALMOST from synchronous prediction judging unit 803, to the control signal CTRL of power control unit 730 outputs impelling power recovery.Then, synchronous control unit 720 receive indication relevant all when being in the status signal STATUS of information of the PE under the off-position already, be in the signal PREP of PE output the impelling environment recovery under the off-position to each.

Power control unit 730 is according to the instruction that comes from synchronous control unit 720, stops to export to the PE power supply of synchronous request signal SYNC, rather than reduces to its power supply.Power control unit 730 also restores electricity to the PE that is stopped power supply when receiving this class instruction from synchronous control unit 720.In case should be noted that the power supply of cutting off PE, often before the supply voltage of PE is stable, be that unit takies 1,000 cycle nearly with the unit of processing clock.At this, the low-power consumption mode that clock supply and power supply both stop to be called as " low-power consumption mode 3 " in this manual.

＜operation 〉

There is shown by about the performed operation of the multiprocessor opertaing device 700 of the modification example of first embodiment in the flow process of Fig. 9.At this, the counterpart with first embodiment is identical basically by the 700 performed operations of multiprocessor opertaing device.Therefore, only by the difference of following detailed description between them.

As shown in Figure 9, the content of step S919 is different from the content of the step S519 of first embodiment.At length, in first embodiment, the output power restricting signal is so that provide the control signal CTRL that impels the low-power consumption power supply for power control unit 130.Yet, in the present embodiment, but output power supply stop signal.When receiving this power supply stop signal, power control unit 730 stops to point to any power supply of having exported the PE of synchronous request signal after their environment has been saved.

Other operation is identical with the operation among first embodiment.

Figure 10 conforms to come illustrational sequential chart by revising Fig. 6 so that with this modification example.

As shown in figure 10, be different from the sequential chart of first embodiment like that, PE execution environment after sending synchronous request signal is preserved (step S1012 and S1022).After this, PE enters low-power consumption mode 3 (step S1013 and S1023).In addition, after the power supply to corresponding PE restarts (step S1071) and after its supply voltage value stabilization, the PE execution environment recovers (step S1072).

＜the second embodiment 〉

First embodiment of Miao Shuing and revise example among both should have three PE at least so that the present invention is effective in the above.Even second embodiment provides the multiprocessor opertaing device that also can tell on when the number of PE is 2.

＜structure 〉

Figure 11 shows the functional structure about the multiprocessor opertaing device 1100 of second embodiment.

As shown in figure 11, multiprocessor opertaing device 1100 comprise PE 1110a, PE 1110b ... PE 1110n, synchronous control unit 1120, power control unit 1130,

cache memory

1140a, 1140b ... 1140n, accurate synchronous request signal generation unit (being abbreviated as " Q unit " in the drawings) 1150a, 1150b ... 1150n and shared storage 1160.

PE 1100a, 1100b ... 1100n also exports the corresponding address signal of carrying out with PE of instruction respectively except that carrying out the operation of distributing to them.

The major function of synchronous control unit 1120 is power controlling control modules 130.Figure 12 illustrates this functional structure.As shown in figure 12, synchronous control unit 1120 comprise synchronous counter 1201, synchronously set up judging unit 1202, Power Limitation judging unit 1203, predict judging unit 1204, sequencer 1205 and accurate synchronous counter 1206 synchronously.

Synchronous counter 1201 receives synchronous request signal SYNC from each PE, and reduces the synchronous number that the storer that is comprised in the itself is used as default.Subtract 1 whenever from PE, receiving the synchronous request signal hour counter.As acquiescence, synchronous counter 1201 is set to the same number of number with PE.Whenever synchronous counter 1201 reaches at 0 o'clock, it is reset and is updated to the number of the PE that next round relates to synchronously.Synchronous counter 1201 also possesses function from the information of received synchronous request signal to Power Limitation judging unit 1203 which PE of output expression that exported.

Set up unit 1202 synchronously and continuously monitor number on the synchronous counter 1201.When this number reaches 0, set up judging unit 1202 synchronously and set up signal ESTABLISH synchronously to sequencer 1205 outputs.

Power Limitation judging unit 1203 continuously monitors the number on the synchronous counter 1201.When this number is shown as 2 or more for a long time, Power Limitation judging unit 1203 is according to the information of the relevant PE that receives from synchronous counter 1201, is used to ask the signal SUPPRESS of the Power Limitation of PE to sequencer 1205 outputs.

Prediction judging unit 1204 continuously monitors the number on the accurate synchronous counter 1206 synchronously.When this number becomes 1, predict that synchronously judging unit 1204 is to the synchronous prediction signal ALMOST of sequencer 1205 outputs.

Sequencer 1205 is waited for cancelling signal ACK synchronously to each PE output, and output control signal CTRL is so that power controlling control module 1130.When receiving when setting up signal ESTABLISH synchronously from setting up judging unit 1202 synchronously, cancelling signal ACK is waited in output synchronously.When Power Limitation judging unit 1203 receives SUPPRESS, sequencer 1205 also to power control unit 1130 output signal CTRL to reduce power consumption.When synchronous prediction judging unit 1204 receives ALMOST, sequencer 1205 to each the PE output signal CTRL that is subjected to Power Limitation with the cancellation Power Limitation.

The number that accurate synchronous counter 1206 will wherein be stored when receiving accurate synchronous request signal PRESYNC from PE subtracts 1.As acquiescence, accurate synchronous counter 1206 is set to the same number of number with PE.Whenever accurate synchronous counter 1206 reaches at 0 o'clock, it is reset and is updated to the number of the synchronously related PE of next round.

Power control unit 1130 is according to the instruction that comes from synchronous control unit 1120, and each PE is provided and stops clock/power.In addition, power control unit 1130 is according to the request that comes from synchronous control unit 1120, and which PE of output expression just is being subjected to the status signal STATUS of power/clock restriction at present.

Cache memory

1140a, 1140b ... 1140n is used for the impact damper of interim storage by the data of the operation generation of independent execution, and has the data contention of preventing and make that writing data into shared storage 1160 is easy to function.Each cache memory all can be visited from PE.This is useful, because if cache memory has been stored the data of another required PE of the operation of PE therein, and just directly access cache rather than shared storage 1160 of this PE then.

When PE reached be arranged in a little its operation synchronous points before accurate synchronous points the time, each accurate synchronous request

signal generation unit

1150a, 1150b ... 1150n exports accurate synchronous request signal.Specifically, as shown in figure 13, each accurate synchronous request signal generation unit comprises that all accurate address register 1301 synchronously and address meet judging unit 1302.Figure 13 only shows accurate synchronous request signal generation unit 1150n as an example, yet other accurate synchronous request signal generation unit all possesses substantially the same structure respectively.Accurate address register 1301 synchronously is stored in the address that arrives the programmed instruction that will carry out before the synchronous points.The address meets judging unit 1302 and monitors whether the address in the accurate address register synchronously mates the ADDRn that outputs to address bus.When ADDRn had match address in accurate SYN register 1301, the address met judging unit 1302 and sends accurate synchronous request signal.

Notice that preferably, consider the stable situation that will account for for a long time of supply voltage, the address that is arranged in the accurate address register 1301 synchronously is that the unit that has with processing clock is the instruction address in about 1,000 cycle of unit.

Employed all variablees in the operation that the whole multiprocessor of shared storage 1160 management is carried out.Each variable is to rewrite by request according to the operating result of this PE by each PE.In principle, the each permission is written to shared storage 1160 by a PE, so that prevent accessing competition.

Notice that each cache memory and shared storage 1160 all are the necessary structures of the common multicomputer system of shared storage type, and optional for the basic function of present embodiment.

＜operation 〉

Below describe in detail by about the performed operation of the multiprocessor opertaing device 1100 of second embodiment.

Figure 14 is the process flow diagram that illustrates by the performed operation of multiprocessor opertaing device 1100.In first embodiment, this flow chart description as the operation of the synchronous control unit 1120 of multiprocessor opertaing device 1100.

At first, synchronous control unit 1120 receives synchronous request signal SYNC or accurate synchronous request signal PRESYNC (step S1401).When receiving synchronous request signal SYNC (step S1401: be), synchronous counter 1201 subtracts 1 (step S1405).Then, set up judging unit 1202 synchronously and judge whether the number on the synchronous counter 1201 has become 0 (step S1407).

When judged result when being sure (step S1407: be), the clock supply that recovers each corresponding PE by means of power control unit 1130, and wait for that synchronously cancelling signal ACK outputs to each corresponding PE (step S1409).Then, replacement synchronous counter 1201 and processing finish (step S1411).

(step S1403: not), accurate synchronous counter 1206 subtracts 1 (step S1413) when receiving accurate synchronous request signal.Then, predict that synchronously judging unit 1204 monitors whether accurate synchronous counter 1206 has reached 0 (step S1415).When it becomes 0, synchronous prediction signal ALMOST is outputed to sequencer 1205.Then, sequencer 1205 is used to cancel control signal CTRL (step 1417) to the Power Limitation of the PE that is subjected to Power Limitation to power control unit 1130 output.Then, accurate synchronous counter 1206 is reset and is updated to the number identical with PE (step S1419).Control is back to step S1401 so that carry out follow-up processing.

When synchronous counter 1204 did not show 0 in step S1407, output needle was to the control signal CTRL that is used for Power Limitation (step S1421) of the PE that exports synchronous request signal.Then, control is back to step S1401 so that carry out follow-up processing.

Followingly describe by the performed operation of accurate synchronous request signal generation unit 1150 with reference to the process flow diagram shown in Figure 15.

The address signal that accurate address judging unit 1302 is synchronously judged in the address bus to be passed through whether conform to (step S1501) with the address of the synchronous address register 1301 of standard.When judged result when negating (step S1501: not), control be back to step S1501 in case whenever new address signal in address bus by the time carry out and judge.

When judged result when being sure (step S1501: be), accurate address synchronously meets unit 1302 to the accurate synchronous request signal PRESYNC of synchronous control unit 1120 outputs, and this signal indication operation has arrived accurate synchronous points.Then, control finishes.

Hereinafter, by case description the operation of multiprocessor opertaing device 1100.

Figure 16 is the sequential chart that operational instances is shown.In this sequential chart, PE 1110a is the PE that at first finishes its processing, and PE 1110n is immediately following finishing its processing after the PE 1110a.PE 1110b is that last finishes its processing among all PE.

When the synchronous address of standard met judging unit and judges that address signal ADDRa in the address bus is with the matching addresses that is stored among the accurate address register 1301a synchronously, accurate synchronous request signal generation unit 1150a generated and to synchronous control unit 1120 output accurate synchronous request signal PRESYNCa (step S1611).The synchronous control unit 1120 that receives accurate synchronous request signal PRESYNCa subtracts 1 with accurate synchronous counter 1206, it is arranged to n-1 (step S1641).

Next, reached the PE 1110a of synchronous points to synchronous control unit 1120 output synchronous request signal SYNCa (step S1643).The synchronous control unit 1120 that receives synchronous request signal SYNCa subtracts 1 with synchronous counter 1201, it is arranged to n-1 (step S1642).Then, Power Limitation judging unit 1203 is to sequencer 1205 output power restricting signal SUPPRESS.Sequencer 1205 is to the control signal CTRL that be used for power-limiting (step S1643) of power control unit 1130 output needles to PE 1110a.Power control unit 1130 begins to provide low-power by reducing voltage to PE1110a according to control signal CTRL, and stops the clock supply at PE 1110a.Under the restriction aspect power and the clock two, PE 1110a enters low-power consumption mode 1 (step S1613).

When reaching accurate synchronous points after PE 1110n follows PE 1110a, PE 1110n is to synchronous control unit 1120 output accurate synchronous request signal PRESYNCn (step S1631).The synchronous control unit 1120 that receives accurate synchronous request signal PRESYNCn subtracts 1 with accurate synchronous counter 1206, it is arranged to n-2 (step S1644).

When reaching synchronous points, PE 1110n is to synchronous control unit 1120 output synchronous request signal SYNCn (step S1632).The synchronous control unit 120 that receives synchronous request signal SYNCn subtracts 1 with synchronous counter 1201, it is arranged to n-2 (step S1645).Then, Power Limitation judging unit 1203 points to the power limit signal SUPPRESS that is used for power-limiting of PE 1110n to sequencer 1205 outputs.Sequencer 1205 points to the control signal CTRL that is used for power-limiting (step S1646) of PE 1110n then to power control unit 1130 outputs.Power control unit 1130 beginning that receives control signal CTRL provides low-power and stops clock supply at PE 1110n to PE 1110n.As a result, PE 1110n enters low-power consumption mode 1.

After this, whenever PE (except that PE 1110b) when reaching accurate synchronous points, the number on the accurate synchronous counter 1206 subtracts 1.In addition, whenever PE (except that PE 1110b) when reaching synchronous points, the number on the synchronous counter 1201 subtracts 1, carries out the Power Limitation at the PE that exports synchronous request signal whereby.

At last, PE 1110b reaches accurate synchronous points, and Plesiochronous Signal generation unit 1150b is to synchronous control unit 1120 output accurate synchronous request signal PRESYNCb (step S1621).When receiving accurate synchronous request signal PRESYNCb, synchronous control unit 1120 subtracts 1 with accurate synchronous counter 1206, it is arranged to 0 (step S1647).Confirm that accurate synchronous counter 1206 shown numbers have become 0, predict synchronously that then judging unit 1204 is to the synchronous prediction signal ALMOST of sequencer 1205 outputs.Sequencer 1205 outputs that receive the status signal STATUS of the information of indicating the PE that is subjected to Power Limitation from power control unit 1130 are used to cancel the control signal CTRL of the Power Limitation of (a plurality of) PE that is subjected to Power Limitation.In addition, accurate synchronous counter 1206 is reset and is updated to the number n (step S1648) of all PE.The PE that its Power Limitation is cancelled begin to obtain normal power (step S1614, S1634).

When PE 1110b reached synchronous points, synchronous request signal SYNCb was output to synchronous control unit 1120 (step S1622).The synchronous control unit 1120 that receives this last synchronous request signal SYNCb subtracts 1 with synchronous counter 1201, it is arranged to 0 (step S1649).When synchronous counter 1201 has become 0, set up judging unit 1202 synchronously and send and set up signal ESTABLISH synchronously.Sequencer 1205 is waited for cancelling signal ACK to power control unit 1130 output control signal CTRL synchronously with the recovered clock supply and to each PE output.In addition, replacement synchronous counter 1205 is to be updated to n (step S1650).

Each PE that receives synchronous cancelling signal ACK carries out follow-up processing (step S1660) after synchronous points separately.

The modification example of＜the second embodiment 〉

As in the modification example of first embodiment, this modification example of second embodiment also is the situation about stopping power supply up hill and dale.

The situation with second embodiment is identical basically with operation for primary structure.Therefore, below concentrate on the difference with second embodiment.

＜structure 〉

Figure 17 shows the functional structure about the multiprocessor opertaing device 1700 of the modification example of second embodiment.

About the multiprocessor opertaing device 1700 of this modification example have basically with second embodiment in the identical structure of counterpart.Be that with the difference of second embodiment multiprocessor opertaing device 1700 is equipped with such bus, promptly export synchronous ready signal PREP from synchronous control unit 1730 to each PE via this bus.At this, ready signal PREP is used to impel any PE execution environment that is under the off-position to recover synchronously.

In addition, the sequencer 1805 of synchronous control unit 1720 has the function of this synchronous ready signal PREP of output.This synchronous ready signal PREP be according to from the status signal STATUS of power control unit 1730 output, provide power and supply voltage to export after stable for once more each PE.

Accurate synchronous request signal generation unit 1750a, 1750b ... 1750n (being abbreviated as " Q unit " in the drawings) has accurate address register synchronously separately.The address of each accurate address register synchronously is all by considering that the needed time of environment recovery is provided with in addition the needed time except that power supply is stablized.Notice that to be that unit is minimum with the unit of processing clock take about 100 cycles to environment recovery.Therefore, required T.T. of power stability and environment recovery is approximately 1,100 cycle.Given this, it is desirable to, 1,100 cycle is provided with the address at the instruction address place in advance.

＜operation 〉

Below utilize the process flow diagram of Figure 19 to describe in detail by about the performed operation of the multiprocessor opertaing device 1700 of the modification example of second embodiment.

The step S1417 that is different from Figure 14 of second embodiment, in the step S1917 of Figure 19, synchronous control unit 1720 is exported synchronous ready signal PREP to be used to impel environment recovery to the PE that each is in off-position.

Other operation is identical with the operation among second embodiment.

Figure 20 is by revising the illustrational sequential chart that conforms to about Figure 16 of second embodiment so that with this modifications example.

As the sequential chart of sequential chart that can be by Figure 16 relatively and Figure 20 understand, below 2 be difference.First difference be in the modification example of second embodiment PE 1710a and PE 1710n execution environment preserve (step S2013, S2033).Second difference be each PE of having begun to obtain power supply (step S2015) after stable to its supply voltage, come execution environment to recover (step S2016) according to the synchronous ready signal PREP that receives from synchronous control unit 1720.

＜other attention 〉

So far described about multiprocessor opertaing device of the present invention according to embodiment.Yet much less, the present invention should not be limited to these above-mentioned instantiations, but can comprise other modification example.In these modification examples some have below been described.

(1) in the above-described embodiment, synchronous control unit is equipped with synchronous counter and accurate synchronous counter.Yet these counters are optional.

For example, synchronous control unit can have the structure shown in Figure 22.In this width of cloth figure,, each PE is used to transmit synchronous request signal SYNC for providing corresponding bus.Similarly, in order to transmit accurate synchronous request signal PRESYNC, also can provide corresponding bus (not shown in FIG.) for each PE.

In this case, the structure of predicting judging unit synchronously can be the circuit structure shown in Figure 23 A.For the purpose of simplifying the description, this width of cloth figure has described the situation that has four PE, just PEa, PEb, PEc and PEd.

Shown in Figure 23 A, predict that synchronously judging unit can be made of AND circuit and OR circuit.Each AND circuit design is become from all PE except that a PE to receive synchronizing signal.For example, 2300a is designed to the AND circuit: receive synchronous request signal SYNCa from PEa, receive synchronous request signal SYNCb and receive synchronous request signal SYNCc from PEc from PEb.When any AND circuit receives three signals, will represent that the signal of " 1 " outputs to the OR circuit.Therefore, be used to indicate will set up soon synchronous synchronous prediction signal ALMOST will be ready to output.

Figure 23 B for example understands an example of the structure of setting up judging unit synchronously in this case.

The Power Limitation judging unit can be by replacing the OR circuit of Figure 23 A to realize with the NOR circuit.

(2), predict synchronously that judging unit is worked as to export synchronous prediction signal ALMOST when number on the synchronous counter has become 1 at first embodiment and revise in the example.Yet, can synchronous counter show 2 or 3 o'clock output ALMOST.By such configuration, will allow more time to be used for stable power-supplying voltage.In addition, this structure can support latter two PE to finish the situation of their operation simultaneously.

(3) in the above description, second embodiment has the accurate synchronous request signal generation unit that is used to export accurate synchronous request signal.Yet, be provided for exporting the port of accurate synchronous request signal might for each PE.In this case, the instruction that is used for generating accurate synchronous request signal might be inserted in the middle of the performed program of each PE, determine the time of the accurate synchronous request signal of output whereby.Figure 21 shows the program example 2100 that is used in this class situation.In being applicable to this class multicomputer system of this example, probably can estimate to instruct the number (promptly about 1,000 cycle) of performance period of SYNC instruction from PRESYNC.Therefore, if necessary, consider the needed periodicity of environment recovery (about 100 cycles), can be by inserting the accurate synchronous request signal of PRESYNC instruction output.

Insert in the process of this class PRESYNC instruction when the program of description, whether 1,000 or 1,100 cycle should noting SYNC instruction front is corresponding to cycling or branch operation.

(4) in second above-mentioned embodiment and modification example thereof, the output time of accurate synchronous request signal is 1,000 or 1,100 cycle before the output respective synchronization request signal.Yet, the invention is not restricted to such structure.Can exist in the situation of end operation within 1,000 cycle.In this case, might before the period expires of being mentioned, export.

(5) in the above description, first embodiment and modification example thereof have the structure shown in Fig. 1.Yet they can be configured in Figure 24.

In Figure 24, each PE has synchronous control unit.In this case, each

synchronous control unit

2440a, 2440b, 2440c ... 2440n can both know the output state of the synchronous request signal of other PE except that the PE that is connected in the respective synchronization control module via bus.Therefore, synchronous control unit 2440 can be arranged under the control that distributes.Can expect to produce and identical effect in first embodiment and modification example thereof according to such structure.

(6) each unit of formation multiprocessor opertaing device can be implemented as part or whole LSI (large scale integrated circuit) or VLSI (VLSI (very large scale integrated circuit)).Perhaps, each unit can be implemented as the combination of a plurality of LSI or one or more LSI and other circuit.

(7) in above-mentioned example, low-power consumption mode 1 is described to supply voltage is reduced " degree that the information (for example, operating result) to register can not be lost ".Yet,, threshold voltage can be arranged to higher numerical value in order to reduce the power consumption that causes because of semi-conductive leakage current.At this threshold voltage of mentioning is to surpass the numerical value that its electric current will begin voltage mobile in circuit.Be set to threshold voltage if hang down numerical value, then produce leakage current possibly.It is meticulous more that semiconductor technology becomes, and leakage current is big more with the ratio of consumed power.Yet, high if threshold voltage is set to, be expected to a certain extent and can prevent leakage current.

(8) in the above-described embodiments, synchronous counter and accurate synchronous counter come respectively the number of synchronous request signal and the number of accurate synchronous request signal to be counted by subtracting from default value.Yet, perhaps might carry out addition so that these numbers are counted.With first embodiment this situation is described as an example.As acquiescence, " 0 " is set to synchronous counter 201.Then, when receiving synchronous request signal, synchronous counter 201 is added 1.In addition, predict that synchronously judging unit 204 has the structure of exporting synchronous prediction signal ALMOST when the number on the synchronous counter 201 reaches demonstration n-1.Set up judging unit 202 synchronously and have when the number on the synchronous counter 201 has become n the structure that signal ESTABLISH is set up in output synchronously.

(9), preferably design synchronous counter so that receive a synchronous request signal at every turn although specifically do not mention in the above description.Similarly, further preferably design accurate synchronous counter so that receive an accurate synchronous request signal at every turn.

Although fully described the present invention by example, should be noted in the discussion above that various variants and modifications will be conspicuous to those skilled in the art with reference to accompanying drawing.Therefore, in other words,, otherwise should think that they are included in the middle of the present invention unless such variants and modifications has broken away from scope of the present invention.

Claims

1. synchronous multiprocessor opertaing device that comprises a plurality of processors and control described a plurality of processors, wherein:

In described a plurality of processor each is all exported the synchronous request signal of the corresponding EO of expression, and

Described multiprocessor opertaing device comprises:

Synchronous control unit, based on reception to described synchronous request signal, when the quantity of the synchronous request signal that receives reaches predetermined number, output is used for cancelling the cancelling signal to each restriction of powering of described a plurality of processors, wherein said predetermined number is less than the sum of described a plurality of processors, and when the quantity of the synchronous request signal that receives did not reach described predetermined number, output is used for limiting described a plurality of processor, and any one had exported the power limit signal of its power of processor of synchronous request signal; And

Power control unit, be used for based on to reception from the described power limit signal of described synchronous control unit, limit by the power supply of the pointed processor of described power limit signal, and based on to the reception from the described cancelling signal of described synchronous control unit, cancellation is to the power supply restriction of the just confined processor of its power supply.

2. multiprocessor opertaing device as claimed in claim 1, wherein:

Described synchronous control unit a) comprise be used for synchronous counter that the number of the synchronous request signal that begun at described a plurality of processors to be exported after the operation is separately counted and b) output cancelling signal when the number counted when described synchronous counter has become number than described a plurality of processors and lacks one number.

3. multiprocessor opertaing device as claimed in claim 2, wherein:

After receiving new synchronous request signal, when the number of being counted by described synchronous counter did not reach described predetermined number yet, described synchronous control unit was to described power control unit output power restricting signal, and

According to the described power limit signal that receives, the power supply of any one has been exported in described a plurality of processors of described synchronous request signal in described power control unit restriction.

4. multiprocessor opertaing device as claimed in claim 1, wherein:

Described power control unit a) comprising: low-power power supply subelement, and it can be operated and be used to described a plurality of processor that the power lower than normal power is provided; With the normal power supply subelement, it can be operated and be used to provide normal power, and b) limit power supply to processor and c by means of described low-power power supply subelement) cancel the power supply restriction by means of described normal power supply subelement.

5. multiprocessor opertaing device as claimed in claim 1, wherein:

Described power control unit stops the processor power supply, and

In described a plurality of processor each is preserved the information about the register that is comprised in this respective processor after respective processor is exported synchronous request signal and before respective processor is stopped power supply; And

After the cancellation of described power control unit is to each the power supply restriction in described a plurality of processors, recover the information of being preserved.

6. synchronous multiprocessor opertaing device that comprises a plurality of processors and control described a plurality of processors, wherein:

Described multiprocessor opertaing device comprises:

A plurality of accurate synchronous request signal output units, it is corresponding one by one with described a plurality of processors, and when corresponding processor arrived the stage in the cycle that also remained predetermined number before corresponding operating finishes, each all operationally exported accurate synchronous request signal;

Synchronous control unit, based on reception to described accurate synchronous request signal, when the quantity of the accurate synchronous request signal that receives and described a plurality of processors total identical, output is used for cancelling the cancelling signal to each restriction of powering of described a plurality of processors, and based on reception to described synchronous request signal, when the quantity of the synchronous request signal that receives also was different from described a plurality of processors total, output is used for limiting described a plurality of processor, and any one had exported the power limit signal of its power of processor of synchronous request signal; And

7. multiprocessor opertaing device as claimed in claim 6, wherein:

Described synchronous control unit a) comprises synchronous counter, be used for the number of the synchronous request signal that begins at described a plurality of processors to be exported after the operation is separately counted, when and b) sum of the number of counting when described synchronous counter and described a plurality of processors is also inequality, the output power restricting signal, and

Described power control unit is based on the reception to described power limit signal, and the power supply of any one has been exported in described a plurality of processors of described synchronous request signal in restriction.

8. multiprocessor opertaing device as claimed in claim 6, wherein:

In described a plurality of accurate synchronous request signal output unit each a) comprising: address storaging unit, it can operate the address that is used for storing predetermined justice, and b) when the address that outputs to address bus with when described address storaging unit institute address stored is consistent, export accurate synchronous request signal.

9. multiprocessor opertaing device as claimed in claim 6, wherein:

In described a plurality of processor each when the instruction that is used to export accurate synchronous request signal is explained, is exported accurate synchronous request signal, and described instruction is described by the corresponding program that just is being performed.

10. multiprocessor opertaing device as claimed in claim 6, wherein:

11. multiprocessor opertaing device as claimed in claim 6, wherein:

Described power control unit stops the processor power supply, and

12. as any described multiprocessor opertaing device in claim 1 and 6, wherein:

Described power control unit provides clock in described a plurality of processors each, and restriction is to being provided clock by the indicated processor of described power limit signal.

13. one kind is used in and comprises a plurality of processors and control Poewr control method in the synchronous multiprocessor opertaing device of described a plurality of processors, may further comprise the steps:

In described a plurality of processor each is all exported the synchronous request signal that the corresponding operation of expression stops;

Based on reception to described synchronous request signal, when the quantity of the synchronous request signal that receives does not reach predetermined number, output is used for limiting described a plurality of processor, and any one has exported the power limit signal of power of the processor of synchronous request signal, and wherein said predetermined number is less than the sum of described a plurality of processors;

Limit by the power supply of the pointed processor of described power limit signal based on reception described power limit signal;

Based on the reception to described synchronous request signal, when the quantity of the synchronous request signal that receives reached described predetermined number, output was used for cancelling the cancelling signal to each restriction of powering of described a plurality of processors; And

Based on the reception to described cancelling signal, cancellation is to the power supply restriction of the just confined processor of its power supply.

14. one kind is used in and comprises a plurality of processors and control Poewr control method in the synchronous multiprocessor opertaing device of described a plurality of processors, may further comprise the steps:

Synchronous request signal output step, each that is used for impelling described a plurality of processors is all exported the synchronous request signal that the corresponding operation of expression stops;

A plurality of accurate synchronous request signal output steps, (i) it is corresponding one by one with described a plurality of processors, and (ii) each step all is used for exporting accurate synchronous request signal when corresponding processor arrives corresponding operating and also remains stage in cycle of predetermined number before stopping;

Power limit signal output step, be used for based on the reception to described synchronous request signal, output is used for limiting described a plurality of processor any one has exported the power limit signal of power of the processor of synchronous request signal when the sum of the quantity of the synchronous request signal that receives and described a plurality of processors is also inequality;

Conditioning step is based on the reception from the described power limit signal of described synchronous control unit being limited to by the power supply of the pointed processor of described power limit signal;

Cancelling signal output step, based on reception to described accurate synchronous request signal, when the quantity of the accurate synchronous request signal that receives and described a plurality of processors total identical, output is used for cancelling the cancelling signal to each restriction of powering of described a plurality of processors; And

Cancellation step, based on the reception to described cancelling signal, cancellation is to the power supply restriction of the just confined processor of its power supply.

15. one kind is installed in and comprises a plurality of processors and control integrated circuit in the synchronous multiprocessor opertaing device of described a plurality of processors, wherein:

In described a plurality of processor each is all exported the synchronous request signal that the corresponding operation of expression stops, and

Described multiprocessor opertaing device comprises:

16. one kind is installed in and comprises a plurality of processors and control integrated circuit in the synchronous multiprocessor opertaing device of described a plurality of processors, wherein:

Described multiprocessor opertaing device comprises:

A plurality of accurate synchronous request signal output units, it is corresponding one by one with described a plurality of processors, and each is all operated and is used for exporting accurate synchronous request signal when corresponding processor arrives corresponding operating and also remains stage in cycle of predetermined number before stopping;