CN1719902A - Coefficient pantagraph calculating module in multi-mode image encoding and decoding chips - Google Patents
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Abstract
This invention discloses a factor reducing-enlarging computing module in a multi-mode image code-decode chip including an operation unit, three signal input ends and output ends, among which, the first input is connected with factor DCP or the quantification parameter DSCTEPp for factor reducing-enlarging computation of the WMV9 protocol or one of factor QFA and quantification parameter QPA for the computation in protocol MPEG4, the second signal input is connected with one of DCP and DSCTEPp and connected with one of factor QFA and quantification parameter QPS, the third one is connected with the index parameter DSCTEPc in the factor reducing-enlarging formula of protocol WMR9 and quantification parameter QPX of protocol MPEG4. The operation unit carries out factor reducing-enlarging operation in terms of the formula: the first signal input parameter x that of the second/the third and outputs the result from the signal output end.
Description
Technical field
The present invention relates to the arithmetic element in a kind of multi-mode image encoding and decoding chips, the coefficient pantagraph calculating module in particularly a kind of multi-mode image encoding and decoding chips.
Technical background
In image encoding and decoding technique field now because multiple encoding and decoding standard can and deposit in a very long time, therefore can compatibility etc. multiple standards will become the characteristic of image chip product indispensability.This have multiple image coding and decoding algorithm to coexist, and the chip of compatible various protocols is called as " multi-mode image encoding and decoding chips ".The main a kind of technology path of multi-mode image encoding and decoding chips design at present is beyond the encoding and decoding nuclear of original certain agreement, increases the encoding and decoding nuclear of other agreements.In the code decode algorithm for WMV9 agreement and MPEG4 agreement, the coefficient convergent-divergent computing in its coefficient prediction is to carry out according to coefficient convergent-divergent operational formula separately respectively.
The coefficient convergent-divergent computing formula of MPEG4 agreement is:
(QFA*QPA)//QPx， ①
Wherein QFA is a coefficient, and QPA is a quantization parameter, and QPX is a quantization parameter, and its span is 1～31 integer, comprises 1 and 31.
The coefficient convergent-divergent computing formula of WMV9 agreement is:
Wherein DCp is a coefficient, and DCSTEPp is a quantization parameter, DCSTEP
cBe indexing parameter, its span is 1～31 integer, comprises 1 and 3l, DQScale[DCSTEP
c] be with DCSTEP
cBe the function of variable, its value list is as follows:
DCSTEP
c DQScale[DCSTEP
c]
1 262144
2 131072
3 87381
4 65536
…
8 32768
…
11 23831
…
14 18725
…
18 14564
…
22 11916
…
26 10082
…
28 9362
29 9039
30 8738
3 18456。
In multi-mode image encoding and decoding chips, for the coefficient convergent-divergent of realizing these two kinds of agreements according to above-mentioned formula calculates, have to adopt two different arithmetic elements to be calculated respectively in the prior art, therefore, the increase of hardware module quantity will certainly strengthen chip area, increases product cost.
Summary of the invention
The objective of the invention is:, provide a kind of coefficient pantagraph calculating module that reduces the multi-mode image encoding and decoding chips cost at the deficiencies in the prior art.
In order to solve the problems of the technologies described above, the technical solution used in the present invention is: the coefficient pantagraph calculating module in a kind of multi-mode image encoding and decoding chips, comprise arithmetic element, first signal input part, secondary signal input, the 3rd signal input part and signal output part, wherein:
Described first signal input part connects coefficient DCp that the coefficient convergent-divergent that is used for the WMV9 agreement calculates and of quantization parameter DCSTEPp, and is used for coefficient QFA that the coefficient convergent-divergent of MPEG4 agreement calculates and of quantization parameter QPA;
Described secondary signal input connects another among described coefficient DCp and the quantization parameter DCSTEPp, and among described coefficient QFA and the quantization parameter QPA another;
Indexing parameter DCSTEPc in the coefficient convergent-divergent computing formula of described the 3rd signal input part connection WMV9 agreement, and the quantization parameter QPX that is used for the coefficient convergent-divergent calculating of MPEG4 agreement;
Described arithmetic element will be from the parameter of first signal input part, secondary signal input and the input of the 3rd signal input part according to formula:
, carry out the coefficient convergent-divergent and calculate, and result of calculation is exported from described signal output part.
Preferably, described arithmetic element is made of multiplier and divider, and described multiplier is used for realizing that the multiplication between parameter that the coefficient convergent-divergent calculates calculates, and described divider is used for realizing the division calculation between the parameter of coefficient convergent-divergent computing.
Further, two multiplier inputs of described multiplier can connect described first signal input part and secondary signal input respectively, its product output connects the dividend input of described divider, the divisor input of described divider connects described the 3rd signal input part, and its merchant's output connects described signal output part.
Further, the dividend input of described divider can connect described first signal input part, described divisor input connects described the 3rd signal input part, its merchant's output connects a multiplier input of described multiplier, another multiplier input of described multiplier connects described secondary signal input, and the product output of described multiplier connects described signal output part.
Further, described divider can adopt pipelining divider to substitute.
Preferably, described arithmetic element can be made of adder and multiplier and reciprocal table, described adder and multiplier is used for realizing the calculating of multiplication and addition between coefficient that the coefficient convergent-divergent calculates, the inverse of described reciprocal table stored indexing parameter DCSTEPc and quantization parameter QPX, and be index with the indexing parameter DCSTEPc or the quantization parameter QPX of input, the reciprocal value that output is corresponding.
Further, two multiplier inputs of described adder and multiplier can connect first signal input part and secondary signal input respectively, its addend input is used for input parameter 0x20000, the input of described reciprocal table connects described the 3rd signal input part, its output connects in two multiplier inputs of described adder and multiplier, in two multiplier inputs of described adder and multiplier another also is connected with its output, and described signal output part connects the output of described adder and multiplier.
Further, described adder and multiplier can be provided with two, comprise first adder and multiplier and second adder and multiplier, wherein two of first adder and multiplier multiplier inputs connect first signal input part and secondary signal input respectively, its output connects a multiplier input of described second adder and multiplier, the input of described reciprocal table connects described the 3rd signal input part, its output connects another multiplier input of described second adder and multiplier, the addend input input parameter 0x20000 of described second adder and multiplier, its output connects described signal output part.
Further, described first adder and multiplier can adopt multiplier to replace.
Preferably, the span of described quantization parameter QPX and indexing parameter DCSTEPc can be the integer between 1 to 31, and comprises integer 1 and 31.
In technique scheme, the present invention is owing to realized adopting a hardware module, i.e. arithmetic element, just can realize that the coefficient convergent-divergent under two kinds of agreements of MPEG4 and WMV9 calculates, relative prior art, can simplify hardware configuration in the multi-mode image encoding and decoding chips, reduce cost, save chip area.
Description of drawings
Accompanying drawing 1 is the block diagram of embodiments of the invention 1;
Accompanying drawing 2 is the operation time sequence figure of embodiments of the invention 1;
Accompanying drawing 3 is the block diagram of embodiments of the invention 2;
Accompanying drawing 4 is the block diagram of embodiments of the invention 3;
Accompanying drawing 5 is the operation time sequence figure of embodiments of the invention 3;
Accompanying drawing 6 is the block diagram of embodiments of the invention 4;
Accompanying drawing 7 is the operation time sequence figure of embodiments of the invention 4.
Embodiment
Below in conjunction with Figure of description and specific embodiment the present invention is described in further detail.
Technological core of the present invention is to adopt a hardware module, the coefficient convergent-divergent calculating of realization MPEG4 agreement and WMV9 agreement.
At first, be necessary to explain that the present invention can adopt the reason of a hardware module.
Analyze the function DQScale[DCSTEP of WMV9 agreement
c] value, can find that they can be expressed as:
262144d＝40000H＝2
18/1，
131072d＝20000H＝2
18/2，
87381d＝15555H＝2
18/3，
65536d＝10000H＝2
18/4，
…
32768d＝8000H＝2
18/8，
…
21845d＝5555H＝2
18/12，
…
16384d＝4000H＝2
18/16，
…
13107d＝3333H＝2
18/20，
…
10923d＝2AABH＝2
18/24，
…
9362d＝2492H＝2
18/28，
…
8456d＝2108H＝2
18/31。
Through above-mentioned conclusion, we find function DQScale[DCSTEP in the prior art
c] look-up table be a reciprocal table, the data of its storage are the unsigned number of 19bit, the 18bit that moves to right after multiplication is finished corresponding just divided by 2
18
Also can sum up a formula by above-mentioned conclusion:
DQScale[DCSTEP
c]＝2
18/DCSTEP
c ③
In this formula substitution formula 2, obtain:
Contrast equation 1 and formula 4 can be found all to have a multiplication and a division in two formula, can be expressed as: Y=A*B/C, in addition, as the indexing parameter DCSTE in the coefficient convergent-divergent computing formula of the WMV9 agreement of divisor
c, and the quantization parameter QPX of the coefficient convergent-divergent of MPEG4 agreement calculating, the span of the two all is the integer between 1～31, comprises 1 and 31.Therefore their reciprocal value also can be by formula 3 expressions.
In addition, owing to need the result of calculation 18bit that moves to right, the essence that adds 0x20000 so is to round up in formula 2 and the formula 4.
And in the formula 4, owing to after multiplication and division calculation finish, the result need be multiply by 2
18, be about to the result and move to left 18.After carrying out additional calculation, need again the result is moved to right 18.So, this formula can be reduced to:
Analyze as can be known thus, the formula 1 that the coefficient convergent-divergent of MPEG4 agreement calculates and the coefficient convergent-divergent formula 2 of WMV9 agreement all can be expressed as:
Y=A*B/C, wherein C is quantization parameter QPX or indexing parameter DCSTEP
c
Also can be expressed as:
Y=A*B*D, wherein D is quantization parameter QPX or indexing parameter DCSTEP
cReciprocal value.
Like this, the identical point that we have just found the coefficient convergent-divergent of MPEG4 agreement and WMV9 agreement to calculate, thus can adopt an arithmetic element, realize that the coefficient convergent-divergent of two kinds of agreements calculates.
Embodiment 1:
With reference to figure 1, the coefficient pantagraph calculating module in a kind of multi-mode image encoding and decoding chips that present embodiment provides comprises arithmetic element A, first signal input part 1, secondary signal input 2, the 3rd signal input part 3 and signal output part 4, wherein:
Described first signal input part 1 connects coefficient DCp that the coefficient convergent-divergent that is used for the WMV9 agreement calculates and of quantization parameter DCSTEPp simultaneously, and is used for coefficient QFA that the coefficient convergent-divergent of MPEG4 agreement calculates and of quantization parameter QPA; In the present embodiment, described first signal input part, 1 coefficient of connection DCp and coefficient QFA.
Described secondary signal input 2 connects another among described coefficient DCp and the quantization parameter DCSTEPp simultaneously, and among described coefficient QFA and the quantization parameter QPA another; In the present embodiment, described secondary signal input 2 connects quantization parameter DCSTEPp and quantization parameter QPA.
Described the 3rd signal input part 3 connects the indexing parameter DCSTEPc in the coefficient convergent-divergent computing formula of WMV9 agreement simultaneously, and is used for the quantization parameter QPX that the coefficient convergent-divergent of MPEG4 agreement calculates;
Described arithmetic element A will be from the parameter of first signal input part 1, secondary signal input 2 and 3 inputs of the 3rd signal input part according to formula:
, carry out the coefficient convergent-divergent and calculate, and result of calculation is exported from described signal output part 4.
In the present embodiment, described arithmetic element A is made of multiplier and divider, and described multiplier is used for realizing that the multiplication between parameter that the coefficient convergent-divergent calculates calculates, and described divider is used for realizing the division calculation between the parameter of coefficient convergent-divergent computing.
Two multiplier inputs of described multiplier connect described first signal input part 1 and secondary signal input 2 respectively, its product output connects the dividend input of described divider, the divisor input of described divider connects described the 3rd signal input part 3, and its merchant's output connects described signal output part 4.
The computing module that present embodiment provides when the coefficient convergent-divergent that carries out the WMV9 agreement calculates, obtains coefficient DCp from first signal input part 1, obtains quantization parameter DCSTEPp from secondary signal input 2, obtains indexing parameter DCSTEPc from the 3rd signal input part 3.In multiplier, finish the multiplying of coefficient DCp and quantization parameter DCSTEPp, and this product is imported divider as dividend, in divider, finish the calculating that removes with indexing parameter DCSTEPc, thereby directly obtain the coefficient convergent-divergent result of calculation of WMV9.
When the coefficient convergent-divergent that carries out the MPEG4 agreement calculates, obtain coefficient QFA from first signal input part 1, obtain quantization parameter QPA from secondary signal input 2, obtain quantization parameter QPX from the 3rd signal input part 3.In multiplier, finish the multiplying of coefficient QFA and quantization parameter QPA, and this product is imported divider as dividend, in divider, finish the calculating that removes with quantization parameter QPX, thereby directly obtain the coefficient convergent-divergent result of calculation of MPEG4 agreement.
In order to verify the performance of present embodiment scheme, we adopt the multiplier that cell library provided of Synopsys company and divider to realize this scheme.Be specially:
The work clock of determining system is 166M, so the critical path of module, its time-delay should be less than 6ns.
(A_WIDTH=12 B_WIDTH=6) realizes multiplication, and division is realized with one 17/6 divider with a multiplier DW02_mult#.
At first estimate the area of multiplier, its report file is as follows:
****************************************
Report：area
Design:VDEC_SMULTI12X6P0 (title of multiplier in the cell library of Synopsys company)
****************************************
Library (s) Used:UMC018AG_AASW (title of cell library)
Total area:8298.486328 (area value of estimation)
The critical path of this multiplier is 5.58ns, less than 6ns, therefore can finish this computing in a clock cycle.
Below we estimate divider, call the DW02_divide module, its area report file is:
****************************************
Report：area
Design：dw_div
****************************************
Library(s)Used：UMC018AG_AASW
Total?area：45839.781250
The critical path of this divider is 20.00ns, need finish in 4 clock cycle.
By above-mentioned estimation as can be seen:
The area of this programme: a multiplier and a divider area and:
8298+45839＝54137
The sequential of this programme as shown in Figure 2.
Be subjected to the restriction of divider critical path, the computing frequency of this scheme is: per 4 cycles are finished once-through operation.
Embodiment 2:
With reference to figure 3, present embodiment only is that with the difference of embodiment 1 elder generation carries out division arithmetic with the parameter that first signal input part 1 is connected with the parameter that the 3rd signal input part 3 is connected, and the parameter that secondary signal input 2 is connected and the result of division arithmetic multiply each other then.
Embodiment 3:
With reference to figure 4, the difference of present embodiment and embodiment 1 only is to adopt pipelining divider to substitute
Divider among the embodiment 1.
This performance change that substitutes the aspects such as speed, area and power consumption that will cause module.We verify as follows to this:
The work clock of determining system is 166M, so the critical path of module, its time-delay should be less than 6ns.
Divider changes the data rate that pipeline organization can improve system into, and its algorithm is from the manual calculations of binary division.We finish twice subtraction in a level production line, the pipeline series of its needs is so:
(17+6)/2＝11.5
Be that we need 12 level production lines
Estimate the area of divider, its report file is as follows:
****************************************
Report：area
Design：ADCP_SCALE_PE
****************************************
Library(s)Used：UMC018AG_AASW
Total?area：69986.791052
The time of the critical path of pipelining divider is 5.72ns.
Therefore, the area of this programme: a multiplier and a pipelining divider area and:
8298+69986＝78284
Shown in the timing reference accompanying drawing 5 of this programme.Because it has adopted pipeline organization, it can receive a new computing in each cycle.But, its stand-by period is 13 cycles.
Among 3 kinds of embodiment that provide previously, all be to adopt this model of Y=A*B/C to realize arithmetic element.To provide the embodiment that adopts the Y=A*B*D model to realize arithmetic element below.
Embodiment 4:
With reference to figure 6, three parameters that signal input part connected of present embodiment can be identical with embodiment 1.Its arithmetic element A is made of adder and multiplier and reciprocal table, described adder and multiplier is used for realizing the calculating of multiplication and addition between coefficient that the coefficient convergent-divergent calculates, the inverse of described reciprocal table stored indexing parameter DCSTEPc and quantization parameter QPX, and be index with the indexing parameter DCSTEPc or the quantization parameter QPX of input, the reciprocal value that output is corresponding.
Though shown in Fig. 6 is two adder and multipliers, these two adder and multipliers are actually same adder and multiplier, and we use it at timesharing, thereby finish different calculation procedures.
Two multiplier inputs of this adder and multiplier connect first signal input part and secondary signal input respectively, its addend input input parameter 0x20000, the input of described reciprocal table connects described the 3rd signal input part, its output connects in two multiplier inputs of described adder and multiplier, in two multiplier inputs of described adder and multiplier another also is connected with its output, and described signal output part connects the output of described adder and multiplier.
During the work of this coefficient pantagraph calculating module, when the coefficient convergent-divergent that carries out the WMV9 agreement calculates, obtain coefficient DCp from first signal input part 1, obtain quantization parameter DCSTEPp, obtain indexing parameter DCSTEPc from the 3rd signal input part 3 from secondary signal input 2.Adder and multiplier is at first finished the multiplying of coefficient DCp and quantization parameter DCSTEPp, in next sequential the gained product is input to an one multiplier input then, simultaneously reciprocal table with indexing parameter DCSTEPc as index, from the inverse of its storage, find corresponding inverse, as DCSTEPc is 1 o'clock, finding its inverse is 262144, it is 2 o'clock, thereby find its another multiplier input that this value of searching is outputed to adder and multiplier for 131072...... reciprocal, adder and multiplier multiplies each other the value of two multiplier inputs, and add parameter 0x20000 on its addend input, at last with the result by signal output part 4 outputs.In actual applications, need this result's binary value is moved to right 18 the coefficient convergent-divergent result of calculation under the final WMV9 agreement of the i.e. number of winning the confidence output 4 output results' the 19th conduct.
When the coefficient convergent-divergent that carries out the MPEG4 agreement calculates, adder and multiplier at first will multiply each other from first signal input part 1 coefficient QFA that obtains and the quantization parameter QPA that obtains from secondary signal input 2, in next sequential its product is input to an one multiplier input after finishing, simultaneously, the quantization parameter QPX that its another multiplier input acquisition reciprocal table is imported according to the 3rd signal input part 3 searches the reciprocal value of output, and adder and multiplier multiplies each other these two values.In the MPEG4 agreement, the addition input of adder and multiplier is not imported any value.After finishing all multiplyings, the product that adder and multiplier will obtain at last outputs to signal output part 4 as final coefficient scaled results.
System verification is as follows:
The work clock of determining system is 166M, so the critical path of module, its time-delay should be less than 6ns.
Use an adder and multiplier MAC_DW20X17, finish above-mentioned computing.
Its area assessment file is:
****************************************
Report：area
Design：MAC_ADCP
****************************************
Library(s)Used：UMC018AG_AASW
Total?area：67587.320312
Estimate the sequential of adder and multiplier, the time of critical path is 5.08ns in its report file
Its sequential chart as shown in Figure 7.
It finishes once-through operation needs 2 clock cycle.
In addition, the one of ordinary skilled in the art should know, the technical conceive of present embodiment can also adopt multiple scheme to realize, as adopting two adder and multipliers, comprise first adder and multiplier and second adder and multiplier, wherein two of first adder and multiplier multiplier inputs connect first signal input part and secondary signal input respectively, its output connects a multiplier input of described second adder and multiplier, the input of described reciprocal table connects described the 3rd signal input part, its output connects another multiplier input of described second adder and multiplier, the addend input input parameter 0x20000 of described second adder and multiplier, its output connects described signal output part.
For another example, can adopt the described adder and multiplier of combination replacement of multiplier and adder.
And for example, can adopt multiplier to substitute described first adder and multiplier.
Also as, can change reciprocal table output link position, make the multiplying between the output valve of parameter that arithmetic element finishes the input of first signal input part or secondary signal input earlier and reciprocal table, and then finish the multiplication and the add operation of remainder.
……
Although the present invention comes the coefficient pantagraph calculating module in the multi-mode image encoding and decoding chips is described in detail with the foregoing description, but the present invention is not limited in above embodiment, and can extend to those of ordinary skill in the art by reading the apparent and easy to know embodiment that above embodiment expects.
Therefore, any change or modification that those of ordinary skill in the art has done the coefficient pantagraph calculating module in the multi-mode image encoding and decoding chips of the present invention ought to drop within the present invention's claim scope required for protection.
Claims (10)
1, the coefficient pantagraph calculating module in a kind of multi-mode image encoding and decoding chips comprises arithmetic element, first signal input part, secondary signal input, the 3rd signal input part and signal output part, wherein:
Described first signal input part connects coefficient DCp that the coefficient convergent-divergent that is used for the WMV9 agreement calculates and of quantization parameter DCSTEPp, and is used for coefficient QFA that the coefficient convergent-divergent of MPEG4 agreement calculates and of quantization parameter QPA;
Described secondary signal input connects another among described coefficient DCp and the quantization parameter DCSTEPp, and among described coefficient QFA and the quantization parameter QPA another;
Indexing parameter DCSTEP in the coefficient convergent-divergent computing formula of described the 3rd signal input part connection WMV9 agreement
c, and the quantization parameter QPX that is used for the coefficient convergent-divergent calculating of MPEG4 agreement;
Described arithmetic element will be from the parameter of first signal input part, secondary signal input and the input of the 3rd signal input part according to formula:
Carry out coefficient
Convergent-divergent calculates, and result of calculation is exported from described signal output part.
2, the coefficient pantagraph calculating module in the multi-mode image encoding and decoding chips according to claim 1, it is characterized in that: described arithmetic element is made of multiplier and divider, described multiplier is used for realizing that the multiplication between parameter that the coefficient convergent-divergent calculates calculates, and described divider is used for realizing the division calculation between the parameter of coefficient convergent-divergent computing.
3, as the coefficient pantagraph calculating module in the multi-mode image encoding and decoding chips as described in the claim 2, it is characterized in that: two multiplier inputs of described multiplier connect described first signal input part and secondary signal input respectively, its product output connects the dividend input of described divider, the divisor input of described divider connects described the 3rd signal input part, and its merchant's output connects described signal output part.
4, as the coefficient pantagraph calculating module in the multi-mode image encoding and decoding chips as described in the claim 2, it is characterized in that: the dividend input of described divider connects described first signal input part, described divisor input connects described the 3rd signal input part, its merchant's output connects a multiplier input of described multiplier, another multiplier input of described multiplier connects described secondary signal input, and the product output of described multiplier connects described signal output part.
5, as the coefficient pantagraph calculating module in the multi-mode image encoding and decoding chips as described in the claim 2,3 or 4, it is characterized in that: described divider adopts pipelining divider to substitute.
6, the coefficient pantagraph calculating module in the multi-mode image encoding and decoding chips according to claim 1, it is characterized in that: described arithmetic element is made of adder and multiplier and reciprocal table, described adder and multiplier is used for realizing the calculating of multiplication and addition between coefficient that the coefficient convergent-divergent calculates, described reciprocal table stored indexing parameter DCSTEP
cWith the inverse of quantization parameter QPX, and the indexing parameter DCSTEP to import
cOr quantization parameter QPX is index, the reciprocal value that output is corresponding.
7, as the coefficient pantagraph calculating module in the multi-mode image encoding and decoding chips as described in the claim 6, it is characterized in that: two multiplier inputs of described adder and multiplier connect first signal input part and secondary signal input respectively, its addend input is used for input parameter 0x20000, the input of described reciprocal table connects described the 3rd signal input part, its output connects in two multiplier inputs of described adder and multiplier, in two multiplier inputs of described adder and multiplier another also is connected with its output, and described signal output part connects the output of described adder and multiplier.
8, as the coefficient pantagraph calculating module in the multi-mode image encoding and decoding chips as described in the claim 6, it is characterized in that: described adder and multiplier is provided with two, comprise first adder and multiplier and second adder and multiplier, wherein two of first adder and multiplier multiplier inputs connect first signal input part and secondary signal input respectively, its output connects a multiplier input of described second adder and multiplier, the input of described reciprocal table connects described the 3rd signal input part, its output connects another multiplier input of described second adder and multiplier, the addend input input parameter 0x20000 of described second adder and multiplier, its output connects described signal output part.
9, as the coefficient pantagraph calculating module in the multi-mode image encoding and decoding chips as described in the claim 8, it is characterized in that: described first adder and multiplier adopts multiplier to replace.
10, as the coefficient pantagraph calculating module in the multi-mode image encoding and decoding chips as described in claim 1 or 6, it is characterized in that: described quantization parameter QPX and indexing parameter DCSTEP
cSpan be integer between 1 to 31, and comprise integer 1 and 31.
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| CNB2005100877673A CN100370834C (en) | 2005-08-08 | 2005-08-08 | Coefficient pantagraph calculating module in multi-mode image encoding and decoding chips |
| US11/262,150 US7869504B2 (en) | 2005-08-08 | 2005-10-28 | Coefficient scaling operational units |
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| US5146324A (en) * | 1990-07-31 | 1992-09-08 | Ampex Corporation | Data compression using a feedforward quantization estimator |
| JP3123286B2 (en) * | 1993-02-18 | 2001-01-09 | ソニー株式会社 | Digital signal processing device or method, and recording medium |
| US5479166A (en) * | 1993-11-30 | 1995-12-26 | Texas Instruments Incorporated | Huffman decoding method, circuit and system employing conditional subtraction for conversion of negative numbers |
| JPH0818956A (en) * | 1994-06-28 | 1996-01-19 | Intetsukusu Corp:Kk | Method and device for encoding image data |
| US6101276A (en) * | 1996-06-21 | 2000-08-08 | Compaq Computer Corporation | Method and apparatus for performing two pass quality video compression through pipelining and buffer management |
| JP3246715B2 (en) * | 1996-07-01 | 2002-01-15 | 松下電器産業株式会社 | Audio signal compression method and audio signal compression device |
| US6529460B1 (en) * | 1998-01-31 | 2003-03-04 | Seagate Technology Llc | Detection of pulse peak instance and amplitude in a storage drive |
| US6282631B1 (en) * | 1998-12-23 | 2001-08-28 | National Semiconductor Corporation | Programmable RISC-DSP architecture |
| US20020016161A1 (en) * | 2000-02-10 | 2002-02-07 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and apparatus for compression of speech encoded parameters |
| JP3561485B2 (en) * | 2000-08-18 | 2004-09-02 | 株式会社メディアグルー | Coded signal separation / synthesis device, difference coded signal generation device, coded signal separation / synthesis method, difference coded signal generation method, medium recording coded signal separation / synthesis program, and difference coded signal generation program recorded Medium |
| US6882685B2 (en) * | 2001-09-18 | 2005-04-19 | Microsoft Corporation | Block transform and quantization for image and video coding |
| US7336711B2 (en) * | 2001-11-16 | 2008-02-26 | Ntt Docomo, Inc. | Image encoding method, image decoding method, image encoder, image decode, program, computer data signal, and image transmission system |
| WO2004030369A1 (en) * | 2002-09-27 | 2004-04-08 | Videosoft, Inc. | Real-time video coding/decoding |
| US7280595B1 (en) * | 2003-10-21 | 2007-10-09 | Redrock Semiconductor, Ltd. | Post-inverse-quantization AC prediction with a unified variable-length-decoding and inverse-quantization stage |
| US7620103B2 (en) * | 2004-12-10 | 2009-11-17 | Lsi Corporation | Programmable quantization dead zone and threshold for standard-based H.264 and/or VC1 video encoding |
| US8576924B2 (en) * | 2005-01-25 | 2013-11-05 | Advanced Micro Devices, Inc. | Piecewise processing of overlap smoothing and in-loop deblocking |
| US7895250B2 (en) * | 2005-05-25 | 2011-02-22 | Qualcomm Incorporated | Fixed point integer division techniques for AC/DC prediction in video coding devices |
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| US7869504B2 (en) | 2011-01-11 |
| CN100370834C (en) | 2008-02-20 |
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