CN1713164A - DMA controller and data transmission with multi-transaction discretionary process - Google Patents
DMA controller and data transmission with multi-transaction discretionary process Download PDFInfo
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- CN1713164A CN1713164A CN 200510027972 CN200510027972A CN1713164A CN 1713164 A CN1713164 A CN 1713164A CN 200510027972 CN200510027972 CN 200510027972 CN 200510027972 A CN200510027972 A CN 200510027972A CN 1713164 A CN1713164 A CN 1713164A
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Abstract
A DMA controller is prepared by connecting itself to both system bus and equipment bus as well as to in - chip processor, in - chip storage and system data communication module for providing data channel between said module and said storage. The data transmission method includes using processor to write all transaction requests in storage by form of transmission - description symbol and connecting them to be chain table, arranging transmission for each transaction by using DMA controller to read in those symbols autonomously from storage.
Description
Technical field
The invention belongs to microelectronics technology, be specifically related to a kind of DMA (Direct Memory Access, direct memory access (DMA)) data transmission method of controller and eventful affair transmission relates in particular to a kind of dma controller and the data transmission method that can independently handle eventful affair transmission requirement according to the transmission descriptor.
Background technology
In traditional System on Chip/SoC design, dma controller (DMAC) is an add-on module on the system bus, it can replace the processor control data when processor does not need to take bus between storer and storer, perhaps between storer and the data communication module, perhaps transmit between data communication module and the data communication module.Its advantage is to have avoided processor all will control each I/O transmission in data transmission procedure, and processor is freed from heavy data transfer task.Traditional chip system structure that has dma controller as shown in Figure 1, system bus is connected by special bridge module (107) with device bus, dma controller (103) is not on data channel, but control by each data communication module of special control pair, receive and respond their transmission requests, as USB module (106), and, dma controller within it portion's register accept processor (101) write configuration after, can independently arrange data transmission procedure one time, dma controller will transmit the mode of result by the processor read register and return to processor after transmission is finished.
According to the difference of system architecture, each data communication module can respectively carry a dma controller, also can the multiplexing dma controller of several data communication modules.No matter be any system architecture, its DMA workflow all as shown in Figure 2.At first data communication module sends transmission requests (201), and DMA sends bus application (202); The application of processor responding DMA bus waits for that bus disposes the register in the dma controller in the time of the free time, authorizes dma controller to begin to initiate once transmission (203), and this step needs the participation of processor; Subsequently, DMA control beginning place of processor is handled and is arranged a data transmission procedure (204), comprises the replacing of storage address, the buffering of data, the supervision of transmission course etc.After once transmission is finished (205), processor participates in transmission course once more, read in the information in the status register of dma controller, judge whether to arrange to retransmit (206), perhaps whether arrange next this transmission (207), perhaps finish transmission (208) this time, under preceding two kinds of situations, processor all needs to write once more the operation note of dma controller.
Present integrated circuit SOC (system on a chip) (SOC) comprises the system of eventful affair transmission requirement often, as have a system of usb host controller module, because according to the usb protocol requirement, the data length of each affairs transmission has maximal value (as being 512byte) under the bulk transfer condition of USB2.0, so each data that receive or send 512byte, processor just must DMA requests of response.Like this,, improved system effectiveness, under the less situation of this suitable transmission transaction though traditional dma controller and data transfer control method have reduced the work of processor in data transmission procedure to a certain extent.A plurality of transmission transactions are often being arranged, and in the indefinite system of the number of transmission transaction, are needing that processor is disposable all to be arranged all affairs properly, wait until then these affairs finish after responding DMA request again, could improve system effectiveness to greatest extent.Therefore, traditional limited register in dma controller write the mode of transmission transaction information with regard to no longer suitable such system requirements.
Summary of the invention
The object of the present invention is to provide the dma controller that can independently handle eventful affair transmission requirement in a kind of system that is applied to eventful affair transmission requirement, and a kind ofly use this dma controller to carry out the method for Data Transmission Controlling, to reduce the consumption of processor resource in the transmission course, reduce the frequency of processor responding DMA request, can guarantee simultaneously the bandwidth requirement of data transmission again, maximization improves the overall performance of System on Chip/SoC.
The dma controller that can independently handle eventful affair transmission requirement provided by the invention comprises:
The slave unit interface of a system bus is used for the initial address that receiving processor is written to the affairs transmission chained list of storer, also can be used for the order that receiving processor is initiated and end data is transmitted.
The host device interface of a system bus is used for reading or writing the transmission descriptor and transmit data to storer from storer.
The bridge device interface of a device bus is exported the data in the storer as the bridge device between system bus and device bus to each data communication module, perhaps the data that each data communication module is received are sent to storer.For data correctly transmission between two buses, the bridge device interface has special clock zone change-over circuit.
A plurality of control signal wires that link to each other with each device communication module cooperate the transmission data that each device communication module is controlled.
The said system bus is generally high-speed bus in the sheet, and the said equipment bus is generally low speed bus in the sheet, but the transmission speed of the transmission speed of removal system bus and device bus is unsuitable, even lower than the transmission speed of device bus.
Having one in the above-mentioned storer can be for the shared drive district of processor and dma controller common access, and it is a special address field.And the bus interface at storer has arbitration circuit, makes processor and dma controller simultaneously during reference-to storage, adjusts the priority of processor and dma controller.
Above-mentioned processor can be according to the transmission requests of data communication module, the form that the specific transmission set of descriptors that will comprise transmission information is made into chained list is written in the shared drive district of storer, also can read in the transmission descriptor simultaneously and know the situation that transmission is finished from the shared drive district.
Affairs transmission chained list is the data organization mode that forms with one or more data structure organization in the above-mentioned storer, the elementary cell of its chained list is the transmission descriptor, each transmission interconnects by pointer between descriptor, and its actual physical address can continuously also can be discontinuous.
The transmission descriptor is to form with one or more data structure organization in the above-mentioned storer, be used to describe the set of all information of a transmission transaction, wherein the information that must comprise has: the length of the initial address of transmission data in storer, transmission data, the direction of transmission data, the optional information that comprises has: carry out transmission this time data communication module, transmit corresponding remote equipment address, other and the protocol-dependent information of particular data transmission with this.
The length of transmission descriptor can be fixed or floated in the above-mentioned storer, if length is floated, needs an end mark and notifies dma controller to finish this time to transmit reading in of descriptor.The actual physical address of transmission descriptor can be continuous or discontinuous, if discontinuous, need pointer between each physics byte and connect.
The transmission descriptor can read in and resolve the information that wherein comprises by dma controller in the above-mentioned storer, also can after finishing or end, transmission write back by dma controller, comprise the situation that transmission is this time finished or ended in the transmission descriptor that writes back, can in needs, understand by processor.
Above-mentioned dma controller has a register that can write affairs chain heading location, can directly not obtain the address of one or many transmission data storer from processor, but only obtain the initial address of affairs transmission chained list storer from processor, according to this address, from the shared drive district of storer, read in each transmission descriptor successively according to the order of connection of data transmission chained list.
Above-mentioned dma controller has the structural unit that an energy is resolved the transmission descriptor, can resolve according to the type of transmission descriptor, therefrom extract data transmission length, the data first address, information such as data transfer direction can be initiated data transmission according to the state of current corresponding data communication module in good time, arranging data is unremitting transmission between system bus and device bus, and can follow the tracks of data quantity transmitted.
Above-mentioned dma controller can be used as the data bridge of system bus and device bus, all will pass through dma controller when data are transmitted between two buses, and all like this data transmission can be initiated, follow the tracks of and be controlled by dma controller.
A kind of data transmission method that can independently handle the dma controller of eventful affair transmission requirement, be applied to be undertaken the information transmission of affairs transmission requests by the transmission descriptor in the storer, dynamically arrange in a plurality of affairs transmission initiations and the System on Chip/SoC of concluding time by dma controller, comprise processor, storer, dma controller/bridge, system bus, device bus and data communication module, it is characterized in that, comprise the steps:
At first processor is according to the transmission needs of data communication module, finds the corresponding driving program from Driver Library, will transmit set of descriptors and be made into the transmission chained list and be written in the shared drive district of storer; Processor is written to the initial address of transmission chained list in the corresponding registers of dma controller;
Dma controller finds first transmission descriptor according to the initial address of transmission chained list in the shared drive district of storer then; Dma controller is initiated the transmission of data between storer and data communication module according to the information of this transmission descriptor;
If transmission is not finished, dma controller continues to upgrade the address of reference-to storage, and the data of transmission are counted;
If transmission is finished, and mistake occurs in transmission course, then guarantee transmission correctness by the information requirements that parse in the transmission descriptor, the dma controller arrangement retransmits;
If transmission is finished, and mistake does not appear in transmission course, even perhaps occur wrong but transmitting the information that parses in the descriptor does not require the assurance transmission correctness, dma controller is not arranged to retransmit, and this transmission information is write back in the transmission descriptor in the shared drive district;
If show the transmission transaction that also has next time by the information that parses in the transmission descriptor, dma controller finds next transmission descriptor according to indicator linking, therefrom parses transmission information, arranges the bus data transmission;
If show the transmission transaction that does not have next time by the information that parses in the transmission descriptor, the end of transmission (EOT) this time of dma controller is reported to processor.
In the data transmission method of the above-mentioned dma controller that can independently handle eventful affair transmission requirement, dma controller can be finished or uncompleted situation according to once transmitting, and arranges the transmission of next affairs or the re-transmission of affairs this time, does not need the processor intervention.
Original advantage of the present invention is: in the system that eventful affair transmission requirement is arranged, processor can disposablely be written to the form of all affairs transmission requirements with the transmission descriptor in the shared drive district of storer, come the transmission of autonomous each affairs of arrangement then by dma controller, comprise the retransmission mechanism of makeing mistakes.After all transmission transactions were all finished, dma controller was just reported to processor.Can reduce the consumption of processor resource in the transmission course like this, reduce the frequency of processor responding DMA request, can guarantee the bandwidth requirement of data transmission simultaneously again, maximization improves the overall performance of System on Chip/SoC.
Description of drawings
Fig. 1 is traditional system architecture synoptic diagram that has dma controller;
Fig. 2 is traditional dma controller workflow diagram;
Fig. 3 is the system architecture synoptic diagram that has dma controller of the present invention;
Fig. 4 is a dma controller control data transmission mode process flow diagram of the present invention;
Fig. 5 is a transmission descriptor example in the shared drive district among Fig. 3;
Fig. 6 is a dma controller example among Fig. 3.
Number in the figure is as follows:
101 is the sheet inner treater, and 102 is on-chip memory, and 103 is dma controller, and 104 is system bus, and 105 is device bus, and 106 is data communication module (as USB), and 107 is bus bridge.
201 send transmission requests for data communication module, 202 send the bus application for dma controller, 203 are the register in the processor configuration dma controller, 204 are the transmission of dma controller control bus, 205 judge whether transmission is finished for dma controller, 206 for processor judges whether to retransmit, and whether 207 carry out next step transmission for decision processor, and 208 is end of transmission (EOT).
301 is the sheet inner treater, and 302 are on-chip memory (wherein comprising a shared drive district), and 303 is dma controller/bus bridge module, and 304 is system bus, and 305 is device bus, and 306 is data communication module (as USB).
401 send transmission requests for data communication module, 402 send the bus application for dma controller, 403 write the transmission transaction chained list for processor in the shared drive district, 404 read in the transmission descriptor for dma controller from the shared drive district, 405 are the transmission of dma controller control bus, and 406 judge to transmit whether finish for dma controller, and 407 judge whether to retransmit for dma controller, 408 for dma controller judges whether to carry out next step transmission, and 409 is end of transmission (EOT).
Embodiment
Following with reference to accompanying drawing detailed description the specific embodiment of the present invention.
Fig. 3 is the system construction drawing that other module of dma controller of the present invention and system is connected, and dma controller (303) is as follows with the annexation of each module of system:
With system bus (304): dma controller (303) both can be used as the main equipment of system bus, also can be used as the slave unit work of system bus.
With the sheet inner treater (301) on the system bus: processor can have access to the setting and the status register of dma controller inside by the system bus addressing, processor can write chain heading location to dma controller, processor can write beginning or end the transmission zone bit to dma controller, but processor does not directly write address and the data length of each transmission data in storer to dma controller, and with the relevant information of transmission transaction.
With the on-chip memory (302) on the system bus: memory inside has an address field to be called the shared drive district specially, can be by the visit of processor and dma controller.Storer can be a double port memory, also can be the single port storer, if storer is the single port storer, storer and system bus junction need an arbitration circuit and come the request of access of processor and dma controller is arbitrated so.Dma controller can pass through system bus, reads or write transmission descriptor and transmission data from the shared drive district of storer.
And device bus (305): dma controller is as the bridge device between device bus and the system bus, the synchronizing function in the time of can finishing data and change between two clock zones.
With the data communication module (306) on the device bus: dma controller has special control line to be connected with control signal between these data communication modules, the transmission data connect by device bus, dma controller can send the data IO Command to specific data communication module (as USB) according to the information of transmission descriptor, and provide corresponding transmission information, as destination address, target device etc.
In the present invention, dma controller comprises special resolution unit, can resolve the transmission descriptor in the shared drive district, and therefrom extract the transmission information relevant with data transfer affairs, and as the transmission data address, the transmission data length, transmission direction, transport-type etc.And dma controller can find the address of next transmission descriptor from a transmission descriptor, judge perhaps whether this transmission descriptor is last.
In the present invention, dma controller comprises one group of register, only is used for receiving the affairs chain heading address that writes from processor.
In the present invention, dma controller comprises transmission control unit, can finish or because of after unusually ending in transmission once, according to the information independence decision re-transmission of transmission descriptor or transmit next time.
In the present invention, dma controller can be reported to processor by the mode of status register or interruption when transmission is finished.
In the present invention, dma controller can independently be selected continuous transmission mode (burst) or single transmission mode (single) according to the needs of transmission.
Fig. 4 is the data transfer mode process flow diagram of dma controller control of the present invention, and the step of DMA work is as follows:
Step 401: the data communication module on the device bus is dealt into dma controller with transmission requests, and this finishes by control line special between dma controller and the data communication module.
Step 402:DMA controller sends transmission requests to processor, and this mode that can but be not limited to by interrupting to the processor application realizes.
Step 403: the type of the transmission application that processor sends according to dma controller, find the corresponding driving program in the slave driver storehouse, disposable current transmission requests is decomposed into a plurality of transmission descriptors, in the shared drive district with the mode write store of transmission transaction chained list, then the first address of transmission transaction chained list is write in the register of dma controller.
Step 404:DMA controller reads in a transmission descriptor from the shared drive district, therefrom parse corresponding transmission information.
The transmission of step 405:DMA controller control data between storer and data communication module, data flow between system bus and device bus through the bridge of dma controller conduct.
The data length that step 406:DMA controller transmits as required and the data length of actual transmissions, and unusual situation takes place in the transmission course, judge whether current transmission is finished, if do not finish, then continue transmission, if finish or, enter next step judgement because unusual and end.
Step 407:DMA controller need to judge whether to retransmit after a transmission transaction is finished.If mistake occurs in transmission course, and guarantee transmission correctness by the information requirements that parse in the transmission descriptor, the dma controller arrangement retransmits, and gets back to step 405; If mistake in transmission course, do not occur, even still transmitting the information that parses in the descriptor does not require the assurance transmission correctness mistake perhaps to occur, dma controller is not arranged to retransmit, and this transmission information is write back in the transmission descriptor in the shared drive district, enters next step judgement;
Step 408:DMA controller judges whether to transmit next time.If show the transmission transaction that also has next time by the information that parses in the transmission descriptor, dma controller is got back to step 404 according to indicator linking, arranges the bus data transmission; If show the transmission transaction that does not have next time by the information that parses in the transmission descriptor, the end of transmission (EOT) this time of dma controller.
Step 409:DMA controller end of transmission (EOT) is reported to processor.
Fig. 5 and Fig. 6 are for the invention provides an example.
Fig. 5 is the example of transmission descriptor in the described shared drive of Fig. 3 district.Look for a transmission descriptor to constitute, comprised different fields, comprising by being stored in 4 data in the continuous address:
Next Pointer: the pointer that points to next transmission descriptor address.
V (Value): the validity of this transmission descriptor is described, does not put 1 by processor before dma controller is carried out, expression effectively; Execute the back at dma controller and put 0 by dma controller, it is invalid to represent.
H (Head): illustrate whether this transmission descriptor is the gauge outfit of transmission transaction chained list.If be 1, expression is a gauge outfit, if 0, then expression is not a gauge outfit.In annular chain meter, be 1 if occur this field for twice, can think that then all transmission all finish.
Data Length: the data length of current transmission.
Data PageL: the page number of data in storer of current transmission.This is used in the storage system of multipage facial canal reason.
I/O: the direction of current transmission.If be 1, represent that then to storer be input, data are input in the storer by data communication module; If be 0, represent that then to storer be output, data are input in the data communication module by storer.
Data Offset: the page or leaf bias internal of the data of current transmission in storer.This is used in the storage system of multipage facial canal reason.
T (Terminate): chain end of list (EOL) sign.If be 1, then expression transmission chained list is to showing tail; Otherwise then expression transmission chained list is not intact.This is used in the end of judging affairs transmission chained list in the other than ring type chained list.
Fig. 6 is the described dma controller inner structure of a Fig. 3 example.Inner structure comprises:
Data port of one group system bus master (ram_data_i, ram_data_o) and address mouth (ram_addr_o) are used for reading and writing data from storer and transmitting descriptor.
The data-interface of one group system bus slave (register_i, register_o) is used for the transmission transaction chain heading location that receiving processor writes.
Data port of one group of device bus bridge device (txdata, rxdata) and control line (control lines) are used for the data communication module on the device bus is carried out the output or the input of data and control signal.
Buffer unit on a pair of system bus and the device bus (Data Buffer).
Bridge construction on data passage comprises clock zone change-over circuit (Data Bridge).
The storage unit (DP Buffer) of a transmission descriptor is used for the interim transmission descriptor that reads in of preserving from the shared drive district, can therefrom parse transmission transaction information; After transmission is finished, also can upgrade wherein corresponding information in addition, and write back in the shared drive district.
The resolution unit (DP Decode) of a transmission descriptor is used for parsing useful information, the control line of control data communication module and dma controller internal logic from the transmission descriptor.
A register cell (DP Address Register) is used for the transmission transaction chained list first address that receiving processor writes.
A memory read/write address control unit comprises page control module (Page Control) and offset control unit (Offset Control), is used for producing in real time when read-write transmission descriptor and read-write transmission data the corresponding memory physical address.The affairs chain heading address that processor writes also is kept at here.
A transmission control unit (Transfer Control) is used for actual conditions according to the requirement and the transmission of transmission transaction, independently arranges the control of retransmission mechanism and transmission process.
It should be noted last that: above embodiment is the unrestricted technical scheme of the present invention in order to explanation only, although the present invention is had been described in detail with reference to the foregoing description, those of ordinary skill in the art is to be understood that: still can make amendment or be equal to replacement the present invention, and not breaking away from any modification or partial replacement of the spirit and scope of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (10)
1, a kind of dma controller that can independently handle eventful affair transmission requirement is characterized in that, comprising:
The slave unit interface of a system bus is used for the initial address that receiving processor is written to the affairs transmission chained list of storer, perhaps is used for the order that receiving processor is initiated and end data is transmitted;
The host device interface of a system bus is used for reading or writing the transmission descriptor and transmit data to storer from storer;
The bridge device interface of a device bus, as the bridge device between system bus and device bus, to each data communication module output, perhaps the data that each data communication module is received are sent to storer the data in the storer;
A plurality of control signal wires that link to each other with each device communication module cooperate the transmission data that each device communication module is controlled.
2, the dma controller that can independently handle eventful affair transmission requirement according to claim 1 is characterized in that, has a register that can write affairs chain heading address.Dma controller does not directly obtain the address of one or many transmission data storer from processor, but only obtain the initial address of affairs transmission chained list storer from processor, according to this address, from storer, read in each transmission descriptor successively according to the order of connection of data transmission chained list.
3, the dma controller that can independently handle eventful affair transmission requirement according to claim 1 and 2 is characterized in that, has a transmission descriptor resolution unit.Dma controller is resolved the type of transmission descriptor, therefrom extracts information such as data transmission length, data first address, data transfer direction, according to the state of current corresponding data communication module, initiates data transmission or re-transmission.
4, the dma controller that can independently handle eventful affair transmission requirement according to claim 1 and 2, it is characterized in that, affairs transmission chained list is the data organization mode that forms with one or more data structure organization in the described storer, the elementary cell of its chained list is the transmission descriptor, interconnect by pointer between each transmission descriptor, its actual physical address is continuous or discontinuous.
5, according to claim 2 or the 3 or 4 described dma controllers that can independently handle eventful affair transmission requirement, it is characterized in that, the transmission descriptor is the set that forms all information that are used to describe a transmission transaction with one or more data structure organization in the described storer, wherein the information that must comprise has: the initial address of transmission data in storer, the length of transmission data, the direction of transmission data, the optional information that comprises has: carry out the data communication module of transmission this time, transmit corresponding remote equipment address with this, other and the protocol-dependent information of particular data transmission.
6, according to claim 2 or the 3 or 4 described dma controllers that can independently handle eventful affair transmission requirement, it is characterized in that, the length of transmission descriptor is for fixing or unsteady in the described storer, if length is floated, then there is an end mark to notify dma controller to finish and this time transmits reading in of descriptor.The actual physical address of transmission descriptor is continuous or discontinuous, if discontinuous, then has pointer to connect between each physics byte.
7, according to claim 2 or the 3 or 4 described dma controllers that can independently handle eventful affair transmission requirement, it is characterized in that, the transmission descriptor is read in and is resolved the information that wherein comprises in the described storer by dma controller, perhaps after finishing or end, transmission writes back by dma controller, comprise the situation that transmission is this time finished or ended in the transmission descriptor that writes back, in needs, understand by processor.
8, a kind of data transmission method that can independently handle the dma controller of eventful affair transmission requirement, be used for carrying out the transmission of affairs transmission requests information by the transmission descriptor of storer, dynamically arrange in a plurality of affairs transmission initiations and the System on Chip/SoC of concluding time by dma controller, comprise processor, storer, dma controller/bridge, system bus, device bus and data communication module, it is characterized in that, comprise the steps:
(1) processor is according to the transmission needs of data communication module, finds the corresponding driving program from Driver Library, will transmit set of descriptors and be made into the transmission chained list and be written in the shared drive district of storer;
(2) processor is written to the initial address of transmission chained list in the corresponding registers of dma controller;
(3) dma controller finds each transmission descriptor according to the initial address of transmission chained list in the shared drive district of storer;
(4) dma controller is initiated the transmission of data between storer and data communication module according to the information of each transmission descriptor;
(5) dma controller transmission once finish or transmit ended after, the information of upgrading the transmission descriptor also writes back in the shared drive district, independently arranges next step operation then.
9, the data transmission method that can independently handle the dma controller of eventful affair transmission requirement according to claim 8, it is characterized in that, dma controller can be finished or uncompleted situation according to once transmitting, arrange the transmission of next affairs or the re-transmission of affairs this time, do not need the processor intervention.
10, the data transmission method that can independently handle the dma controller of eventful affair transmission requirement according to claim 8, it is characterized in that, described shared drive district is a special address field in storer, and processor and dma controller can carry out the addressing visit.
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