CN1547249A

CN1547249A - Programmable logic device structure

Info

Publication number: CN1547249A
Application number: CNA2003101094525A
Authority: CN
Inventors: 童家榕; 郭斌林; 马晓骏
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2003-12-16
Filing date: 2003-12-16
Publication date: 2004-11-17
Anticipated expiration: 2023-12-16
Also published as: CN1280892C

Abstract

The invention is a kind of programmable logic device (FDP) which is applicable to the data channel, which is made up of programmable logic unit arrays. The arrays are organized into layer structure through the layer programmable wire. M n LCs build-up the programmable macro unit, in order to realize the multi-bit data operation; uses the MC as base unit to carry on array extension, acquires the FPGA series with different standard, and the programmable IP kernel which accords variable capacitance demands can be acquired. The FDP structure can be used as FPGA chip; it also can be used as the programmable system-on-chip or programmable IP kernel.

Description

Programmable logic device structure

Technical field

The invention belongs to the design of electronic circuits technical field, be specifically related to a kind of programmable logic device structure, this structure is suitable for data path and uses.

Background technology

FPGA (Field Programmable Gate Array, field programmable gate array) is a kind of programmable logic device that is widely used, and can write in device by the user " programming data ", realizes the logical circuit of difference in functionality.The field-programmable characteristic of FPGA can reduce the development cost of electronic system, shortens Time To Market, reduces the system maintenance upgrade cost.FPGA both can be used as the design verification of electronic system exploitation, also can be used for the finished product production of electronic product, had widely to use in various military, civilian electronic products.SOC (system on a chip) (SOC) is that an electronic system is integrated in technology on the chip piece.The same with common electronic system, in SOC (system on a chip), also can widely apply programmable module with variable logic function.Therefore to design programmable I P nuclear, be used for system design for the SOC designer.There is very big similitude the core of the core of FPGA and programmable I P nuclear, and their structure (comprising programmable logic cells structure and programmable interconnect structure) can adopt same design, in the present invention they is referred to as FPGA.

Such as fields such as sound/image processing, digital communication, controls in real time, need computings such as a large amount of additions, multiplication, FFT, dct transform.At present, these computings often adopt DSP, FPGA or ASIC (application-specific integrated circuit (ASIC)) chip to realize.In the occasion that real-time is had relatively high expectations, often adopt FPGA or ASIC just can reach required computational speed.Because it is more approaching that FPGA compares on speed with ASIC, and on development rate, development cost and application flexibility, want much superior.Therefore, FPGA has the good ratio of performance to price in the application of data path, just adopted widely.

The problem that the structural design of FPGA contained has: the use of the combination of the tissue of array of programmable logic cells, programmable links resource and array of programmable logic cells, programmable I/O unit, design are with the solution of spline structure different scales FPGA etc.The FPGA structural design has important effect for everyways such as the function of FPGA product, performance, use, test, maintenances.Application meeting in different field proposes different optimization requirements to the structure of FPGA, is necessary that therefore the main application fields (using as the data path) at FPGA proposes the special FPGA structural design of optimizing.

Summary of the invention

The objective of the invention is to propose a kind of programmable logic device structure design that is suitable for the optimization of data path application.

The present invention proposes is suitable for programmable logic device (FPGA for DataPath the is abbreviated as FDP) structure that data path is used, and is made up of programmable logic cells (LC) array, and the programmable links resource organizations by hierarchy type becomes the hierarchy type structure.This structure is optimized at the data path application, has used to be suitable for programmable logic cells structure and the programmable links structure that data path is used; M * n (16 〉=m, n 〉=2) LC formed programmable macro unit (MC), help realizing the bits of data computing; Can be that elementary cell is carried out array extension by MC, obtain the FPGA series of different size, also can be met the programmable I P nuclear of Different Logic capacity requirement.The FDP structure both can be used as fpga chip, also can be used as programmable system on chip or programmable I P nuclear.

(1) about the hierarchy type chip structure

FDP uses the data path and has carried out special optimization, wherein adopted and be suitable for programmable logic cells (the Programmable Logic Cell that data path is used, LC) and the programmable links structure, also can take into account the instructions for use that generic logic is used simultaneously well.The programmable links structure is organized with hierarchy type in the chip, is divided into three layers, corresponds respectively to programmable logic cells is connected with chip level in LC rank, MC rank; With such hierarchy type interconnection structure the programmable resource of chip is organized as the hierarchy type structure: several LC form m * n (16 〉=m, n 〉=2) array and corresponding short-term, long line able to programme, special-purpose carry line, special clock line constitute a macrocell (Macro Cell, MC), entire chip is made up of according to array format MC.

The institutional framework of FDP hierarchy type is seen the example among Fig. 1, Fig. 2.As shown in fig. 1, chip center partly is the array of a MC.Is programmable I/O unit around the MC array, as the user of FDP input and output pin when the design circuit.

Be a macrocell of being made up of 4 * 4 LC among Fig. 2, contiguous LC connects by short-term, and divisible long line is finished the connection in MC inside.The contact that is formed by resources such as divisible long line, special-purpose carry chain, clock lines between the LC among the MC is tightr, and they are made as a whole circuit and the layout design of carrying out.

With MC is unit, by control to the interconnection resources program switch on the MC edge, can determine divisible long line length, can control the carry mode (set, reset or carry are transmitted) of special-purpose carry chain between MC.A MC can realize the full adder of four nibbles efficiently, or 4 multipliers of a high speed.Can and by the divisible long line of several MC, special-purpose carry chain etc. are connected together, come MC to reach the more data operation of long number with several.In addition, the special clock network is that unit carries out clock buffering and distributes by MC, by the clock line among the control MC, can forbid the transmission of clock in this MC when preface function when not required, reaches the purpose that reduces dynamic power consumption.

Programmable switch group on the MC edge combines the control of divisible long line, special-purpose carry chain and special clock network, and its structure as shown in Figure 3.Vertically with on the horizontal direction one group of such programmable switch group---vertical control unit and horizontal control unit are being arranged respectively.

(2) expansion of chip-scale

Programmable logic chip or programmable I P nuclear will be different according to different user the circuit scale requirement, the tandem product of different scales is provided, allow the user under the prerequisite that assurance function is used, reduce cost and chip area consumption.Therefore FDP can just can form the programmable logic chip or the programmable I P nuclear of different scales size by number and the corresponding long line interconnection resource that changes MC by the unit of MC as the hierarchy type array.With the FDP structure among Fig. 1 is example, and 4 * 4MC array is increased to 5 * 5 array, and increases elongated line each row in length and breadth, just can make original chip enlarge about 50%.

When the scale of MC array changes significantly, because long line length changes, need to adjust the driving of MC, also need to change the interconnection resources changes in demand that causes, change the channel width (the bar number of line in each group line) of long line, divisible long line according to scale to long line.But when the variation of chip in certain scope, still can be channel width and long line be driven and do not do change, the scale that array size adjustment programmable logic device or the programmable I P by simple change MC and long line examines.

Description of drawings

Fig. 1 .FDP overall structure

Fig. 2. macro cell structure

Fig. 3. vertical/horizontal control unit structure

Number in the figure: 1 is long line, and 2 is divisible long line, and 3 is short-term, 4 is the programmable macro unit, and 5 is special-purpose carry line, and 6 is programmable I/O unit, 7 is vertical carry line, and 8 is horizontal carry line, and 9 is vertical control unit, 10 is horizontal control unit, and 11 is programmable logic cells, and 12 are the clock input, 13 are the output of clock buffering, and 14 are the carry input, and 15 are carry output, 16 is divisible long wiretap group, and 17 are carry value control, and 18 are the control of carry on/off.

Embodiment

In fact in the structure shown in Fig. 1, Fig. 2, Fig. 3 is exactly specific embodiment of the present invention.As shown in fig. 1, comprise 4 * 4 mc units in the device of this example, have 4 groups of long lines of horizontal direction and 4 groups of long lines of vertical direction, 4 every group, have 32 long lines.Around the MC array 4 * 4 is programmable I/O unit, realizes the input and output pin of user when design circuit of FDP.Comprise 16 the I/O mouths that can use for the user, i.e. each row in the MC array/I/O mouths of row correspondence in the I/O unit on each limit.

The structure of MC inside as shown in Figure 2.4 * 4 lc unit array is connected with divisible long line (a drawn divisible long line is represented a group that comprises 4 divisible long lines among the figure) by short-term (a drawn short-term is represented a group that comprises 5 short-terms among the figure).16 divisible long lines at MC edge are controlled by programmable switch group (horizontal control unit among Fig. 2 and vertical control unit, structure as shown in Figure 3) with 4 special-purpose carry lines, link to each other with adjacent MC.

Structure in this example is exactly a programming device that comprises 16 * 16LC unit, 64 programmable I/O mouths.

Claims

1, a kind of programmable logic device structure of hierarchy type tissue can be used for it is characterized in that adopting the programmable logic cells IC structure and the programmable links structure that are suitable for the data path application in the design of FPGA and programmable I P nuclear; M * n (16 〉=m, n 〉=2) LC formed programmable macro unit (MC), is that elementary cell is carried out array extension with MC, obtains the FPGA series of different size, or satisfies the programmable I P nuclear of Different Logic capacity requirement.

2, the programmable logic device structure of hierarchy type tissue according to claim 1 is characterized in that: the programmable resource of chip is organized as 3 levels: programmable logic cells LC is the programmable resource of minimum level; Every m * n (16 〉=m, n 〉=2) LC and corresponding interconnection resources constitute a macrocell (MC); Entire chip is made up of according to array format MC, and programmable I/O mouth is arranged around the array.

3, the programmable logic device structure of hierarchy type tissue according to claim 2, it is characterized in that: m * n (16 〉=m, n 〉=2) LC array and the short-term between them, long line able to programme, special-purpose carry line, special clock line are made as a whole circuit and the layout design of carrying out; The junction of MC and MC has the programmable switch group that long line able to programme, special-purpose carry line are connected and controls.