CN1378397A - Realising device for baseband forming filter in stream line mode - Google Patents

Abstract

On the basis of the present design of the base band formed wave filter, the device of the invention puts forward an idea and a device of the base band formed wave filter based on the pipeline system. Its characteristic is that partitioning the processing link of the wave filter in the pipeline system style, and applying the pipeline system technology to key processing link (especially on the multiplier), and raising the system working clock, and increasing the system data flow. Using the base band formed wave filter based on the pipeline system, it can support longer input word length and filter word length, and is suited to the base band formed filter of base station down signals.

Description

Adopt the implement device of the base band shaping filter of pipeline system

(1) technical field:

Apparatus of the present invention belong to digital communication technology field, relate in particular to the implement device of the base band shaping filter that adopts pipeline system.

(2) background technology:

In digital communication system, the actual transmission channel bandwidth is always limited, for wireless communication system, radio spectrum resources is very valuable, so transmit in the inherent wireless channel of the frequency band that digital baseband signal need be modulated to qualification, so, the quality of isolating between each frequency band will directly have influence on systematic function.In general, in wireless communication system, attenuation outside a channel requires to arrive 40dB-80dB usually, to reduce the interference to adjacent channel.

If directly adopt the transmission code shape of rectangular pulse as baseband signal, signal spectrum will be expanded on whole frequency domain, behind the band-limited channel of reality, signal spectrum is by brachymemma, on time domain, the pulse of each symbol will extend in the time interval of adjacent-symbol, form intersymbol interference (ISI), thereby the probability that causes receiver to make a mistake when detecting a symbol increases.

Pulse shaping technique is by selecting the transmission code shape of special single pulse waveforms as baseband signal, and the available ISI that reduces is limited in signal spectrum in the limited bandwidth simultaneously.When signal transmission code shape is satisfied Nyquist first criterion (the undistorted criterion of sample value) (" digital communication (third edition) " (DigitalCommunications Third Edition, John G.Proakis)) time, just can guarantee disturbing between nonexistent code on the sampled point.The pulse shaping filter of the type that the most generally adopts in mobile communication system is the raised cosine roll off filter.

For the pulse shaping filter of reality, the frequency domain representation of its transfer function is Heff (f), often by all adopting transfer function to be at the Receiver And Transmitter end

Filter realize, the advantage of system matches filter response is provided, limited transmission bandwidth simultaneously, reduced ISI.So the transmitting terminal for adopting the raised cosine filter system uses root raised cosine filter (root-raise-cosinefilter) usually, its frequency-domain expression is the square root of raised cosine filter.Because developing rapidly of digital processing technology, make this process of baseband filtering to realize in number, adopt filter way " variable Rate Digital Signal Processing " (the Multirate Digital SignalProcessing of interpositioning, Englewood Cliffs, NJ, Prentice-Hall, Inc., 1983 R.E.Cronchiere L.R.Rabiner) have saved a large amount of hardware logic resources in realization, can realize the filter on longer exponent number (nearly 100 rank).Characteristics of digital processing technology are responsive especially to word length, and digital filter is actually by a series of multiplication and add operation to be formed.The increase of filter input word length, the raising of filter factor precision all can make the logical resource of filter rise rapidly.In present existing realization technology, mainly contain two kinds of structures, first kind is direct multiplier architecture, as special chip HSP43168 (Intersil Corporation.HSP43168 Data Sheet, Feb.1999), use several core multipliers to carry out multiplying in the chip.Because the execution needed time of multiplying is long, limited the scope of application of chip, for example, need 30ns if carry out the time of multiplication, the reliably working frequency of chip operation just can not surpass 33MHz so.Another is to adopt look-up table configuration, and (ELECTRONICSLETTERS 2 at " electronics wall bulletin " ^NdSep 1999 vol.35 No18 1504-1505) there are concrete description, this way to be suitable for importing the relatively shorter situation of data bit width, are particularly suitable for single-bit filtering.But along with the long increase of Input Data word, the scale of look-up table can increase thereupon, the logical block linear growth, and also the speed of tabling look-up also can slow down

(3) summary of the invention:

It is to realize digital baseband forming filter at a high speed that the present invention directly designs order ground, especially at Input Data word length and the long situation of filter coefficient word length.

The notion of The pipeline design is that the logical operation of carrying out in a clock cycle is divided into the less operation of several steps, and finishes in the clock of a plurality of higher speeds.(a) figure is the way that does not adopt streamline in accompanying drawing 1, module 2 is core processing units of this circuit, and signal 7 is input data, and 1 pair of signal 7 of module latchs generation signal 8 and sends into processing unit 2, module 2 is sent result 9 into latch module 3, final output signal 10.Signal 11 is clock signals of latch.If the time of implementation of module 2 is t, the maximum clock frequency of this circuit (highest frequency of signal 11 just) is 1/t so.In accompanying drawing 1 (b) figure, being the way that adopts streamline is divided into module 4 and module 5 with the operation of module 2, and the signal 12 of module 4 outputs produces signals 13 by latch 6 and sends into module 5.The processing time of module 4 and module 5 all is t/2 in the ideal case, and the maximum clock frequency of this circuit is brought up to the twice of figure (a) so.Therefore adopt pipelining to improve the data traffic of system, i.e. handled data volume in the unit interval.The abundant utilization of streamline thought among the present invention, it is characterized in that streamline division to the handling process of whole filter, adopt pipelining to be divided into the shift LD of input data the filter process process, the preliminary treatment of input data, the cyclic shift of coefficient, multiplication calculates (or the processing of tabling look-up), accumulation calculating, the back level is handled plurality of processes, all processing units all use the master clock of streamline, if a certain link process object is a low speed data, then use the enable signal of low-frequency signal as clock.

Beneficial effect of the present invention: the present invention can support long input word length and filter factor word length, has improved the work clock of system, has increased the data traffic of whole system.

(4) description of drawings:

Fig. 1 is the pipeline organization schematic diagram;

Fig. 2 is that WCDMA BTS base band sends schematic diagram;

Fig. 3 is for adopting 64 rank base band shaping filters of pipeline system;

Fig. 4 distributed for the streamline time.

(5) figure embodiment:

Below in conjunction with the description of drawings embodiment:

In the present invention, the utilization of pipelining in the realization of baseband filter can be set forth from the following aspects.1, the division of ripple device processing procedure.The handling process of filter can be divided into the shift LD of importing data on the whole, the preliminary treatment of input data (for example, when the coefficient of filter has symmetry, to import the addition of data symmetry earlier), the cyclic shift of coefficient (at the variable coefficient multiphase filter), multiplication calculates (for the Design of Filter of look-up table configuration, multiplication calculates this process process of being tabled look-up and replaces), accumulation calculating, the back level is handled (if adopt resource multiplex, the data of accumulator output being handled accordingly).When adopting the pipelining design, whole filter is only used the beat of all processing procedures of clock control, sets up register to carry out data latching between different processes.After dividing like this, the data traffic of whole filter will depend on that step processing of minimum speed, and therefore, the processing speed that how to improve each procedure becomes the key of Design of Filter.2, the multiplication link is the bottleneck of whole filter processing speed in Design of Filter usually, and in multiplier architecture, when adopting two-stage or three class pipeline structure just can obtain reasonable result, performance can improve more than 80%.3, in adopting the Design of Filter of multiplier architecture, with the increase of filter order, the number that adds up that output adds up to multiplier also increases thereupon, adopts streamline to carry out layering and adds up and just seem and very must

Want.In the look-up table structural design, same when checking result is added up, as adopting flowing water

The line mode is handled, and also can improve the data traffic of this processing links.

From above-mentioned some as can be seen, by the streamline of each processing links of whole filter being divided and to the utilization of the pipelining of crucial processing links, improved the data traffic of whole system, the system that makes can handle the input data of higher rate.When twice is arrived in the disposal ability raising one of system, make system multiplexing become possibility simultaneously.For example, when the signal of QPSK modulation is handled, to design usually two filters parallel to I, the Q circuit-switched data is carried out filtering, after adopting pipelining, system processing power increases, and pipeline clock can be doubled, I, Q data serial input filter, with I, the sampling of Q circuit-switched data separates, and has only taken a filter resource on the hardware at output.

Embodiment 1, the realization of WCDMA BTS transmitter 64 rank base band shaping filters.

The realization principle that base band sends among the WCDMA BTS as shown in Figure 2.Among the figure, 20-24 module and 25-29 module are respectively that the base band of different physical channels sends processing unit module and the annexation between them thereof, 30 modules are base-band digital synthesis modules of a physical channel, and promptly different physical channels carries out addition through the data behind the spread spectrum in this module handles.Data after different physical channels are synthetic are given base band shaping filtration module 31 and are handled.According to the definition of 3GPP standard (" 3GPP technical specification 25.213 v3.2.0 ") and the requirement of base station, for down channel, because the acting in conjunction of following 6 aspects:

1, the system spread-spectrum modulation system adopts multiple spread spectrum;

2, the relative channel gain for DPDCH and DPCCH in the channel has definition;

3, each physical channel has relative gain;

4, a plurality of physical channels will carry out combining channel in number;

5, support the downlink power control of certain limit;

The down physical channel number of 6, one BTS supports may reach tens, tens.

All of these factors taken together makes Input Data word length increase (arriving more than the 10bit), this example takes directly to use the implementation method of multiplier, for the base station, the consideration of chip volume and power consumption aspect requires low than travelling carriage, can use higher work clock, so that hardware resource is carried out repeatedly multiplexing, thereby save hardware resource.

Time domain expression formula according to the root raised cosine filter of regulation among the 3GPP " 3G TS 25.104 v3.2.0 " $R{C}_0\left(t\right)=\frac{\sin \left(\mathrm{\π}\frac{t}{T_C}(1-\mathrm{\α})\right)+4\mathrm{\α}\frac{t}{T_C}\cos \left(\mathrm{\π}\frac{t}{T_C}(1+\mathrm{\α})\right)}{\mathrm{\π}\frac{t}{T_C}(1-{\left(4\mathrm{\α}\frac{t}{T_C}\right)}^2)},$ Wherein, $T_c=\frac{1}{3.84\mathrm{MHZ}}\≈0.2604\mathrm{\μs}$ Be code-element period.Calculate 64 coefficients.The data rate of input filter is a spreading rate, frequency is 3.84MHz, filter employing interpolation factor is 4 interpolation filter, data of every input produce the output valve of 4 phase points, the speed of filter output is 4 times of clocks (chipx4_clk) so, this 64 rank filter of principle according to interpolation filter can equivalence be the variable coefficient filter on one 16 rank, index variation speed is chipx4_clk, in design to the calculating section logical multiplexing twice, the multiplexing output that is to calculate 16 rank filters for the first time, calculate the value on preceding 8 rank earlier, calculate the value on 8 rank, back then; For the second time multiplexing is because system has adopted the modulation system of QPSK, need be to I and the filtering respectively of Q road, but the coefficient of both filters is just the same, so the time-division I and Q circuit-switched data are calculated with same logical block, because above-mentioned twice multiplexing system clock that requires reaches 4 times of chipx4_clk (being chipx16_clk=61.44MHz).

Provide the overall structure figure of filter in the accompanying drawing 3, can be divided into 6 layers from top to down.

Ground floor is the shift LD of input data, the I road part of only having drawn among the figure, Q road, abridged, module 101 to 115 is 15 shift registers, because the speed of input data is spreading rates, and system works speed is 16 times of spreading rates, so with the clock of chipx16_clk as shift register, and with signal 116 (chip_clk) as enable signal, the propelling speed of shift register data is chip clock (chip_clk) like this;

In the second layer, 201 to 208 is gating modules, as gating signal the signal 117 to 132 from ground floor is carried out gating with 4 times of chip clock (chipx4_clk) signal 209, successively half data of the first half of 117 to 132 and back are sent to next stage.The same with ground floor, the Q road part of not drawing among the figure.

The 3rd layer is with the gated clock of 8 times of chip clock (chipx8_clk) signal 309 as data strobe module 301 to 308, carry out I, Q is multiplexing, because I, the coefficient of Q path filter is identical, so after adopting the high power clock multiplexing, the multiplier and the used hardware resource of adder of whole filter calculating section can be reduced half.

The 4th layer is that coefficient is selected and the multiplying part, because I, the coefficient of Q path filter is identical, so I, the rate of change of the multiplexing back of Q coefficient is chipx8_clk, the method that coefficient produces is with the clock of chipx16_clk as counter module 409, with the enable signal of signal 410 (chipx8_clk) as counter, with the counter output signal 411 of 3 bits one in 8 coefficients of gating in turn, be input to an input of multiplier, the another one of multiplier is imported the I from the 3rd layer, the time-division output of Q.Calculate for multiplication,, adopted 4 level production lines in order to reach the target of multiplexing clock.

Layer 5 is the adder part, and the output valve of 8 multipliers is carried out addition with 3 stage pipeline structure.

Layer 6 is the filtering data output, comprises an accumulator, and it carries out addition with the first half of filter and the accumulation result of latter half, also has a sampler 601 in addition, it is I, the Q data separating, and in time with two paths of data 602 and 603 alignment.

Accompanying drawing 4 is time diagrams of streamline, and abscissa is a unit with the master clock cycle 1/chipx16_clk of system, has shown the corresponding needed pipeline series of each layer in accompanying drawing 3, has also reflected the processing time-delay of this level simultaneously.Ordinate is represented the speed of these cell processing data, and minimum is chip_clk, is up to chipx16_clk.For example the 3rd layer of expression when Q circuit-switched data gating is handled, needs a level production line to I, i.e. in a chipx16_clk cycle, the speed of deal with data is 8 times of chip_clk.Among the figure the 11st grade on streamline to the 15th grade corresponding to the layer 6 in the accompanying drawing 3.

Adopt above-mentioned base band shaping filter, can support long input word length and filter factor word length, be applicable to the base band shaping filtering of base station down signal based on pipeline system.

Claims (2)

1. adopt the implement device of the base band shaping filter of pipeline system, it is characterized in that: the filter process process adopts pipelining to be divided into the shift LD of input data, the preliminary treatment of input data, the cyclic shift of coefficient, multiplication calculates (or the processing of tabling look-up), accumulation calculating, the back level is handled plurality of processes, all processing units all use the master clock of streamline, if a certain link process object is a low speed data, then use the enable signal of low-frequency signal as clock.

2. the implement device of the base band shaping filter of employing pipeline system as claimed in claim 1, it is characterized in that: ground floor is the shift LD of input data, module 101 to 115 is 15 shift registers, because the speed of input data is spreading rates, and system works speed is 16 times of spreading rates, so with the clock of chipx16_clk as shift register, and with signal 116 (chip_clk) as enable signal, the propelling speed of shift register data is chip clock (chip_clk) like this;

In the second layer, 201 to 208 is gating modules, as gating signal the signal 117 to 132 from ground floor is carried out gating with 4 times of chip clock (chipx4_clk) signal 209, successively half data of the first half of 117 to 132 and back are sent to next stage;

The 3rd layer is with the gated clock of 8 times of chip clock (chipx8_clk) signal 309 as data strobe module 301 to 308, carry out I, Q is multiplexing, because I, the coefficient of Q path filter is identical, so after adopting the high power clock multiplexing, the multiplier and the used hardware resource of adder of whole filter calculating section can be reduced half;

The 4th layer is that coefficient is selected and the multiplying part, because I, the coefficient of Q path filter is identical, so I, the rate of change of the multiplexing back of Q coefficient is chipx8_clk, the method that coefficient produces is with the clock of chipx16_clk as counter module 409, with the enable signal of signal 410 (chipx8_clk) as counter, with the counter output signal 411 of 3 bits one in 8 coefficients of gating in turn, be input to an input of multiplier, the another one of multiplier is imported the I from the 3rd layer, the time-division output of Q.Calculate for multiplication,, adopted 4 level production lines in order to reach the target of multiplexing clock;

Layer 5 is the adder part, and the output valve of 8 multipliers is carried out addition with 3 stage pipeline structure;

Layer 6 is the filtering data output, comprises an accumulator, and it carries out addition with the first half of filter and the accumulation result of latter half, also has a sampler 601 in addition, it is I, the Q data separating, and in time with two paths of data 602 and 603 alignment.

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