CN1346557A - Management of time slot operations for wireless communication - Google Patents
Management of time slot operations for wireless communication Download PDFInfo
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- CN1346557A CN1346557A CN 99813631 CN99813631A CN1346557A CN 1346557 A CN1346557 A CN 1346557A CN 99813631 CN99813631 CN 99813631 CN 99813631 A CN99813631 A CN 99813631A CN 1346557 A CN1346557 A CN 1346557A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
- H04W88/02—Terminal devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/24—Radio transmission systems, i.e. using radiation field for communication between two or more posts
- H04B7/26—Radio transmission systems, i.e. using radiation field for communication between two or more posts at least one of which is mobile
- H04B7/2615—Radio transmission systems, i.e. using radiation field for communication between two or more posts at least one of which is mobile using hybrid frequency-time division multiple access [FDMA-TDMA]
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Abstract
A user station includes a control system for managing time slot operations for a system using aspects of TDMA/TDD and FDMA/FDD, to allow the user station to communicate periodically with a base station. The control system comprises an over-the-air driver for interfacing with upper layer protocol functions, and a slot manager for interfacing with the hardware to handle slot-related functions. The slot manager maintains a list or queue of slot objects, each defining a group of one or more time slots forming a logical communication channel. The slot manager configures the hardware to process each time slot at the appropriate time within a time frame. Different slot objects may be created for voice, signalling or other data traffic, and each slot object may cause the user station to communicate with the base station in one or more time slots of the time frame. The over-the-air driver instructs the slot manager to add, modify or delete slot objects based on requests from upper layer protocol functions. The control system may include service routines for performing data transfers in response to interrupts generated by a hardware controller (such as a control ASIC). The user station hardware may include a set of direct access data channels controlled through the use of interrupts to a peripheral event controller (PEC). The user station control system may also comprise components for radio reconfiguration, ARQ processing and power control processing.
Description
Background of invention
Invention field
The present invention relates to a kind of method and apparatus of in a multi-access communication system, managing and control time slot operations.
Background
The various technology that allow a plurality of users to utilize shared communication resource and one or more fixed station (that is base station) to communicate are known.The example of multi-access communication system comprises various types of cellular radio network drawn game field wireless communication nets, such as dedicated packet switched (PBX) net.In this multi-access communication system, for example, can adopt variety of way, such as according to different frequencies, time slot, and code distinguish transmission from various information source.
Thus, distinguish that according to transmitted frequency the communication system of transmission can be referred to as frequency division multiple access (FDMA) communication system.Forward link on a frequency transmits the communication system of matching mutually with the reverse link transmission on another frequency can be referred to as Frequency Division Duplexing (FDD) (FDD) communication system.
Distinguish that according to relevant transmission sequential (that is, using time slot) communication system of transmission can be referred to as the time division multi access (tdma) communication system.Can be referred to as time division duplex (TDD) communication system in the forward link transmission of (or period) during the time slot with the communication system that the reverse link of (or period) during another time slot transmits pairing mutually.
The communication system of the coding that transmits being distinguished according to employed code can be called as Code Division Multiplex access (CDMA) communication system.In cdma communication system, data to be transmitted are encoded usually in some way, in a kind of mode, cause signal to be arrived wider frequency by " spread spectrum ", and also cause signal power to reduce with the frequency bandwidth expansion usually.In receiver side, signal is decoded, and signal is resumed by " despreading " and permission primary signal.Unique code can be used to distinguish transmission, thereby allows a plurality of communications simultaneously, although transmit with the power level that is lower than " arrowband " FDMA or tdma system usually on broad frequency band.Thereby different users can transmit on identical frequency simultaneously, and can the phase mutual interference.
Introduce more than one multiple-access communication technology various " mixing " communication system be developed or be suggested.For example, gsm system can be considered a kind of " mixing " communication system of utilizing FDD and two kinds of technology of TDMA.
In the communication system of utilizing TDMA or TDD feature, comprise " mixing " type system, the management of the forward direction of subscriber station and the relevant time slot operations of reverse link may face the challenge, and partly cause is sequential and synchronous restriction.For example, for the time frame that the base station is set up, subscriber station perhaps needs accurately to control its received frame window and it transmits frame window.Subscriber station may also need to handle the data (for example, decoding or correction/processing) of reception, and at one time or at once must be to base station foldback data.
In addition, the burst sequence characteristic of the TDMA of grouping or TDD communication may cause the particular difficulty possibility at the subscriber station of deal with data.For example, carrier or speech data may need to be divided into a plurality of packets that perhaps transmit on the frame for a long time several according to the data volume that will transmit, equally, need according to perhaps from the packet that the base station receives, rebuilding carrier or speech data on the frame for a long time several.May also need to encode after reception or before transmitting or decoding algorithm (for example, phonetic synthesis) is handled, and Error processing, so increase the complexity of control and treatment at subscriber station.
Except various sequential and environmental limitations, subscriber station may also need treaty and handle different types of messages, such as signaling (that is control) service message and normal bearer services message.For example, subscriber station may need the exchange of signaling service message ability so that set up communication or to the handover of other base station.The subscriber station hardware interface may need rapidly effectively response from the instruction in the signaling message of base station.In addition, subscriber station may wish to support the high-level protocol feature, such as hypervelocity rate or subrate communication.
In the communication system of using FDMA or FDD (also having TDMA or TDD in addition), may run into further difficulty.For example, the radio of subscriber station may need the switching between reception and the transmission frequency is periodically disposed again.Wireless configuration again may need to take place simultaneously to rigidly connecting the processing of the data that receipts maybe will send.Subscriber station also needs to control radio, so that allow the supervision of adjacent base station and carry out handover when needed.
Therefore, being provided at the equipment and the method for management time slot operations in the communication system with TDMA or TDD, will be useful.In addition, providing and can and communicate required a plurality of whiles or equipment and method that approximate simultaneous task is handled to the time slot of management multi-access communication system, will be useful.In addition, providing one can handle the data that receive from the base station, can prepare again simultaneously to send information to the base station, and be the subscriber station of effectively handling with the minimum possibility of obliterated data, will be useful.In addition, the ability that provides dynamically reconfigures its radio, by the different frequency between time slot (with/or use different sign indicating number) send and receive so that execution FDMA or FDD (with/or CDMA) subscriber station of communicating by letter, will be useful.In addition, providing to have the high-level protocol ability and for example have by the hypervelocity rate or subrate sends and the subscriber station of receiving ability, will be useful.In addition, can be associated with the communication in TDMA or the TDD environment management time slot and peripheral function are provided, supporting different communication environment and agreement (for example, FDD or FDMA) in addition and support the subscriber station control system that the dynamic radio of the handover between the base station reconfigures, will be useful.
Summary of the invention
One aspect of the present invention provides the time slot operations in a kind of management of wireless communications system, and is particularly suitable for the method and apparatus that uses in the communication system of utilizing features such as FDMA or FDD and TDMA or TDD.
In one embodiment, the subscriber station control system comprises by the microprocessor utilization and interrupts communicating and an event-driven structure of activation manipulation.Microprocessor responds this interruption by data being called in various hardware componenies or access data from various hardware componenies, for example various hardware components are to send and received frame storage buffer, digital signal processor (DSP) and sound synthesizer, and wireless channel.In one embodiment, the various interruptions of microprocessor responds, the transmission of its each interrupt requests data discrete amount (for example, single byte).A plurality of private counter are write down the total amount of byte of transmission, interruption subroutine starts microprocessor and carries out each data passes, perhaps notify the microprocessor data transmission to take place, arrive predetermined calculated value or be under an embargo until other counters until suitable counter.
In another embodiment, the subscriber station control system comprises the software section of various management and control time slot operations.The subscriber station control system can comprise a time slot manager, is used to be provided with time slot and is used for keeping working time slot by tabulation or queueing form.The subscriber station control system may further include (OTA) driver in the air, is used to connect various hardware components (for example, the DSP/ sound synthesizer), and also being used for is increasing, upgrading or instruction time slot manager during from time slot tabulation or queuing deletion working time slot.The time slot manager can be lined up by slotted messages with the OTA driver and be communicated by letter.The subscriber station control system preferably includes various direct memory access (DMA) data passes tasks, so that permission access hardware register and various hardware come from the data passes between the target.In addition, the subscriber station control system can comprise be used for that radio reconfigures, ARQ handles and the parts of power control and treatment.
In another embodiment, microprocessor is programmed according to the algorithm of the time slot operations in control and the leading subscriber station.Control ASIC docks with microprocessor, and the interface with various hardware componenies is provided, and these hardware componenies comprise for example program storage, random access memory, DSP/ sound synthesizer, linearizer and radio device.Microprocessor can comprise the peripheral event controller of response from the interruption of control ASIC input.Microprocessor can (for example send the relevant predetermined amount of data that will transmit to control ASIC between hardware component, byte number) instruction, control the peripheral event controller of ASIC then, the direct transmission of beginning data for each byte interrupt microcontroller that will transmit.
The subscriber station control system of a management time slot operations is provided in another embodiment.Wherein subscriber station can while and more than one base station communication.The subscriber station control system is that each time slot or the relevant relevant group of time slot keep a discrete data profile with the form of time slot object preferably, dynamically reconfigure the subscriber station radio (if suit with data profile according to current time slots, comprise its operating frequency), to send or to receive.When the current time slots processing finishes, load the control and the configuration parameter that are used for next time slot.Each time slot is preferably in and comprises the indicating device (that is pointer) that identifies next working time slot in its data profile.Can be for each efficient communication channel (no matter signaling, voice or data) increase time slot object, and can when communication channel is closed, delete time slot object.In a kind of situation, communicate by letter simultaneously by providing with the different base station ability of (in genuine different time-gap of identical time) of subscriber station control system for subscriber station, for subscriber station provide be handed over to other base station from a base station or monitor near the ability of base station.
In another embodiment, management TDMA or a TDD communication system (with/or FDD or FDMA communication system) in the subscriber station control system of time slot operations, by providing GSM operation sequence with a subscriber identification module (SIM) card docking that is arranged in the subscriber station.The subscriber station communications system can comprise provides the control of interface between microprocessor and SIM card ASIC.
Other embodiment of the present invention, modification, variation and enhancement mode also will here further be set forth.
Brief description of drawings
Fig. 1 is the schematic diagram of cellular system;
Fig. 2 is the Figure of abstract of the part of the optimization software system that adapts with various aspects of the present invention and its relevant interface;
Fig. 3 is the present invention's subscriber station that can be used or the block diagram of mobile phone;
Fig. 4 carries out the frame structure schematic diagram that FDD communicates by letter between a base station and a plurality of subscriber stations;
Fig. 5 and Fig. 6 are other the frame assumption diagrams that carries out between a base station and a plurality of subscriber stations that FDD communicates by letter;
Fig. 7 is the process chart of a subscriber station of control;
The data path figure of Fig. 8 modern operation flow of letter that to be diagram adapt with the preferred embodiment of subscriber station;
Fig. 9 is the sequential of diagram signaling traffic and the sequential chart of ordering;
Figure 10 is the be dominant data path figure of flow process of the voice that select embodiment or bearer service of diagram user;
Figure 11 is diagram voice or the sequential of bearer service and the sequential chart of ordering;
Figure 12 is the sequential chart of diagram time slot object access control;
Figure 13 is the sequential chart of diagram time slot interrupt sequence;
Figure 14 is the tabulation of automatic repetitive requests (ARQ) state;
Figure 15 is the high order system figure of the preferred control section of subscriber station that adapts with some aspect of the present invention described here;
Figure 16 is an optimum decision system memory mapped schematic diagram;
Figure 17 is the memory mapped schematic diagram that easily loses memory space;
Figure 18 is transmission/received frame memory construction figure;
Figure 19 is the example that concerns between diagram time slot object and the time slot.
DETAILED DESCRIPTION OF THE PREFERRED
Fig. 1 is the schematic diagram with cellular communication system 101 of base station and subscriber station.In Fig. 1, the communication system 101 of communication comprises a plurality of unit 103 in a plurality of subscriber stations 102, and its each unit has and is usually located at unit 103 central authorities or near base stations 104 it.Each station (base station 104 and subscriber station 102) can comprise a receiver and a transmitter usually.Subscriber station 102 and base station 104 preferably use described Frequency Division Duplexing (FDD) (FDD) technology to communicate, and wherein communicate by letter on a frequency band in base station 104, and subscriber station 102 is communicated by letter on another frequency band.Communication preferably is implemented as different subscriber station 102 and transmits in the different time (that is, during different time slots), as further described.
Shown in Fig. 1 was further, communication system 101 can also be included in the base station controller 105 that specific geographic area connects base station 104.Base station controller 105 is assembled the input of a plurality of base stations 104, and the information relay from base station 104 also finally is relayed to public switch telephone network (PSTN, or " network ") (marking among the figure) to mobile switching centre (MSC) (marking among the figure).Base station controller 105 also arrives each base station 104 to the information relay that comes automatic network.In case of necessity, base station controller 105 can be carried out and relate to for example mobile management and the conversion of calling out the signaling message of controlling, and the communication protocol that signaling message and base station 104 are used is compatible mutually.
In a preferred embodiment, wireless communication system comprises a frame structure, and this frame structure is suitable for distinguishing to still from the transmission of subscriber station and be suitable for sending the base station and transmitting being different from frequency band that subscriber station transmits according to the time (that is, TDMA and TDD).A kind of typical frame structure that can utilize in a kind of like this wireless communication system is shown in Figure 4, and will be described hereinafter.The example of other frame structures is shown in Fig. 5 and Fig. 6, and will be described hereinafter.Yet, also can use other frame structures related with the inventive features the frame structure shown in Figure 6 with described here except that Fig. 4, Fig. 5.
In frame structure shown in Figure 4 401, repeat time frame 402 and comprise set of time-slot 403, each time slot 403 comprises the very first time section 417 and second time period 418.Can on a plurality of frequency bands, stipulate time slot 403, so that carry out FDD or FDMA communication.Therefore, time slot 403 can be divided into about the base station sending time slots 405 of base station transmission band 411 with about user's sending time slots 406 of user's transmission band.Each base station sending time slots 405 is preferably right with 406 groups of corresponding user's sending time slots, the duplex channel (nearly N total duplex channel) of a such group to having determined communication.Once request, can distribute to subscriber station 102 to N duplex channel.
In a preferred embodiment, the number of the time slot 403 in time frame 402 is 16, and the number of base station sending time slots 405 and user's sending time slots 406 equally also is 16.In addition, in a preferred embodiment, carry out the pairing between base station sending time slots 405 and the user's sending time slots 406, make user's sending time slots 406 and 405 groups of base station sending time slots right, eight time slots (that is half of time frame 402) after this occur.Subscriber station 102 is preferably in the very first time section 417 of user's sending time slots 406 and sends, and base station 104 is preferably in second time period 418 of base station sending time slots 405 and sends.In other words, during the very first time of user's sending time slots 406 section 417, distributed the subscriber station 102 of duplex channel to send subscriber station message to base station 104; During second time period 418 of relevant base station sending time slots 405, base station 104 sends base station message to the subscriber station 102 that has distributed duplex channel.
A consideration of design frame structure 401 is to allow TDD equipment that the adaptability comparatively easily of carrying out the FDD function is arranged.So, base station message is separated (promptly in time with subscriber station message, subscriber station 102 sends during the very first time of time slot 403 section 417, and base station 104 sent during second time period 418 of time slot 403), although the time separate be not avoid interference necessary because base station message is also separated by frequency with subscriber station message.When the TDD base station of the single frequency band that is used in base station and user transmission is transformed into the base station of using FDD, frame structure 401 is favourable, because in the very first time section 417 that must switch each time slot 403 with between second time period 418 in the frequency, the base station that is used can be between user's transmitting time section of each time slot and base station transmitting time section the same correlation timing of maintenance.So for the frame structure 401 of Fig. 4, base station 104 does not need to possess the ability that sends simultaneously and receive on two different frequency bands, and does not need for example equipment of duplexer.
Although a preferred embodiment of the present invention that the following describes relates to frame structure shown in Figure 4 401, also introduced here can related use with described inventive features and method other frame structure.Specifically, other frame structure illustrates in Fig. 5 and Fig. 6.For frame structure shown in Figure 5 501, repeat time frame 502 and comprise set of time-slot 503, image pattern 4 is divided into like that about the base station sending time slots 505 of base station transmission band 511 with about user's sending time slots 506 of user's transmission band 512.Each base station sending time slots 505 is preferably right with 506 groups of corresponding user's sending time slots, the duplex channel (amount to N duplex channel) of a such group to having determined to be used to communicate by letter.Yet different with the frame structure of Fig. 4 is that time slot 503 is not divided into the very first time section and second time period.But, during each user's sending time slots 506, distributed the subscriber station 102 of duplex channel to send subscriber station message to base station 104 through user's transmission band, during each base station sending time slots 505, base station 104 sends the base station through the base station transmission band to the subscriber station 102 that has distributed duplex channel and transmits message.Thereby carry out base station 104 and the multiple-access communication of a plurality of subscriber stations 102.Usually, communicate by letter with N subscriber station 102 nearly in N time slot 503 of time frame 502 in base station 104, unless more than one time slot (user's time slot 506 and base station time slot 505, have with the both) gathered unique user station 102, perhaps another the time when communicating by letter image duration more than one other subscriber stations 102 be assigned with and share single time slot 503.In one case, the advantage of frame structure 501 is can support to double the subscriber station 102 that frame structure 401 is supported, except requiring base station 104 can send simultaneously and receive on two different frequency bands 511,512, other conditions are all identical, and this is different from the frame structure 401 of Fig. 4.
Another frame structure 602 shown in Figure 6 is similar with frame structure shown in Figure 4, and its difference is that base station 104 does not require and can send simultaneously and receive at different frequency bands.For frame structure shown in Figure 6 601, repeat time frame 602 and comprise one group of base station sending time slots 605 and one group of user's sending time slots 606.Each base station sending time slots 605 is preferably right with 606 groups of corresponding user's sending time slots, the duplex channel (nearly N total duplex channel) of a such group to having determined communication.Time frame 602 the first half 602a during, base station 104 sends in each base station sending time slots 605 continuously through base station transmission band 611.For user's transmission band 612, time frame 602 the first half 602a are " deceiving " or be not used.During the second half 602b of time frame 602, subscriber station 102 sends on user's transmission band 612 continuously.For user's transmission band 611, time frame 602 the second half 602a are " deceiving " or be not used.Best, base station sending time slots 605 is right according to same relative sequence order and 606 groups of user's sending time slots, so the first base station sending time slots 605 and 606 groups of first user's sending time slots are right, the second base station sending time slots 605 and 606 groups of second user's sending time slots are right, or the like.In such preferred embodiment, each base station sending time slots 605 is right with 605 groups of half user's sending time slots that separates by time frame 602.
Among the described here embodiment, can set up communicating by letter between base station 104 and the subscriber station 102 by any suitable method, these methods comprise for example U.S. Patent application 08/284, method described in 053 and technology, this patent application was submitted on August 30th, 1994, and transfer assignee of the present invention, thereby all quoted as reference at this.According to a kind of technology that application serial 08/284,053 proves absolutely, base station 104 is effectively sending " ordinary round-robin " message in each identical time slot to communicating by letter.Expectation is set up the subscriber station 102 communicate by letter with base station 104 and is responded an ordinary round-robin message by sending a trivial response message to base station 104, and the response message that is sent is transmission in the same time slot of transmission ordinary round-robin message (or with the corresponding user's sending time slots of base station sending time slots) preferably.As the part of ordinary round-robin message, subscriber station 102 sends a subscriber station identifier.Trivial response message is once reception, and base station 104 just is preferably in the time slot identical with sending ordinary round-robin message and sends a special polling message to subscriber station 102.This special polling message is once reception, and subscriber station 102 can send a special response message, or can begin communication information in suitable time slot.
In one embodiment, subscriber station 102 can be asked a circuit switching to new base station 104 by at first setting up and the communicating by letter of new base station 104, and abandons original link then, and communication is switched to a base station 104.Subscriber station 102 can monitor the quality of signals that receives from other home base stations 104, when handover case appears in hope, by the common training in rotation message in the effective time slot that responds new base station 104, sets up a communication link with new base station 104.New communication link is once foundation, and subscriber station 104 just orders old base station 104 to switch to the circuit that is used to call out, and stops the communication link with old base station 104 then.Abandoned up to old link, subscriber station 102 keeps two separate links in the time slot of two separation, and be likely on different frequency with/or use the different code group to keep these two to separate link.
In conjunction with a preferred, users station 301 (for example, mobile phone) shown in Figure 3 some feature of the present invention can be described easily.As shown in Figure 3, subscriber station 103 comprises a radio transceiver 305 (comprising a transmitter 315 and a receiver 316), believes the antenna 306 that 305 machines are connected with transceiving for one, with an aerial controller 310 that is connected with radio transceiver 305.Aerial controller 310 is connected with a storage buffer 311.Control controller 310 management wireless receiving and dispatching pagers 305 are sought the information stores that message is deposited in storage buffer 311 that the information retrieval of the information that sends to the base station 104 of communicating by letter with subscriber station 301 and managing radio transceiver 305 are carried out when this information that receives from base station 104 from storage buffer 311.
Storage buffer 311 connects modulus (A/D) converter 331 and digital-to-analogue (D/A) converter 332.A/D converter 331 is connected the sound synthesizer 335 that is connected with loud speaker/microphone 336 with D/A converter 332.D/A converter 332 will 104 information that receive and deposit in the storage buffer 311 be transformed to analog format from number format from the base station.Sound synthesizer is handled this analog format information then, and sends signal to produce sound or other sound that user/listener can listen to loud speaker/microphone 336.Loud speaker/microphone 336 also picks up from user's sub-audible sound or other sound, and analog data signal is transferred to sound synthesizer 335.Sound synthesizer 335 is handled this analog data signal, the analog data signal of handling is sent to A/D converter 331, to transform to number format.These number format data are stored in the storage buffer 311 subsequently, and are sent to base station 104 in suitable time slot.
Fig. 3 also shows the details of aerial controller 310.As shown in the figure, control controller 310 comprise one with the time frame counter 321 clock 320 being connected with time slot counter 322.The time frame counter 321 be connected with control logic circuit 323 with time slot counter 322, the output formatization of 323 time spent of control logic circuit frame counter 321 and time slot counter 322 is used for the message of air communication.Aloft under the control of controller, radio transceiver 305 storages and elimination are from the information of storage buffer 311.Radio transceiver 305 also comprises transmission/reception (T/R) switch 317 that permission is selected between sending mode and receiving mode.Control logic circuit 323 these T/R switches 317 of control of aerial controller 310, thereby, between sending mode and receiving mode, selecting when forward part for example according to time frame (such as, described elsewhere time frame 401).When being in sending mode, controller 301 is selected user's transmission frequency (for example, the user sends frequency band 412), and when being in receiving mode, aerial controller 310 is selected base station transmission frequency (for example, the base station sends frequency band 411).
In a preferred embodiment, control logic circuit 323 comprises a microcontroller or microprocessor 327 (such as a Siemens C163/C165 processor) and a control ASIC328 (also being referred to as " MSCA " sometimes).Control ASIC 328 can provide the interface between many other hardware componenies of microprocessor 327 and subscriber station 301, these parts comprise radio transceiver 305 and loud speaker/microphone 336, and encoder/decoder (CODEC) and digital signal processing circuit.MSCA 328 can comprise various general and special registers, so that the execution of various functions.The example of such register comprises with lower member:
The receive data register of not encoding
The coding transmitting data register
The time slot mapping pointer register
The normal state register
Interrupt control register
Compare input register
Compare counter register
DSP data/control byte register
The DSP source register
The reception sources register
Send destination register
The sleep control register
The accepting state register
The RC counter register
The agreement control register
Radio configuration/time slot mapping data register
Radio configuration sign indicating number register
General destination register (writing)
The normal state register
In a preferred embodiment, microcontroller comprises peripheral event controller (PEC), is used to receive the interim interruption that is used for data passes or similar task from MSCA 328.The radio transceiver control and treatment preferably provides the coordination of all registers of MSCA 328 to upgrade and is comprised in aerial operation or time slot and relies on signal in the operation.
The details of " control section " 1501 that is commonly referred to as the subscriber station of a preferred embodiment or mobile phone is shown in Figure 15.Shown in Figure 15 illustrated embodiment, control section 1501 comprises an air line card assembly (OTA LCA) 1502, and this assembly 1502 comprises controller logic circuit 1503 and wave point logical circuit 1504.Controller logic circuit 1503 can comprise a control ASIC 1591 (similar to the general function of the control ASIC 328 of Fig. 3).OTA LCA 1502 connects with microcontroller 1505 (for example, Siemens SABC-165 microcontroller).In one embodiment, microcontroller 1505 especially comprises a microprocessor and one or more serial port (at least one of high-speed synchronous serial port).OTA LCA 1502 is connected by one group of control line 1561 with microcontroller 1505, comprises a broken link 1542, one control, 1543, one clock cables 1544 of link and one group of sheet choosing (CS) line 1545 in the device.In a kind of situation, OTALCA 1502 provides the control interface between radio transceiver 305 (referring to Fig. 3) and the microcontroller 1505.Microcontroller 1505 can move into and shift out OTA LCA 1502 with data.Read the state of OCA LCA 1502, with/or it carries out the order of some predetermined action to send instruction to OTA LCA 1502.
Except control line 1561, system bus 1530 is connected to microcontroller 1505 to OTALCA 1502.System bus also connects static RAM (SRAM) (SRAM) 1524 and fast storage 1525.SRAM 1524 can be that for example capacity is 128K (octet), and fast storage 1525 can be that for example capacity is 256K (16 bit byte).
As shown in figure 15, the controller logic circuit 1503 of OTA LCA 1502 is connected with linearizer ASIC 1513 with keyboard 1523, battery monitor 1522, digital signal processor/sound synthesizer (DSP/ sound synthesizer) 1501.Controller logic circuit 1503 is connected with wave point ASIC 1514 with wave point logical circuit 1504, and then is connected to radio transceiver (such as, radio transceiver 305 shown in Figure 3).The controller logic circuit 1503 of OTA LCA 1502 preferably also connects SIM port one 520 by SIM line 1533, and wherein SIM port one 520 couples mutually with subscriber identification module (SIM) card (not marking among the figure).At a preferred embodiment, SIM card is utilized to carry out a plurality of about GSM and user environment operation sequence.Such example comprises the storage of the regulation and the user specific information of system safety, comprises such as authentification of user and the such thing of user's particular data.SIM port one 520 also connects microcontroller 1505 through status signal lines 1534.
Figure 16 shows the system memory map related with control section shown in Figure 15 1501.As shown in figure 16, system storage 1601 is divided into image storage section 1602 and non-image storage area 1603.Image storage section 1602 whole are included in same section of system storage 1601 (for example, section 0).In the embodiment shown in Figure 16, image storage section 1602 comprises one or more fast storages 1611,1612 and 1613 (being associated) with fast storage 1525 shown in Figure 15, a SRAM part 1614 (being associated) with SRAM 1524 shown in Figure 15, internal RAM part 1627 (being associated) with the random access memory and the cache memory of microcontroller 1505 inside shown in Figure 15, with a periphery/LCA register 1616 (being associated) with OTALCA 1502 and various peripheral unit shown in Figure 15, if any, and various obsolete part 1615." guiding " sign indicating number of microcontroller 1505 is placed in first (that is, minimum) fast storage part 1611.In addition, required storage preferably is mapped in the section 0 of said structure in some direct memory access (DMA) (DMA) operation.Image storage section 1603 in embodiment illustrated in fig. 16 comprises: 1619, one prototype SRAM of 1618, one SRAM parts of fast storage part part 1620 and a prototype fast storage part 1621.Prototype SRAM part 1620 and prototype fast storage part 1621 are used for participating in code development, and may need to use additional chip selection signal line.
Figure 17 is the schematic diagram that describes SRAM memory assignment map 1701 in detail.As shown in figure 17, SRAM is divided into one group of common software zone 1702,1709 and 1710, time slot/frequency diagram 1702, with a different set of buffer, it comprises a commands buffer 1704, SIM buffer 1705, reception buffer 1706, transmission buffer 1707 and linearizer buffer 1708.Transmission buffer 1707 and reception buffer 1706 are utilized by radio transceiver 305 (referring to Fig. 3) usually, and linearizer buffer 1708 has linearizer ASIC 1535 to utilize usually, and the SIM buffer is utilized by SIM card (connecting through SIM port one 520) usually.
Data can be stored in according to form shown in Figure 180 in SRAM transmission buffer 1707 or the reception memorizer 1706.According to data format, data information memory piece 1801 comprises 1807, one carrier data fields 1906 of 1808, one D channels of header field field and a sound synthesizer control field 1805, can also comprise a reserve part 1804.In a preferred embodiment, header field 1808 comprises 17 bits (being used for message to be sent) or 23 bits (message that is used to receive) of information, D channel field 1807 comprises a byte of information, and carrier data field 1806 comprises that 24 byte sound synthesizer control fields 1805 of information comprise 10 bytes of information.
In a kind of situation, control section 1501 provides the drives interrupts structure of control communications transaction.The incident that appears at outside the microprocessor is known as peripheral incident, and can cause interruption.These interrupt being produced by OTA LCA 1502 usually, and microcontroller 1505 is given in 1542 couplings through interrupt line.Microcontroller 1505 preferably includes internal circuit, specifically a peripheral event controller (PEC) that is used to handle this interruption.The interruption that is caused by peripheral incident can make peripheral event controller log-on data move.Specifically, peripheral event controller can respond an interruption by carry out the transmission of DMA type-word joint through system bus.Different application may need more than one data byte.In one embodiment, isolate each byte (for example, 20 of data bytes need 20 independent interrupt requests) of interrupting being used to data to be passed.The required data passes number (and interruption times from then on) of special applications is preferably learnt by software in advance, and is based upon on the basis of interrupt type.After required byte number is moved, the suitable interrupt service routine of microcontroller 1505 guiding.
Except that PEC interrupts, can also from other hardware or software source, the generation standard interrupt.The priority level that PEC interrupts and standard is interrupted can be by software setting.OTA LCA1502 can comprise an interrupt status machine, is used for the processing events signal and produces where necessary interrupting.If microcontroller 1505 is in sleep state or is in power-down mode when interrupting taking place, then the interrupt status machine can order clock circuit (being used for sleep or power-down mode) and reset circuit (being used for power-down mode) to wake microcontroller 1505 up.In case the interrupt status machine is seen one from resetting and the indication microcontroller 1505 of clock circuit fully during the response of operation, the interrupt status machine is interrupting imposing on microcontroller 1505.Carve at this moment, the interrupt status machine will be shown to all interruptions of having asked so far.For example, if a startup PEC interrupt requests is derived from SIM and receives processing when microcontroller 1505 is fallen asleep or cut off the power supply, and another PEC interrupt requests receives from a various information source during microcontroller 1505 is waken up, and then simultaneously presents this two interrupt requests to microcontroller 1505.When each interrupt requests was moved, its request was eliminated.Have only when all interrupt requests of presenting to microcontroller 1505 have been moved, the interrupt status machine can be handled a new request.
In one embodiment, peripheral type of interrupting is provided by following table 1-1.
Table 1-1
| Interrupt | Information source | Target |
| ????1 | The SRAM transmission buffer | Transmitter |
| ????2 | Receiver | The SRAM reception buffer |
| ????3 | The dsp code data | The SRAM transmission buffer |
| ????4 | SRAM SIM buffer/SIM receiver | The SIM transmitter |
| ????5 | Linearizer SRAM buffer linearizer data/control | Linearizer SRAM buffer linearizer data/control |
| ????6 | The SRAM commands buffer | Order relatively |
| ????7 | The SRAM reception buffer | Receive DSP data/control |
| ????8 | Fast storage | Radio configuration/time slot mapping data |
| ????9 | OTA LCA error | Normal state |
Peripheral event interrupt can by to the hard pulse of the appointment input pin (for example, the pin EX0IN-EX7IN of Siemens SABC-165 microcontroller and pin T2IN) of microcontroller 1505 should be used for advocate.
Below, explain the operation sequence of peripheral event interrupt in more detail.When OTA LCA1502 needs data to send, it advocates that Class1 interrupts (according to table 1-1), operation that may further comprise the steps of microcontroller 1505 usefulness responds: write OTA LCA transmitter register (0E010H) from SRAM transmitter register 1707 sense datas (referring to Figure 17) with these data.These data further are passed to radio transceiver 305 (referring to Fig. 3) at the appropriate time that sends.
For the reception of data, OTA LCA 1502 advocates type 2 interruptions (according to table 1-1), the data in the OTA LCA receiving register (0E011H) is inserted the reception buffer 1706 (referring to Figure 17) that receives SRAM with request.One of microcontroller 1505 usefulness comprise from OTALCA receiving register sense data and the operation that these data write SRAM reception buffer 1706 steps are responded.
In operation, subscriber station 102 in the control section 1501 participation multi-access communication systems or 301 data transmit and receive.Control section 1501 also is useful preferably according to operating such as Fig. 4, Fig. 5 or the disclosed frame structure of Fig. 6 but adopt various other frame structures.Information via Radio Link 1590 shown in Figure 15 is sent to radio transceiver 305 (referring to Fig. 3) and sends from radio transceiver 305.Under the control of microcontroller 1505, information is handled by RIF ASIC 1514 and OTA LCA 1502, and sends DSP/ sound synthesizer 1510 and CODEC 1511 to and send out from DSP/ sound synthesizer 1510 and CODEC 1511.DSP/ sound synthesizer 1510 can combined voice synthesizer function, and can speech data is provided and shift out speech data from CODEC 1511 to CODEC 1511 according to suitable subrate speech coder algorithm.Speech data can be formatted as 64K μ rule pulse-code modulation (PCM) data.
The packed data that DSP/ sound synthesizer 1510 is set up before sending base station 104 to, stores in the SRAM transmission buffer 1707 by OTA LCA 1502.A time between the beginning of transmit frame, OTA LCA 1502 begins from DSP/ sound synthesizer 1501 request msgs, and DSP/ sound synthesizer 1501 usefulness respond through the serial data stream of serial transmission line 1540.DSP/ sound synthesizer 1510 can provide a single byte when OTA LCA 1502 each requests, and when data were received by OTA LCA 1502, PEC interrupted (that is the type 3 that defines) here and advocated by OTA LCA 1502.During response, microcontroller 1505 writes data into SRAM transmission buffer 1707.In a preferred embodiment, before transmit frame starts, comprise that the whole Frame of carrier (for example, voice) data and state byte will move to SRAM transmission buffer 1707 from DSP/ sound synthesizer 1510.
After transmit frame started, OTA LCA 1502 advocated that Class1 interrupts (the following definition), with a byte of request coded data from SRAM transmission buffer 1707.When response, microprocessor sends coding (voice) data from SRAM transmission buffer 1707 to OTA LCA 1502.OTA LCA 1502 asks coded data in the same manner continuously, is sent out until whole transmit frame.
The reception data of compressed format send to the DSP/ sound synthesizer 1510 that is used to decompress through OTA LCA 1502.The data that receive at first are stored in the SRAM reception buffer 1706, by OTA LCA 1502 data are sent out from reception buffer 1706 then.Be compressed in reception before first byte of carrier (for example, voice) data, OTALCA 1502 writes DSP/ sound synthesizer 1510 to sync byte.Sync byte can be stored among the OTA LCA 1502 and send DSP/ sound synthesizer 1510 to, and need not intervened by microcontroller 1505.When data when receiving, are temporarily stored in OTA LCA 1502 from radio transceiver 305 (referring to Fig. 3) through Radio Link 1590.For each byte that receives data, advocate that by OTA LCA 1502 PEC interrupts (that is, the type 2 of definition is here interrupted).When response, transmit the data byte in the SRAM reception buffer 1706.When each byte of carrier (for example, voice) data is received and stores in the SRAM reception memorizer 1706, by OTA LCA 1502 serializations and be sent to DSP/ sound synthesizer 1510.Finish after the reception of carrier data, OTA LCA 1502 produces an interruption that request is received the microcontroller 1505 of the control byte that is used for DSP/ sound synthesizer 1510.When this interrupted in response, microcontroller 1505 sent control data to OTA LCA 1502, and OTA LCA 1502 sends this control data to DSP/ sound synthesizer 1510 serially.
During the process that receives data, ideal situation is to begin to confirm and preliminary treatment before receiving whole Frame.In order to begin this processing, one group of expection of microcontroller 1505 structures is agreed the command template of each received frame and is used for the mask of these templates.This group command template and mask are temporarily stored in SRAM command register 1704.If subscriber station is monitoring more than one time slot, each time slot that is monitoring for subscriber station in SRAM command register 1704 is set up a separate areas so.
Single template and mask comprise that jointly an order/mask is right.On behalf of 1505 expections of a microcontroller, the right command template of order/mask check the order (or data) of next received frame.After one or more command bytes were received as the part of received frame, command template compared with it.Command byte number relatively by, control from the relatively counting order of microcontroller 1505 to OTA LCA 1502 communications.The right mask of order/mask is provided at the ability of some selection bit of ignoring command template in the compare operation.For example, in one embodiment, any mask bit that comprises the mask of logical zero makes the corresponding bits refusal operation of command template, and does not influence the result.
In case microcontroller 1505 has been set up this group command/mask in SRAM commands buffer 1604 right, microprocessor just writes count value relatively in the compare counter register among the OTA LCA 1502.Relatively how many control bytes the count value indication has, and comprises that header byte will be compared.Therefore, relatively count value will equal header byte (for example, being three bytes in a preferred embodiment) usually at least.Comparison state machine device read-around ratio in the OTA LCA 1502 is loaded in the register that successively decreases than count value and it, for the series order is relatively prepared.In case retrieve the command template byte from SRAM commands buffer 1704, the comparison state machine device is that each compare operation is advocated twice interruption (promptly, the type 6 of definition is here interrupted), retrieval command template byte from SRAM commands buffer 1704 is retrieved the mask byte that responds for the second time from SRAM command register 1704 for the first time.For each the input command byte from received frame, the comparison state machine device uses two interruptions, from SRAM commands buffer 1704 retrieval command template bytes and mask byte (that is, an order/mask to).
For the not mask part of command template byte and the each comparison between the input command byte, the register that successively decreases among the OTA LCA 1502 (that is, comparing counter) subtracts 1.Receive to handle at the beginning, just will compare each command byte, the counting in counter relatively reaches zero, otherwise makes a unfavorable comparison (that is, the not mask of command template byte part does not match with the input command byte) and make the comparison process termination; Yet relatively counter successively decreases continuously with each reception byte.When relatively counter arrived zero, the check interrupt control register was to determine whether interruption should send; If then can send regular interrupt and the comparison template will be set.Interruption can be set to when received frame finishes and compare operation is sent when finishing.
In the time of outside comparative sequences advances to first byte (, relatively counter at least once successively decreases), OTA LCA 1502 will carry out transmitting data to DSP/ sound synthesizer 1510 and SRAM1524.During this is handled, preferably do not consider when to send interruption and do not consider that the result of comparative sequences produces RSSI information, so that subscriber station 301 search is used to communicate by letter according to signal strength measurement better time slot or a better base station 104.If compare after present first byte with right unfavorable of comparison/mask but arrived before zero at counter relatively, the PEC that then stops to be used in SRAM commands buffer 1704 storage data interrupts, to preserve energy.When relatively counter reached zero, whole received frame was stored in the SRAM reception buffer 1706.
If from the received frame of base station 104 comprise ordinary round-robin message and special polling message (can be in two message setting up use when communicate by letter between base station 104 and the subscriber station, as mentioned above), so above-mentioned processing can change a little.In a preferred embodiment, comprise one first header byte from the message of base station 104, it comprises the field (for example, ordinary round-robin message, special polling message, or other kind of message) of an indication packet type.If packet type is confirmed as indicating the reception of an ordinary round-robin message or a special polling message, whether then the comparison state machine device uses the current command template to carry out the operation of comparison/mask, be the command type of an expection to check ordinary round-robin message or special polling message.If comparison process is carried out in a manner described continuously so.Yet, if received frame comprises an ordinary round-robin or special poll, but command template does not indicate any one such message to expect, so the comparison state machine device will be not decline ratio than counter, to not store header byte in the SRAM reception buffer 1706 into, and incite somebody to action not index error.On the contrary, OTA LCA 1502 ignores remaining input message (although it may produce RSSI information continuously).When next received frame begins, 1502 pairs of ordinary round-robin message of OTA LCA or special polling message carry out similar test, respond in a similar manner, and repeat this processing until an ordinary round-robin or special poll is received or an overtime appearance (making microcontroller 1505 reset compare operation).The result of these special circumstances is when subscriber station searching ordinary round-robin message or special polling message, only microcontroller 1505 is interrupted/waken up to ordinary round-robin message or special polling message, thereby save electric energy.
For data are sent to SIM card, before starting the SIM interface, microcontroller 1505 writes the data that will send in the SRAM SIM buffer 1750.In case data place SRAM SIM buffer 1705, microcontroller 1505 just is written to the SIM transmitting counter to the byte number of data, thereby starts the SIM interface.OTA LCA 1502 advocates PEC interruption (that is, the type 4 of definition is here interrupted), obtains first byte of data from SRAM SIM buffer 1705, and obtains each byte of the data of transmission after this.For each byte of the data that retrieve, SIM transmitting counter countdown is finished to send on this aspect and is handled until arriving zero.
Under the parity error situation, SIM receives and preferably automatically resends data, does not need microcontroller 1505 to intervene.SIM receives and not to carry out another and send request (interrupting by PEC), until successfully sending in preceding byte, or from the generation that resets of microcontroller 1505.Reach predetermined times (for example, 3 times) if examination sends failure, the normal state register then is adjusted to indication SIM transmission mistake and microcontroller 1505 can send a reset signal to the SIM control circuit by general register.
During energized, or after the successful transmission sequence to SIM card finished, or when carrying out an outside SIM and resetting, SIM port one 520 is placed in receiving mode (receiving the data from SIM card).After SIM port one 520 received each byte from the data of SIM card, DTA LCA 1502 advocated interruptions (that is, as type 4 interruptions in this definition), makes data shift out and be moved into the SRAM SIM register 1705 from OTA LCA 1502.How many bytes microcontroller 1505 preferably remembers is transmitted (when how many bytes hardware does not know to have be received), and when expected numbers purpose byte had been received, microprocessor resetted the SIM state machine.Receiving operating period, microcontroller 1505 can be carried out a monitor function, does not interrupt or does not fail during handling to guarantee SIM card.
Except providing between microcontroller 1505 and SIM port one 520 interface, OTA LCA 1502 also provides an interface between microcontroller 1505 and the linearizer 1513.The bi-directional serial interface 1514 of linearizer ASIC 1513 through being used to transmit order and data is connected OTA LCA 1502.OTA LCA 1502 comprises a linearizer interface, and microcontroller 1505 these interfaces of order are with data serializing and send to linearizer ASIC1513, perhaps receive data from linearizer ASIC1513.The linearizer interface can also place specific automatic function pattern, but thereby can be periodically be loaded into the temperature-compensating instruction in the register of access linearizer ASIC1513, and do not need microcontroller 1505 to intervene.
Subscriber station 301 can comprise when not needing the abundant processing electromotive force of device the equipment by selectivity de-energisation circuit reduces power.When microcontroller 1505 determines that power reduction patterns are suitable, it just instructs OTA LCA 1502 ingoing powers minimizing pattern by an order being write the sleep control register.If microcontroller 1505 oneself cuts out fully, then at first in interrupt control register (0E016H), will cause interruption to information stores, and make microcontroller 1505 return abundant operating state with the indication incident.Do not wish stand-byly for a long time if some power is saved in microcontroller 1505 expectation, the low-limit frequencies that then can make microcontroller 1505 reduce it select to place its standby mode.In order to enter standby mode, microcontroller 1505 writes an appropriate command sleep control register of OTALCA1502.OTA LCA 1502 (for example, 1KHz) responds by master clock frequency being reduced to minimum tolerance frequency.Microcontroller 1505 before carrying out an operation by asking an interruption of handling by OTA LCA 1502 to make its own recovery full speed operation pattern.Microcontroller 1505 can also be by giving an order to OTA LCA1502, come selectively any or all to place the power reduction pattern, and selectively any device is returned to the overall operations pattern from the power reduction pattern DSP/ sound synthesizer 1510, CODEC 1511, digital radio ASIC and linearizer 1513.
The feature of the software control system of subscriber station 301 will be elaborated with particular reference to Fig. 2 and sometimes with reference to the control part component of the feature shown in the subscriber station of figure 3 and Figure 15.Although with reference to explanation is to be used for Fig. 3 and preferred, users station shown in Figure 15 configuration, should be understood that inventive concept that Fig. 2 relates to and feature be independent of these preferred embodiments and will in having the system of various other configurations, find application.
In Fig. 2, software control system 201 (, be known as the radio transceiver part of software sometimes here, or RTRX) generally include by the part shown in the solid line, and the part that is connected with control system 201 is shown by dashed lines usually.Except part shown in Figure 2, software control system also comprises not real time operating system (RTOS) shown in figure 2, and it provides a reciprocation of being convenient to part shown in Figure 2 or a software platform of operation.A plurality of parts shown in Figure 2 are described respectively below, are thereafter to the best reciprocation of the various piece of managing a subscriber station 301 communication and the explanation of operation.
Two major parts of software control system 201 comprise (OTA) driver 210 and time slot manager 211 in the air.OTA driver 210 is preferably controlled the transmission of subscriber station 301 and is received operation, and time slot manager 211 is preferably managed the operation of time slot object.OTA driver 210 and time slot manager 211 use the message queueing 212,213 that further specifies to communicate here.
As shown in Figure 2, software control system 201 comprises a wireless radio service module 217, it can be by OTA driver 210 and 211 accesses of time slot manager, and the digital ASIC in radio transceiver 305 (below be called digital radio ASIC, or DRA) provides a common interface.Software control system comprises that 201 also comprise a digital signal processor (DSP) Object Manager 215, is similar to wireless radio service module 217, also can be by OTA driver 210 and 211 accesses of time slot manager.The general objects of DSP Object Manager 215 is to determine and adjust renewal to DSP/ sound synthesizer object 216.Software control system comprises that 201 other parts comprise automatic repetitive requests (ARQ) module 220 and power control module 221, and these two modules are accessible to time slot manager 211.ARQ module 220 is comprised in the processing header information that is used for automatic repetitive requests, and power control module 221 is handled 104 power control commands that receive from the base station.
Software control system comprises that 201 communicate by letter with other components of system as directed with 244 through various mailboxes 141,242,243, and each mailbox preferably has the particular allocation function that describes in detail here.OTA driver 210 for example can be communicated by letter with OTA state machine 252 through slotted messages (SM) mailbox 242 (the SM mailbox of appointment among Fig. 2), or communicates by letter with digital signal processor (DSP) driver 251 through DSP mailbox 244 (the DSP mailbox of appointment among Fig. 2).The time slot manager 211 of software control system 201 can be according to the detailed description here through various direct memory access (DMA) (DMA) interface section 235,236,237,238 and the various memory locations of 239 accesses (comprising special register).
In a kind of situation, time slot manager 211 is hearts of software control system.Time slot manager 211 can define time slot object 231 and the relevant operation of carrying out time slot object, and this operation can comprise foundation, deletes, upgrades and inquire the ability of a time slot object 231.In addition, time slot manager 211 can be finished all time slot operations that response software slot synchronization incident (for example, interrupting) must be carried out.Time slot manager 211 can utilize the intrinsic knowledge of interruption to manage the operation of time slot object 231, and synchronization DS P control and state upgrade, and the synchronization of radio config update.
During its various processing, time slot manager 211 can use the service operations program that hardware is set, and configuration ISR is provided with PEC SMA path and upgrades time slot object 231.Time slot manager 211 can call 215 foundation of DSP Object Manager and start DSP object 216, carries out DSP control and upgrades, or upgrade the DSP state.Time slot manager 211 can call wireless radio service module 217 and be configured renewal, makes radio transceiver to slot synchronization.Between reception and transmission frequency, switch, read the RSSI value, or transmission power level is set.Time slot manager 211 can call the processing that ARQ module 220 control errors detected and recovered the OTA grouping.In addition, time slot manager 211 can call the transmission power level of power control module 221 control radio transceivers 305 (referring to Fig. 3).Time slot manager 211 can also use and power up/and the operation sequence of testing oneself sets up various PEC DMA path.
Send to finish (EOTX) ISR 227 interruption that the sending part timesharing of a time slot produces of finishing dealing with.EOTX ISR 227 is provided with a mark and produces a software and captures (capturing ISR 225 thereby call software), sends end process to carry out.305 DMA transmits when finishing the peripheral event controller of OTA LCA 1502 from SRAM 1524 to radio transceiver sending data, calls EOTX ISR 227.
Peripheral event controller (PEC) ISR (not marking among Fig. 2) handles at the DMA of PEC control and transmits the interruption that produces when finishing.PEC ISR is triggered when relevant PEC channel request DMA data passes is finished at OTA LCA 1502.
Various DMA data transmit tasks 223,235,236,237,238 and 239 and formulate for mobile data.Radio transceiver DMA data transmission task 235 will send data and move to radio transceiver 305 from SRAM 1524.DSP input DAM data passes task 236 moves to DSP/ sound synthesizer 1510 with DSP/ sound synthesizer control data from SRAM 1524.Radio reception DMA data passes task 238 will receive data and move to SRAM 1524 from radio transceiver 305.DSP output DMA data passes task 239 moves to SRAM 1524 with DSP/ sound synthesizer state and transmission data from DSP/ sound synthesizer 1510.Reception comparison DMA data passes task 237 will receive comparing data and move to OTA LCA 1502 from SRAM 1524.Radio configuration DMA data passes task 223 moves the radio configuration data between SRAM 1524 and radio transceiver 305.Above-mentioned DMA data passes task 223,235,236,237,238 and 239 each dock (for example, the control ASIC 1591 among Figure 15, or the control ASIC 328 among Fig. 3) with control ASIC or MSCA 205 in some way.
Wireless radio service module 217 the digital radio ASIC (DRA) in radio transceiver 305 provide a common interface.Wireless radio service module 217 provides multiple operation, and with configuration reception and transmission frequency, code and header, the control transmitted power makes radio to slot synchronization, reads the RSSI value, or disposes various threshold values.Wireless radio service module 217 is utilized the register of OTA LCA 1502 and by the DMAI/O operation that control ASIC 205 triggers, come with radio transceiver 305 in digital radio ASIC (DRA) communicate.
When needing, time slot manager 211 is access ARQ service module 220 and power control service module 221 in a manner described.The ARQ service module if any, is that the basis provides aerial error detection occurs, mistake recovery, error notification and prioritisation of messages with the specific ARQ mechanism of implementing in the aerial grouping.Power control service module 221 if any, serves as the transmission power level of the radio transceiver 305 of basis control subscriber station 301 with the power control mechanism of implementing in the grouping aloft.
The operation of an embodiment of software control system 201 shown in Figure 2 can make an explanation in conjunction with process chart shown in Figure 7.As shown in Figure 7, power up/reset process 705 start-up control processing 701, it generally includes, and for example, user's (that is, the mankind) promotes the eletric button that adds on the mobile phone, in case the power supply place in circuit, control and treatment 701 just enters the step 706 of testing oneself, and begins to power up at this and tests oneself.During the step 706 of testing oneself, move the check of one group of processor and peripheral components confidence level, with the integrality of the electric component of confirming system.If be free from mistakes as powering up the result who tests oneself, then control is sent to implementation and operation system (RTOS), and control and treatment continues to do initialization step 707.
After initialization step 707, OTA driver 210 blocks further operation, control and treatment 701 enters idle pulley (shown in the loop between step 710 and the step 711), and wherein software control system 201 grades are sent to a message of RTRX input mailbox 243 or a time slot incident that is sent by MSCA ISR 224.Software control system 201 can operate to the software loop that above two conditions are carried out poll continuously, perhaps preferably keeps idle fully by an interruption that stops the operation of permission and Wait-to-Restore." loop " 710 plans shown in the step 710 of Fig. 7 and 711 comprise these two embodiment at least.Therefore, as shown in Figure 7, the control and treatment 701 in the step 710 obtains and the relevant message of time slot incident that places slotted messages output work queue 213 by receiving the appearance that detects the time slot incident from the signal of MSCAISR 244.In case detect the time slot incident, OTA driver 210 is just handled the message of being lined up in slotted messages output work queue 213, shown in step 712, and finishes processing to these message.Usually this time slot event message will cause sending a message to slotted messages (SM) mailbox 242 that is associated with OTA state machine 252.In addition, OTA driver 210 is handled the message of queuing in slotted messages input queue 212, shown in the step 713 of control and treatment 701, until not remaining message or needing a message to requeue.In case finishing dealing with in the step 713, OTA 210 just blocks operation once more and turns back to idle pulley.
If do not detect the time slot incident in step 710, then control and treatment 701 enters step 711, detects in the RTRX input mailbox whether receive a message in this control and treatment 701.If then OTA driver 210 is attempted to finish information processing, if suitable, this sends a corresponding response.Yet the operation that comprises the data element that the software module called by the OTA driver with by various ISR 224,225,226 and 227 shares may need guaranteeing the adjustment of dedicated access.Should share the element access and remember the row arbitration into through simple non-RTOS signal post.The request that OTA driver 210 can not be handled fully is best ranks according to first in first out (FIFO) order.
In case receive a message in its slotted messages input queue 212, OTA driver 210 just calls suitable service module and carries out all operations that is associated with the request that does not need dedicated access.OTA driver 210 can, for example call wireless radio service module 217 intiating radios configurations and registration renewal to this radio configuration.OTA driver 210 calls renewal and the request DSP state of DSP object manager module 215 registrations to DSP control.OTA driver 210 calls time slot manager 211, by mode initialization, foundation, renewal, inquiry or the deletion time slot object 231 of following detailed description.After calling the service module that does not need dedicated access, OTA driver 210 is attempted the software section that obtains to be used for the correlation signal mark of these service modules or need dedicated access.If OTA210 is authorized to dedicated access, then uses suitable service module to finish, and send a corresponding response message to the specified mailbox that returns of this request to this requested service.If the dedicated access when OTA driver 210 can not needing obtain, this this request place time slot management input queue 212, be used for follow-up interruption Synchronous Processing.When waiting this situation and take place, OTA drives 210 and blocks operation once more, and turns back to idle pulley, waits the time slot incident to another input message of RTRX input mailbox 243.
In order to keep common duplexing communication channel, two time slot object 231 are set up.First time slot object 231 obtains the supply of single transmit time slot (thereby a single time slot mark is arranged), and second time slot object 231 obtains the supply of single receiving slot (thereby a single time slot mark is arranged).Which time slot position the time slot mark indication subscriber station 301 of first time slot object 23 1 will send at, and first time slot object 231 comprises the above-mentioned information of using in sending processing, contain the pointer to message to be sent.Which time slot position the time slot mark indication subscriber station 301 of second time slot object 231 will receive at, and second time slot object 231 comprises the above-mentioned information of utilizing in receiving processing, comprise the pointer to suitable reception message buffer.The time slot mark of first time slot object 231 comprises a subsequent timeslot pointer, and it will (when lacking other time slot object 231) be designated next effectively time slot to the receiving slot of second time slot object 231; Equally, the time slot mark of second time slot object 231 comprises a subsequent timeslot pointer, and it will be designated next effectively time slot to the sending time slots of first time slot object 231.
If subscriber station 301 sends signaling information (perhaps except the voice or data message that exchange) on common duplexing communication channel, then time slot object 231 can increase the function of determining logical signaling channel.New time slot object 231 will comprise one or more time slot marks, be used in particular for indicating the time slot that is used for sending or receiving signaling information.When increasing new time slot object 231, any other time slot marks in the existing time slot object 231 will be modified, and suitably upgrade their subsequent timeslot pointer, so that keep suitable ordering.
After time slot object 231 is established, exist, until being determined by time slot manager 211.Subscriber station 301 will be got in touch with each time frame in each time slot of being determined by the time slot mark of existing time slot object 231.Setting up time slot object 231 can only communicate by letter in a time slot of a time frame, then deletion.When this short life can appear at subscriber station 301 and for example sends a disconnected signaling message.For continuous call, time slot object can continue indefinitely.Time slot object 231 can dynamically be revised by time slot manager 211.Thereby time slot object 231 not only can be determined a plurality of time slot object in the time slot frame, and can change to another time frame to these time slot frames from a time frame change, thereby allow for example implementation of quick control business operation, as U.S. Patent application 09/122,565 described operations, this application was submitted on August 24th, 1998, and transferred assignee of the present invention, and this application is quoted as complete reference at this.
In a preferred embodiment, existing time slot object 231 definite time slots are handled continuously according to their relevant positions in time frame.At the end of handling a given time slot, the control of (by the subsequent timeslot pointer indication of current time slots mark) of subsequent timeslot and configuration parameter are loaded by time slot manager 211 gives hardware.The loading of new control and configuration parameter for example can cause radio transceiver 305 to be switched to sending mode from receiving mode, and vice versa, if desired, can also make the new spread spectrum code character of radio transceiver 305 loadings.Because the time spent of carrying of control and configuration parameter may surpass amount time rating, therefore in a preferred embodiment, each working time slot at the user-isolated station 301 of at least one time slot removes non-adjacent working time slot and has used identical control and configuration parameter, thereby do not need to load new argument.
An example of the time slot object 231 of the time slot relation of demonstration time frame occurs in Figure 19.In the example shown here, three time objects 1902,1903 and 1904 set are set up by time slot manager 211.Each time slot object 1902,1903 and 1904 comprises a time slot profile, and it comprises order data and configuration information, such as above-mentioned time slot type (send or receive), type of message (voice, signaling, data etc.) and out of Memory (such as transmission power level, ARQ information etc.).Each time slot object 1902,1903 and 1904 has a time slot mark at least, is used for the working time slot at identifying user station 301.First time slot object 1902 has a time slot mark 1911, and it is corresponding to the sending time slots #1 of time frame 1920, and the subsequent timeslot of indication (by the subsequent timeslot pointer) subscriber station 301 is time slot #5.Second time slot object 1903 has a time slot mark 1912, and it is corresponding to receiving slot #9, and the subsequent timeslot of indication (by the subsequent timeslot pointer) subscriber station 301 is time slot #12.According to they time slot profiles separately, for speech business is provided with first and second time slot object 1902,1093.In a kind of situation, for example, according to the frame structure of Fig. 4, Fig. 5 and Fig. 6, first and second time slot object 1902,1903 can comprise the duplex voice channel jointly.The 3rd time slot object 1904 has time slot mark 1913,1914 and 1915.As shown in the figure, its first time slot mark 1913 is corresponding with receiving slot #5; The second time slot mark 1914 is corresponding with receiving slot #12; The 3rd time slot mark 1915 is corresponding with receiving slot #14.In a kind of situation, three time slot marks 1913,1914 of the 3rd time slot object and 1915 common definition are used for the received communication channel of the signaling data of subscriber station 301.If desired, the 4th time slot object can be added the set of time slot object, with the transmission communication channel of definition subscriber signaling data.
The following describes the details of optimum operation, sequential and the ordering of the various piece of software control system 201.
In a kind of situation, OTA driver 210 participates in the operation control of software control system 201.The initialization of OTA driver 210 executive software control system 210, monitor RTRX input mailbox 243, send request, monitor slotted messages input queue 212 and slotted messages output work queue 213 to service module, handle the time slot incident and answer RTRX output mailbox 241.
When the time slot event handling, OTA driver 210 is preferably in and sends the processing of finishing before the next time slot incident the time slot incident.Time slot manager 211 can by guarantee at least one not working time slot (in one embodiment, being 1.25 microseconds for example) appear at and control this ordering between the working time slot indirectly.
Following table 2-1 has listed some to the input of OTA driver 210 and their source, and relevant each note.
Table 2-1
| Project | The source | Function or note |
| The mailbox incident | RTOS | The signal that when one or more message reside in RTRX input mailbox, sends. |
| External message | The input mailbox | Check the explanation of handling about external message. |
| The time slot incident | MSCA ISR | The signal that sends when the ISR time slot is finished dealing with. |
| Slotted messages input queue message | Self | The external message of queuing. |
| Slotted messages output work queue message | The time slot manager | The relevant slotted messages of queuing. |
| Wireless request is answered | Wireless traffic | Initialization and update mode. |
| DSP asks to answer | The DSP Object Manager | Update mode and inquiry message. |
| The time slot request is answered | The time slot manager | Initialization is set up, and upgrades inquiry and deletion state. |
In a preferred embodiment, the following RTRX input of OTA driver 210 responses mailbox message: RTRX configuring request, RTRX reset request, link request, radio configuration request and DSP update request.In one embodiment, provide OTA driver 210 how to answer the brief description of these RTRX input mailbox message in the following manner.
When OTA driver 210 receives RTRX configuration request message in the RTRX input mailbox message 261, carry out following treatment step:
1, the RTRX configuration parameter is updated to the ginseng of RTRX configuration request message appointment
Number.
2, the mailbox that returns of appointment sends one in the RTRX configuration request message
RTRX configuration response message.
RTRX configuration request message back is the RTRX reset request that newly disposes.
When OTA driver 210 receives RTRX reset request message in the RTRX input mailbox message 261, carry out following treatment step:
1, closes software control system 201.
2, reinitialize software control system 201 according to aforesaid initialization step.
3, the mailbox transmission RTRX that returns to the appointment of RTRX reset request message resets
Response message.
When OTA driver 210 receives link request message in the RTRX input mailbox 261, carry out following treatment step:
1, by following each link request of every processing:
A, request for building link-the call time slot that time slot manager 211 is set up appointment.
B, link circuit deleting request-call time slot manager 211 to delete time slots.
C, link inquiry ask-call time slot manager 211 to obtain last the joining of time slot
Put snapshot with state.
D, link update request-call time slot manager 211 to reconfigure by this request
The time slot of appointment.
If 2 time slot managers 211 can not full service request (because potential interruption
Access interference), OTA driver 210 is in slotted messages input queue 212
To this request queue.
If 3 these requests are successfully served, then OTA driver 210 please to link
Ask the link response that returns mailbox transmission association of appointment in the message.
When OTA driver 210 receives radio configuration request message in the RTRX input mailbox 261, carry out following treatment step:
1, calls the nothing that wireless radio service module 217 is upgraded the appointment of radio configuration request message
The line configuration.After this, advance in the lock in time that time slot manager 211 is determined
The configuration that row is new.
2, the mailbox that returns of appointment sends radio configuration in the radio configuration request message
Response message.
When OTA driver 210 receives DSP update inquiry information in the RTRX input mailbox 261, carry out following treatment step:
1, calls DSP Object Manager 215 and upgrade DSP update inquiry information appointments
2, sending the DSP register to the mailbox that is associated with DSP object 216 upgrades
Acknowledge message.
Except that RTRX input mailbox message, OTA driver 210 is also handled the message that receives in slotted messages input queue 212.For example, when OTA driver 210 received time slot request message in the slotted messages queuing 212, this driver was carried out following treatment step:
1, by each time slot request message of following every processing:
A, time slot are set up and are asked-call 211 foundation of time slot manager to be asked by time slot foundation
Ask the time slot of appointment.
B, time slot removal request-call time slot manager 211 to delete these time slots.
The inquiry of c, time slot ask-call the time slot manager obtain time slot last configuration and
A snapshot of state.
D, time slot update request-the call time slot of time slot manager configuration appointment.
If 2 time slot managers 211 can not full service request, then OTA driver
210 can requeue to this request in time slot input queue 212.
If 3 these requests are successfully received, then OTA driver 210 please to time slot
Ask the mailbox that returns of appointment in the message to send the link response message that is associated.
In addition, OTA driver 210 is handled the message of queuing in the slotted messages queuing 213.For example, when OTA driver 210 was received time slot responses message in the time receiving crack message output work queue 213, then this driver was carried out following treatment step:
1, by each time slot responses message of following every execution:
What a, time slot set up response-to this request appointment returns chain of mailbox transmission
Response message is set up on the road.
The deletion of b, time slot responds-calls time slot manager 211 and carries out to this time slot
Whole deletion action, the mailbox that returns of appointment sends in this request then
A link circuit deleting response message.
C, time slot query-response-call time slot manager 211 to obtain joining at last of time slot
Put the snapshot with state, then in this request appointment return mailbox
Send a link inquiry response messages.
What d, time slot upgraded the appointment of response-in this request returns one of mailbox transmission
Link upgrades response message.
When OTA driver 210 was received a time slot responses in the time receiving crack message output work queue 213 and finished message, then this driver was carried out following treatment step:
If 1 time slot manager, 211 indication link event Indication messages should be issued
The time, 210 of OTA drivers:
A, the last configuration of calling time slot manager 211 acquisition time slots and the wink of state
Picture.
B, send a link event to the mailbox that is associated with time slot object 231
Indication message.
If the DSP object 216 that 215 indications of 2 DSP Object Managers are associated
State is updated, 210 of OTA drivers:
A, send a DSP to the mailbox that is associated with DSP object 216 and deposit
Device upgrades Indication message.
In case detect a time slot incident, OTA driver 210 is just according to the specified mode of above-mentioned treatment step, finish processing to all message of being lined up in the slotted messages output work queue 213, finish processing according to the specified mode of above-mentioned treatment step then, perhaps until other is former thereby force a message is requeued because of access conflict or some to the message of all queuings in the slotted messages queuing 212.
If detect a mistake during operation, 210 of OTA drivers are exported mailbox 241 to RTRX and are sent an error Indication message.The example of error condition comprises a unacknowledged external message that receives from RTRX output mailbox 243, perhaps a message unconfirmed that receives from slotted messages input queue 212 or slotted messages output work queue 213.
Following table 2-2 has listed some output and their target of OTA driver 210, and about the note of some OTA driver output.
Table 2-2
| Project | Target | Note |
| External message | The output mailbox | |
| External message | The state machine mailbox | |
| External message | The DSP mailbox | |
| Slotted messages input queue message | Self or time slot manager | The external message of queuing |
| Wireless request | Wireless radio service | Initialization and renewal |
| The DSP request | The DSP Object Manager | Upgrade and inquiry |
| The time slot request | The time slot manager | Initialization is set up, and upgrades inquiry and deletion |
Following table 3-1 has listed the main input of time slot manager 211 and their information source and note.
Table 3-1
| Project | Information source | Note |
| The time slot request | Any | Initialization is set up, and upgrades inquiry, deletion and Interrupt Process request |
| Time slot management input queue message | The OTA driver | The time slot request of queuing |
| The wireless request response | Wireless radio service | Solicited status, RSSL |
| DSP asks response | The DSP Object Manager | Init state, DSP control |
| ARQ asks response | ?????ARQ | ARQ state and message sequence number |
| The response of power control request | Power control | Power level is recommended |
| The PECCx event counter | ????PEC?ISP | PEC End Event counter |
Following table 3-2 shows in a preferred embodiment the data element that is used by time slot manager 211, and to each brief description
Table 3-2
| Element | Note |
| The time slot tabulation | The static list of structure of time slot |
| Current time slots | Time slot tabulation to the work at present time slot is quoted |
| Time slot management input queue | The request about time slot of queuing |
| Time slot management output work queue | The response and the incident about time slot of queuing |
Following table 3-3 has described a structure of using in one embodiment, comprises the configuration that contains a time slot and the time slot manager 211 of state.
Table 3-3
| Element | Note |
| The time slot mark symbol | Unique time slot mark symbol |
| The time slot type | The current time slots type |
| Time slot state | The current time slots state |
| Routing configuration | The addressing information that is used for the link event Indication message of this time slot |
| Receive configuration | Current reception configuration |
| Receive config update | New reception configuration |
| Accepting state | Current accepting state |
| Send configuration | Current transmission configuration |
| Send config update | New transmission configuration |
| Transmit status | Current transmit status |
| The radio configuration identifier | Current wireless configuration reference |
| Wireless status | The current wireless state |
| The DSP identifier | Current DSP object reference |
| The FDD direction | Current RX/TX direction |
| The ARQ state | Current ARQ state |
| The TX power rating | Current TX power level state |
| The PECCx event counter | The event counter value of up-to-date PECC |
| The subsequent timeslot comparative counting | The relative number of time slot to subsequent timeslot |
| The subsequent timeslot reference | Pointer to the structure of time slot of subsequent timeslot |
In a kind of situation, time slot manager 211 comprises a service module that is used for OTA driver 210 and time slot ISR, can be called according to request when needing.Yet time slot manager 211 can submit to the special sequential demand of for example being forced by Interrupt Process operation sequence (for example ISR 224,225 etc.) in some cases.The sequential of various operations and ordering may need (specifically) consideration signaling traffic outlet and speech business to handle.This sequential and ordering consider and can make an explanation with reference to figure 8, Fig. 9, Figure 10 and Figure 11 that wherein Fig. 8 and Fig. 9 relate to the signaling traffic processing, and Figure 10 and Figure 11 relate to the speech business processing.
Fig. 8 shows the signaling traffic path that adapts with embodiment described herein, and Fig. 9 shows data path and the ordering that is used for the efficient signaling business time-slot.Although Fig. 8 shows microphone 827, loud speaker 828, CODEC 826 and DSP/ sound synthesizer 825, in a preferred embodiment, these parts are not used as the part in signaling traffic path.But, SRAM transmission buffer 810 shown in Figure 8, RSAM reception buffer 860, control ASIC 805 and digital radio ASIC (DRA) the 820th, the parts that utilize in the signaling traffic path.SRAM transmission buffer 810 comprises storage area, is used for a subscriber station head 813, D channel information 812, carrier data 811 and DSP/ sound synthesizer state information 814.SRAM reception buffer 860 comprises storage area, is used for a base station head 863, D channel information 862, carrier data 861 and DSP/ sound synthesizer control information 864.
For from being used for one of signaling traffic and sending sequence of subscriber station 301, the following step is according to the appearance that illustrates in sequential/ordering relation shown in Figure 9:
1, a time slot (for example, shown in Figure 4 time slot 1) about subscriber station M9
The user send during the part 902, utilize control to send of byte number
Peripheral event controller counter is with subscriber station head 813, D channel information
812 and carrier data 811 through and wireless transmission DMA data transmit task
Peripheral event controller (PEC) channel of 235 associations sends slow from SRAM
Be sent to DRA 820 towards device 810.
When 2, above-mentioned information sends, the user send part 902 ending or before, produce
Give birth to wireless transmission DMA data and transmit in the related transmission end of task 235
Disconnected.
3, wireless transmission DMA ISR calls to send and finishes (EOTX) ISR 227, sends out
Send a software to capture, capture ISR 225 thereby call software.
4, software is captured ISR225 and is called time slot manager 211, is used for " being sent completely "
Handle.
5, the wireless receiving frequency data are through transmitting task with radio configuration DMA data
A PEC channel of 223 associations is sent to DRA 820 from SRAM 821.
6, when the radio configuration data have been transmitted, take place and radio configuration DMA number
One that reportedly send task 223 to be associated is transmitted end interrupt.
Radio transceiver 305 is readjusted its frequency synthesizer subsequently, adjusts to receive frequency.
Be sent to the receiving sequence of subscriber station 301 for signaling traffic, have following steps to take place, shown in the illustrating in sequential/sequence relation as shown in Figure 9:
1, at the base of a time slot (for example, shown in Figure 4 time slot 9) about the base station
Standing sends during the part 952, utilizes control to send a periphery of byte number
The event controller counter is with base station head 863, D channel information 862 and
The PEC channel of connection is sent to SRAM reception buffer 860 from DRA 820.
2, transmit one that task 237 is associated through comparing the DMA data with RX
The PEC channel will be used for the comparing data (that is order/mask comparison, of received frame
Operation) is sent to control ASIC 805 from SRAM commands buffer 1704.
When 3, above-mentioned information sends, the base station send part 952 ending or before, produce
Give birth to RX relatively the DMA data transmit in the related transmission end of task 237
Disconnected.
4, control ASIC 805 triggers " receive and relatively a finish " interruption.
5, MSCA ISR 224 calls time slot manager 211 and carries out " receive and relatively finish "
Handle.
6, generation and wireless receiving DMA data transmit task 238 related transmission and finish
Interrupt.
7, control ASIC 805 triggers one " received frame is finished " interruption.
8, MSCA ISR 224 calls time slot manager 211 and carries out " received frame is finished "
Handle.
9, wireless receiving frequency data process and radio configuration DMA data are transmitted task
A PEC channel of 223 associations is sent to DRA 820 from SRAM 821.
10, when the radio configuration data have been transmitted, take place and radio configuration DMA number
One that reportedly send task 223 to be associated is transmitted end interrupt.
Figure 10 shows the speech business path that adapts with an embodiment described here, and Figure 11 shows data path and the ordering that is used for the efficient voice business time-slot.Figure 10 shows microphone 1027 and the loud speaker 1028 that is connected with CODEC 1026, and wherein CODEC 1026 connects DSP/ sound synthesizer 1025.As shown in figure 10, DSP/ sound synthesizer 1025 connects control ASIC 1005, and ASIC 1005 is connected with digital radio ASIC (DRA) 1020 with SRAM 1021 (comprising a SRAM transmission buffer 1010 and a SRAM reception buffer 1060).Similar with Fig. 8, SRAM sends transmission buffer 1010 and comprises the storage area that is used for user header label 1013, D channel information 1012, carrier data 1011 and DSP/ sound synthesizer state information 1014.SRAM reception buffer 1060 comprises the storage area that is used for base station head 1063, D channel information 1062, carrier data 1061 and DSP/ sound synthesizer control information 1064.
For transmission sequence, there is the following step to take place, shown in sequential/sequence relation as shown in Figure 11 from the speech business of subscriber station 301.
1, a time slot (for example, shown in Figure 4 time slot 1) about subscriber station M9
The user send during the part 902, utilize control to send of byte number
Peripheral event controller counter is with subscriber station head 1013, D channel information
1012 and carrier data 1011 appoint through transmitting with wireless transmission DMA data
The be engaged in PEC channel of 235 associations is sent to from SRAM transmission buffer 1010
DRA?1020。
When 2, above-mentioned information sends, the user send part 1102 ending or before,
Produce a transmission related with wireless transmission DMA data transmission task 235
End interrupt.
3, wireless transmission DMA ISR calls to send and finishes (EOTX) ISR 227, sends out
Go out a software and capture, capture ISR 225 thereby call software.
4, software is captured ISR225 and is called time slot manager 211, is used for " being sent completely "
Handle.
5, the wireless receiving frequency data are through transmitting task with radio configuration DMA data
A PEC channel of 223 associations is sent to DRA from SRAM 1021
1020。
6, when the radio configuration data have been transmitted, take place and radio configuration DMA number
One that reportedly send task 223 to be associated is transmitted end interrupt.
More than the step of the information of transmission speech business is identical from the step that subscriber station 301 sends signaling informations with aforesaid execution basically.
Be sent to the receiving sequence of subscriber station 301 for speech business, have following steps to take place, shown in the illustrating in sequential/sequence relation as shown in Figure 11:
1, at the base of a time slot (for example, shown in Figure 4 time slot 9) about the base station
Stand and send before the part 1152, DSP/ sound synthesizer state information 1014
Transmit task 239 with carrier data 1011 through exporting the DMA data with DSP
A related PEC channel is sent to from DSP/ sound synthesizer 1025
2, then, with DSP control data 1064 processes and DSP output DMA data
A PEC channel of transmission task 236 associations is from the SRAM reception buffer
1060 are sent to DSP/ sound synthesizer 1025.
When 3, above-mentioned information sends, the base station send part 1152 beginning or before,
Produce a transmission related with DSP input DMA data transmission task 236
End interrupt.
4, during the base station sends part 1152, outside the use control byte transmission number
Enclose the event controller counter, through transmitting task 238 with reception DMA data
Related PEC channel is with base station head 1063, D channel information 1062 and
5, the comparing data of received frame (that is, the result of order/mask compare operation), warp
Cross with RX relatively the DMA data transmit a related PEC letter of task 237
The road is sent to control ASIC 1005 from SRAM commands buffer 1704.
When 6, above-mentioned information is sent out, the base station send part 152 ending or before,
Produce with RX relatively the DMA data transmit the related transmission end of task 237
Interrupt.
7, control ASIC 1005 triggers " receive and relatively a finish " interruption.
8, MSCA ISR 224 calls time slot manager 211 and carries out " receive and relatively finish "
Handle.
9, generation transmits the transmission knot that task 239 is associated with DSP output DMA data
Intrafascicular disconnected.
10, generation and wireless receiving DMA data transmit task 238 related transmission and finish
Interrupt.
11, control ASIC 1005 triggers one " received frame is finished " interruption.
12, MSCA ISR 224 calls time slot manager 211 and carries out " received frame is finished "
Handle.
13, wireless receiving frequency data process and radio configuration DMA data are transmitted task
A PEC channel of 223 associations is sent to DRA from SRAM 1021
1020。
14, when the radio configuration data have been transmitted, take place and radio configuration DMA number
One that reportedly send task 223 to be associated is transmitted end interrupt.
The step 4 of above-mentioned receiving speech information is to 14 basically with to finish reception identical from the step of the signaling information of subscriber station 301.
Except the transmission and reception of assisting signaling information and voice/data information, time slot manager 211 also provides access control to time slot object 231.Specifically, in a preferred embodiment, time slot manager 211 provides the signal mark of a control to time slot object 231 dedicated access.Except between OTA driver 210 and ISR handle, providing the dedicated access, the signal mark also guarantee the configuration of time slot object 231 finish after (that is, after the hardware configuration) will no longer change.Have suitable resolution, provide by a timer 2 29 such as the signal mark of a microsecond resolution.Timer 2 29 preferably is implemented as a single step timer.
In operation, time slot manager 211 is removed this signal mark in the slot synchronization time (transition period between time slot 1202), with period of the numerical value defined that allows in by timer 2 29, to pack into to time slot object 231 accesses; During timer expiration, this signal mark is set, to forbid access time slot object 231.This this operation shown in Figure 12, wherein show a time frame (, not being marked on the time slot on different base station and the user station frequency band among Figure 12) that is divided into a series of time slots 1202 for for simplicity.As shown in figure 12, begin during the signal post section of clocking 1220 to be provided with.Time slot manager 211 is removed this signal mark at time point 1205, and timer 2 29 this moment (loading after the reflection suitable count value of expection access time) starts.In the period shown in Figure 12 1221, effective to time slot object 231 accesses, expire on later time point 1206 until timer 2 29.Then, signal is marked at periods 1222 maintenance and is provided with, and does not allow access time slot object 231 during this period.At next time point 1210, time slot manager 211 clear signal marks, thus allow access time slot object 231.During the period 1223, allow access, the time point 1211 when timer 2 29 expirations.The signal mark turns back to its state that is provided with then.In addition, as shown in figure 12, each setting of signal mark or removing all are to finish the transition period (that is slot synchronization) between time slot 1202.
As mentioned above, time slot manager 211 preferably serves as a service module for OTA driver 210, can call its initialization, foundation, renewal, inquiry or delete a time slot object.Time slot manager 211 is handled each the time slot request that receives from OTA driver 210 respectively, and the response (for example, success is failed, and does not finish) to association is ranked in time slot output message queuing 213.Illustrate the details of explanation according to a preferred embodiment below about these processing.
For the initialization of time slot object 231, time slot manager 211 is carried out several steps.At first time slot manager 211 is installed timer 2 26.Then, the time slot manager carries out initialization process to time slot object 231, slotted messages input queue 212, slotted messages output work queue 213 and DSP object 216.At last, time slot manager 211 activates peripheral event controller (PEC) interruption of relevant time slot object DSP operation sequence.
In order to set up time slot object 231, time slot manager 211 at first attempts to distribute a time slot object 231.If should distribute attempt unsuccessful, this returns a malfunction designator.In addition, according to the appointment initialization of this request and time slot object of configuration.After this, if, then return a unfinished state designator if access time slot object 231 is not allowed to (owing to the reason of signal mark).In addition, this time slot object 231 is inserted in the time slot tabulation.If there is not other effective time slot, calls wireless radio service module 217 so and carry out any uncompleted renewal and finish wireless initialization.Subsequently, time slot manager 211 is carried out " receive and be provided with " and handled, and is as described below.At last, activate by or the interruption of the relevant time slot that produces by control ASIC 205.After this, MSCA ISR 224 will be by a normal state down trigger when successfully receiving first.Time slot manager 211 returns a success status designator then.
In order to delete time slot object 231, time slot manager 211 at first determines whether to allow access time slot object 231 (by the indication of signal mark).If do not allow access, then return a unfinished state designator.In addition, from the time slot tabulation, eliminate this time slot object 231.If there is not other effective time slot, then activate by or the interruption of the relevant time slot that produces by control ASIC 205, and call wireless radio service module 217 and radio transceiver 305 reset to its idle condition.Accepting state machine among the control ASIC 205 is reset.Then, go to distribute the time slot object of from the time slot tabulation, eliminating 231, and return a success status designator.
In order to upgrade time slot object 231, time slot manager 211 is at first preserved the renewal configuration of appointment.If do not allow access time slot object 231, then return a unfinished state designator.In addition, upgrade configuration, " carrying out " config update by the effective configuration that is used for time slot object 231 being transformed into preserve.If the time slot object of upgrading 231 is current to be effectively, time slot manager 211 is carried out " receive and be provided with " according to the mode that describes in detail below or " send and be provided with " handles in due course so.At last, return a success status designator.
In order to inquire a time slot object 231, time slot manager 211 allows access time slot object 231 (by the indication of signal mark) when at first determining.If do not allow access, this returns a unfinished state designator.In addition, the current configuration and the current state of time slot manager 211 access time slot object.Then, time slot manager 211 returns a completion status designator.
Except handling time slot object 231, time slot manager 211 also is called in Interrupt Process.For example, time slot manager 211 is relatively finished interruption, received frame a reception and is finished and interrupt or a transmit frame is finished to carry out when interrupting taking place and handled.
When the interruption generation was relatively finished in reception, time slot manager 211 stopped single step timer 229.Then, check is from header checksum field (HCF) state of the accepting state register of control ASIC 205.If the HCF state is " good ", then the time slot manager extracts the header field that comprises packet type, channel usage, subsequent timeslot pointer, ARQ and power.On the other hand, if the HCF state is " bad ", then the OTA header field is set to following default value: grouping is set to the unknown; Channel usage is set to the unknown; The subsequent timeslot pointer is set to indication " subsequent frame of same time slot "; ARQ is set to indication and does not change; Power is set to indication and does not change.Time slot manager 211 upgrades subsequently and comprise relatively " accepting state " that be used for current time slots of state (extracting) of HCF state, packet type, channel usage and RX from the normal state register of control ASIC 205.At last, time slot controller 211 loads the time slot mapping pointer register of control ASIC 205, with the subsequent timeslot of selective reception.
When a transmit frame was finished the interruption generation, time slot manager 211 was provided with reception in due course and sends next time slot object 231, will elaborate below.
When received frame was finished the interruption generation, time slot manager 211 was at first checked frame check word (FCW) state from the grouping of the accepting state register of control ASIC 205.If " good " then time slot manager 211 determine whether to carry out a trial to a slot synchronization during FCW state, if then determine whether to have realized synchronously.If synchronous, then time slot manager 211 is removed wireless synchronization control.Time slot manager 211 is checked subsequently and is received relatively state, if during this state " good ", the time slot object that then resets is relatively controlled (that is, order/mask template operation), so that only compare with the OTA header field with " freely " packet type.Time slot controller 211 calls ARQ service module 220 subsequently and carries out the ARQ processing, and the accepting state of message is set.Time slot manager 211 is determined the transmit status of message subsequently.If ARQ transmits, then the message transmit status is " good ", and time slot manager 211 is transformed into an acquiescence transmission message.Yet, if ARQ failure, and if predetermined number of retries use up, the message transmit status is converted into " bad ".Time slot manager 211 is transformed into an acquiescence subsequently and sends message.If the ARQ failure, but predetermined number of retries is also unexhausted, and then the message transmit status is switched to (or support) " the unknown ".Current transmission message is that follow-up transmission again keeps.
By calling the next transmission power level that sends that is used on power control module 221 definite current time slots, time slot manager 211 continues on for receiving the Interrupt Process of relatively finishing interruption.Time slot manager 211 is read the RSSI value subsequently from the RSSI register of control ASIC 205.Subsequently, according to following detailed description, time slot manager 211 is handled the message in the time slot input message queueing 212.If this time slot is in the speech business pattern, then time slot manager 211 copies to related DSP object 216 to DSP/ sound synthesizer status data.Received frame is finished the final step of interrupting and carrying out in response, and according to following detailed description, time slot manager 211 receives or sends for next time slot object 231 is provided with in due course.
For reception step is set, time slot manager 211 at first determines whether any uncertain radio configuration renewal, if having, then calls wireless radio service module 217 and upgrades.Time slot manager 211 also calls wireless radio service module 217 configuration wireless receiving frequencies.Time slot manager 211 activates wireless receiving DMA path subsequently, and forbids the wireless transmission operation sequence.Time slot manager 211 is provided with wireless synchronization control by following mode.(that is, synchronously), 211 of time slot managers are provided with wireless synchronization control, the receiving slot that " good " (that is zero defect) limits with first synchronously in the processing of obtaining a time slot if subscriber station 301 is in.If subscriber station 301 be in numerical signal processor (DSP) (for example, DSP/ sound synthesizer 1510 among Figure 15) in the synchronous processing, 211 of time slot managers are provided with wireless synchronization control, a DSP lock-out pulse that is used for current time slots with generation, for example start DSP (for example, the DSP/ sound synthesizer 1510) subsequently by the general register among the control ASIC 205 or 1591.If these simultaneous operation neither ones are underway, then time slot manager 211 is removed wireless synchronization control.
As the next procedure that receives set handling, time slot manager 211 is provided for the reception data path of time slot.In this, time slot manager 211 is provided with and activates with reception and compares a peripheral time controller (PEC) channel that DMA data transmission task 237 is associated, thereby allow direct memory access (DMA) (DMA) operation, comparing data is sent to the order comparand register of controlling the ASIC 205 from memory (for example, from SRAM commands buffer 1704 shown in Figure 17).Time slot manager 211 is provided with and activates with reception and compares the PEC channel that DMA data transmission task 238 is associated, thereby startup dma operation, with data from the reception sources register transfer of control the ASIC 205 to receiving data storage (for example, the SRAM reception buffer 1706).If time slot is used to speech business, then time slot manager 211 copies to DSP control storage (for example, shown in Figure 180 sound synthesizer control field 1805) to DSP/ sound synthesizer control data from the DSP object 216 that is associated.Time slot manager 211 is provided with subsequently and activation transmits the PEC channel that task 236 is associated with DSP input DMA data, thereby startup dma operation, data are sent to a DSP data/control register of controlling among the ASIC 205 from memory (for example, the SRAM reception buffer 1706).
As the next procedure that receives in the set handling, time slot manager 211 is provided with the pre-transmission data path of a time slot.In this, 211 settings of time slot manager and activation transmit the PEC channel that task 239 is associated with DSP output DMA data, thereby the startup dma operation is sent to memory (for example, the SRAM transmission buffer 1707) with the DSP source register of data from control ASIC 205.Time slot manager 211 is provided with the selection of a data notice according to the business model (that is, signaling or voice) of time slot in control ASIC 205.Then, time slot manager 211 starts single step timer 229.If subscriber station 301 is being attempted obtaining the synchronous of this time slot, then it can make interruption not take place; Therefore, as fail-safe mechanism, timer 2 26 is configured to handle queuing message when timer 2 29 expirations.On the other hand, if subscriber station 302 is synchronous to current time slots, then interrupts and to take place; Under a such situation, time slot manager 211 configuration timer ISR 226 make it that time slot object access signal mark is set when expiration, thereby stop access time slot object 231 when timer 2 26 expirations.At last, time slot manager 211 loads compare counter register in control ASIC 205, so that be provided with and starting command/mask template operation when receiving received frame.
For sending set handling, time slot manager 211 at first determines whether any uncertain radio configuration renewal, if having, then calls wireless radio service module 217 and upgrades.Time slot manager 211 also calls wireless radio service module 217 configuration wireless transmission frequencies.Time slot manager 211 is forbidden wireless receiving DMA path, activates the wireless transmission operation sequence, and removes wireless synchronization control.Time slot manager 211 is provided with OTA head (for example, the subscriber station head 813 among Fig. 8, or the subscriber station head 1013 among Figure 10, or the subscriber station head 1808 among Figure 18, this depends on what send is the modern service message of bearer services message or letter) subsequently.For example, time slot manager 211 can be provided with packet type field according to the appointment that sends configuration data, and the ARQ field that ARQ service module 220 is determined perhaps is set.Then, time slot manager 211 is provided for the transmission data path of time slot.211 settings of time slot manager and activation transmit the PEC channel that task 235 is associated with wireless transmission DMA data, thereby activation dma operation, data are sent to the transmission destination register of controlling among the ASIC 205 from sending data storage (for example, the SRAM transmission buffer 1707).Time slot manager 211 starts single step timer 229 and configuration timer ISR226, so that time slot object access signal mark is set during expiration, thereby stops access time slot object 231 when single step timer 229 expirations.At last, time slot manager 211 calls wireless radio service module 217 and loads the expection transmission power level.
During single step timer 229 expirations, time slot manager 211 is just carried out some and is handled operation.Time slot manager 211 is handled the message of queuing in slotted messages input queue 212, disposes timer ISR 226 then, makes it handle the message of queuing when single step timer 229 expirations.
Following table 3-4 has summarized the main output of time slot manager 211 and their target, and note.
Table 3-4
| Project | Target | Note |
| Time slot request response | Any one | Initialization is set up, and upgrades inquiry, deletion and Interrupt Process solicited status |
| Slotted messages output work queue message | OTA drives | The slotted messages of queuing |
| Wireless request | Wireless radio service | Upgrade and the RSSI request |
| The DSP request | The DSP object message | Initialization and update request |
| The ARQ request | ??????ARQ | ARQ state and message sequence are counted request |
| The power control request | Power control | The power control request |
To describe the operation that starts with MSCA ISR224 below in detail about each other components of system as directed of software control system shown in Figure 2 201.MSCA ISR 224 handles the normal state that is produced by control ASIC 205 and interrupts.Detect the interruption of relevant non-time slot, then, signal from the outside through the external event interface.The interruption of relevant non-time slot can comprise, for example, SIM TX mistake (that is SIM transmit port mistake), pattern change (that is, the port connector conversion takes place or is detected) and KeyEvent (that is, press and discharge one or more keyboards).The interruption of relevant time slot is handled by the associative operation program of calling time slot manager 211.The interruption of relevant time slot comprises that for example, RX relatively finishes (that is, being that a time slot is finished reception order/mask template operation) and the RX frame is finished (that is the receiving unit of, having finished a time slot).When subscriber station 301 receives data about effective time slot, produce time slot and interrupt.MSCA ISR 224 preferably can utilize the ISR service of real time operating system, the words of its operation sequence if desired.
When calling, MSCA ISR 224 reads MSCA normal state register (GSR), with the reason of determining to interrupt.Then, MSCA ISR 224 beginnings are this break in service according to its information source.For example, relatively finish interruption for RX, MSCA ISR 224 can call time slot manager 211 execution RX and relatively finish processing.Finish interruption for the RX frame, MSCAISR 224 can call time slot manager 211 execution RX frames and finish processing, sends a time slot event signal then.
For sequential and the ordering interrupted, the interruption of the relevant non-time slot of being handled by MSCA ISR 224 is asynchronous with aperiodic.On the other hand, the interruption about time slot is and slot synchronization that this can make an explanation with example shown in Figure 13.Here, time slot 1302 is divided into a subscriber station transmit frame 1303 and a base station transmit frame 1305.Subscriber station transmit frame 1303 and base station transmit frame 1305 are isolated by a protection time slot and steering gap (concentrating expression by the gap among Figure 13 1304).Subscriber station transmit frame 1303 starts from after the variable radio gap 1310 of starting point 1321 appearance of time slot 1302.Second steering gap 1311 occurs between the terminal point 1322 (that is the starting point of next time slot 1352) of 1305 endings of base station transmit frame and time slot 1302.
In example shown in Figure 13, during first period, RX relatively finishes and interrupts taking place, as the other places here are described.Therefore the processing of the head in the length reflection base station message of first period 1316, depends on the length of head in the message of base station to a certain extent.RX during period 1361 relatively finishes interrupt call MSCA ISR 224.During second period 1362, the Interrupt Process that response RX relatively finishes interruption takes place, and finishes before being preferably in the end of base station transmit frame 1305.After base station transmit frame 1305 finishes, after this fixing period is preferably arranged, a RX frame relatively interrupts occurring on the point 1363 of Figure 13.The processing that response RX frame relatively interrupts occurred on the period 1364, and finished before being preferably in next time slot 1352.Yet if next time slot 1352 is not used, processing can continue, and finishes up to next time slot 1352.
Following table 4-1 has summarized the main output of MSCA 224 and their target, and note.
Table 4-1
| Project | Target | Note |
| The time slot request | The time slot manager | The Interrupt Process request |
| The time slot incident | The OTA driver | The signal that the ISR time slot sends when finishing dealing with |
| KeyEvent | Outside | The signal that button is pressed or sent when discharging |
| Pattern changes incident | Outside | The signal that port connector sends when changing |
| The SIMTX error event | Outside | The signal that the SIM port sends when sending mistake |
Software is captured ISR 225 and is handled the software interrupt (capturing) that is produced by software control system 201.Software is captured ISR 225 calls time slot manager 211 based on the information source of interrupting proper handling program.In the meaning of freely using the real time operating system service that is used for Interrupt Process, software is captured preferably " co-operate " ISR of ISR 225.The purpose that software is captured ISR225 is that non-co-operate ISR is risen to common ISR.
Software is captured can be by comprising that the TX frame is finished or any one of the variety of event of single step timer expiration touched.It can also call by for example sending end (EOTX) ISR 227 or timer ISR 226.
Send the interruption that produces when the subscriber station transmit frame that finishes in time slot of (EOTX) ISR 227 processing is finished.EOTX ISR 227 can be called by the peripheral event controller ISR of a wireless transmission DMA.EOTX ISR 227 is provided with a mark and produces a software and captures, and sends end process to carry out.Transmit when finishing from memory to wireless DMA, wireless transmission DMA PEC ISR calls EOTX ISR 227.In certain embodiments, EOTX ISR 227 can be non-co-operate ISR, therefore can not use real time operating system (RTOS) service.Yet EOTX ISR 227 can call software and capture ISR 225, to allow this service of access.
The interruption that timer ISR 226 produces when handling single step timer 229 expirations.Timer ISR 226 can upgrade a signal mark or a mark is set, and produces one then and control is sent to software captures the software of ISR 225 and capture, and handles to carry out timer expiration.In certain embodiments, timer ISR 226 can be non-co-operate ISR, therefore, does not have the assistance of software I SR225 just can not use the real time operating system service.
Peripheral event controller (PEC) ISR handles the controlled DMA of PEC and transmits the interruption that produces when finishing.PEC ISR is triggered when the DMA I/O of the channel request of control ASIC 205 through being associated finishes.Usually, when calling, PEC ISR upgrades a counter, perhaps in other words calls an operation sequence, as previously explained shown in the example.Following table 5-1 has summarized the main input of PEC ISR and their source, and note.
Table 5-1
| Project | The source | Note |
| EX01N interrupts | MSCA | When from memory when the transmission that sends destination register is finished, the signal that sends. |
| EX11N interrupts | MSCA | When the transmission from the reception sources register to memory is finished, the signal that sends. |
| EX21N interrupts | MSCA | When the transmission from the DSP source register to memory is finished, the signal that sends. |
| EX41N interrupts | MSCA | When data service mode: when the transmission from the DSP source register to memory is finished, the signal that sends. |
| EX51N interrupts | MSCA | When from memory when relatively the transmission of input register is finished, the signal that sends. |
| EX61N interrupts | MSCA | When the transmission of the data from memory to DSP/control byte register is finished, the signal that sends. |
| EX71N interrupts | MSCA | When configuration during radio: when from the memory to the radio configuration/when the transmission of time slot mapping data register is finished, the signal that sends.When data service mode: when never encoding receive data register when the transmission of memory is finished, the signal that sends. |
In one embodiment, PEC ISR not be " non-co-operate " on the meaning that real time operating system is connected.System processor (for example, shown in Figure 15 microcontroller 1505) is preferably highest priority and the group number service that PEC interrupts.Preferential status is listed in request to a plurality of PEC channel the time in according to the PEC channel number, and here, channel 0 has lowest priority, and channel 7 has highest priority.Following table 5-2 has exported PEC interrupt distribution in one embodiment.
Table 5-2
| PEC channel (PECCx) | Interrupt |
| PECC7-radio configuration DMA | ????EX71N |
| PECC6-RX is DMA relatively | ????EX51N |
| PECC5-DSP exports DMA | ????EX21N |
| PECC4-is wireless RX DMA | ????EX11N |
| PECC3-DSP imports DMA | ????EX61N |
| PECC2-is wireless TX DMA | ????EX01N |
| PECC1-does not use at present | ????EX41N |
At the terminal point that the data that are used to set up the PEC channel transmit, call relevant PEC ISR and carry out the transmission that PEC finishes and handle.If interrupt action specifies an event counter to go to upgrade, then PEC ISR increases progressively the event counter counting.If interrupt action is specified a call operation program, then PEC ISR calls the operation sequence of this appointment.In this preferred embodiment, have only with wireless transmission DMA to send operation sequence of calling of PEC ISR appointment that task 235 is associated.
The PEC event counter can be monitored by outside (that is non-PEC ISR) software processing part.These external softwares are handled and can be made a given PEC event counter zero clearing (that is, zero), it are increased progressively, until upset.
Following table 5-3 has summarized the main output of PEC ISR and their target, and note.
Table 5-3
| Project | Target | Note |
| PECCx event counter (1-7) | ????MSCA?ISR | PEC end interrupt counter |
| Interrupt | TX finishes ISR | The TX frame is finished notice |
In one embodiment, wireless radio service module 217 provides a common interface to digital radio ASIC (DRA).Wireless radio service module 217 preferably provides the operation sequence of configuration reception and transmission frequency, code and header, with the control transmitted power, makes radio to slot synchronization, reads the RSSI value and disposes various threshold values.In order to communicate by letter with DRA, wireless radio service module 217 can utilize register and the control ASIC 205 among the control ASIC 205 to transmit the DMAI/O operation that task 223 triggers by for example radio configuration DMA data.
Following table 6-1 has summarized the key data element that wireless radio service module 217 is utilized, and note.
Table 6-1
| Element | Note |
| Radio configuration | The current wireless configuration |
| Radio configuration is upgraded | New |
| Synthesizer | |
| 1 frequency meter | For producing the hardware specific value that reception and transmission frequency are loaded |
| | For producing the hardware specific value that characteristic frequency is loaded |
| Receive code table | The CDMA receiving code |
| Receive the header table | Receive header |
| Send code table | CDMA sends sign indicating number |
| The transmit head table | Transmit head |
Wireless radio service module 217 is preferably configuration or handles the radio adaptation program provides following operation:
1, initialization (radio transceiver 305 is resetted and be initialised to idle pulley)
2, (idle condition that radio is reset to it) resets
3, config update control
A, register upgrade (being further to load to keep new configuration to be provided with)
B, upgrade (be transformed into and load one new configuration be provided with)
4, receive start-up control (start or forbid the data path of radio) to memory
5, send start-up control (starting or forbid being used for the transmission of current receiving slot)
6, Synchronization Control
A, acquisition time slot (are removed synchronously and are received by for example discovery is next
Header is sought next good receiving slot)
B, synchronization slot (locking onto the next good receiving slot that receives)
C, synchronization DS P (sending DSP lock-out pulse) about a time slot
7, sequential chain control (selecting wireless sequential chain)
8, time slot selects control (when selecting the next one about current receiving slot to receive
The crack; Be referred to as " next time slot pointer ")
9, transmission power control
A, power controlling level (increasing or reduce power level control)
B, write power level (load power level control)
10, (configuration that loading has a current selection is provided with parameter to load the CDMA configuration
DRA comprises receive frequency, and receiving code receives header, and transmission frequency is sent out
Send sign indicating number and transmit head)
11, (loading has the DRA of " static state " parameter, comprises inspection to load static configuration
Survey/tracking threshold value, ratchet notch threshold value, and simultaneous bias)
12, read RSSI (reading mean value related and difference) with current receiving slot.
The ARQ mechanism of the ARQ service module 220 of software control system 211 to carry out in the carrier grouping provides error detection occurs, error recovery, error notification and prioritisation of messages.ARQ service module 220 is after the received frame of a time slot but be called before the transmit frame of this time slot, so that before next grouping is sent out, a request that resends last reception grouping can be sent to the base station.ARQ service module 220 can be divided into two state machines from function, and one is used to receive ARQ, and one is used to send ARQ.Figure 14 is the schematic diagram of state table 1401 of the operation sequence performance of diagram ARQ service module 220.In Figure 14, " Msg CRC state " representative derives from the error state of cyclic redundancy check (CRC); " the TX Msg# " of " RX Msg# " indication base station message whether match (that is, the message of reception whether be " identical " message or " next one " message by expection) with desired value; What " RX ACK " indicated affirmation 104 receptions from the base station is (ACK) message or (" NAK ") unconfirmed message; " special Msg? " whether indicate this message is the message of which kind of type that will not cause RXMsg# to be upgraded; " TX ACK " indication is that ACK or NAK message will turn back to base station 104; " RX Msg# " indication subscriber station 301 will send the packet identical with previous transmission still will send a new data packet; " next expection RX MSG# " indication from the next received frame of base station 104 whether should constitute one with identical packet or the new data packet of previous reception.
In a preferred embodiment, the reception ARQ state machine of ARQ service module 220 is responsible for filtering the copy message from base station 104 usually.When base station 104 can not be when subscriber station 301 receives ACK to its previous message that sends, it can for example send one and duplicate (repetition) message.By checking " RX Msg# " bit of 104 message (that is, packet) that receive from the base station, receive ARQ state machine filtering copy message.If " RX Msg# " bit and " Msg# of expection " coupling are thought that then this message is effective, and are handled.Otherwise, think that this message is copy message, so deleted.
Under the situation of 104 some particular message that receives (for example, CT-HLD (control is professional to keep) and lose the CT-SPO (control professional specific polling) of link between convalescence) from the base station, subscriber station 301 do not upgrade this " RX Msg# ".Subscriber station 301 is handled these particular message, although " RXMsg# " may not match " Msg# of expection ".In addition, when initial paging, subscriber station 301 will accept to be used for any value of " RX Msg# ".At initial communication during from the ordinary round-robin of base station 104 control service message (CT-GPO), subscriber station 301 will begin to remember " RX Msg# " from base station 104 in the mode of carrying out.
The reception ARQ state machine of ARQ service module 220 also is responsible for the ACK/NAK value according to the ARQ field the packet that receives from base station 104, " the TX Msg# " of upgrading subscriber station.When receiving of subscriber station message confirmed by " ACK " bit in the ARQ field of the message of subscriber station 301 is set in base station 104, subscriber station 301 upgrading " TX Msg# " (if it have new data to be sent), " the TX Msg# " that is sent in the new data in the next message and is upgraded to base station 104 then.If subscriber station has been received one to " ACK " of its last message response that sends but there is not new information to send, then subscriber station 301 will send the professional maintenance of a control message (CT-HLD), and do not upgrade " TX Msg# ".
The transmission ARQ state machine of ARQ service module 220 is responsible for, and by sending one " ACK " or " NAK " in due course in the next message that subscriber station 301 sends, whether 104 1 particular messages of informing base station are successfully received on subscriber station.Send the ARQ state machine and also be responsible for successfully not receiving the message that subscriber station 301 sends, shown in the ACK/NAK of the ARQ field that receives message to higher level (ISO term) indication base station 104.
When from the base station 104 when receiving a message, subscriber station 103 can be carried out a cyclic redundancy check (CRC), to determine whether to have received the message that mistake is arranged.The CRC state of the message that subscriber station 301 receives usually to ARQ service module 220 transmission ARQ state machine and receive the ARQ state machine and make a difference, for example, shown in state table shown in Figure 14.
The message that subscriber station 301 receives has " head CRC " and " frame CRC ".If head CRC is good, considered frame CRC not then, this head is considered to comprise subscriber station 301 manageable effective informations.For example, if the information that subscriber station 301 is received has good head CRC and bad frame CRC, and have the ACK bit setting, then subscriber station 301 can then send a new information, because it knows that the base station successfully received its last message that sends (because ACK bit is provided with).Yet the D and the B channel that receive message are left in the basket, because bad frame CRC indication grouping contains mistake.Therefore, subscriber station 301 will send " NAK " about this reception message, and will delete the message of this reception.
The power control service module 221 of software control system 201, powered controls of operating in the head based on the packet of transmission between subscriber station 301 and the base station 104, the transmission power level of the radio transceiver 305 of control subscriber station 301.Power control service module 221 is preferably in after the received frame of time slot but was called before the next transmit frame of this time slot, so that allow to be undertaken by base station 104 the closed power control of subscriber station 301.In present preferred embodiment, a power control field (that is, one group of bit) that contains in the head of subscriber station 301 response base station message, 7-1 adjusts transmitted power according to table.
Table 7-1
| At preceding power bit | The current power bit | The TX power level is recommended |
| ??????0 | ??????0 | Reduce TX power |
| ??????1 | ??????1 | Increase TX power |
| ??????0 | ??????1 | Keep current TX power |
| ??????1 | ??????0 | Keep current TX power |
| Lose | ??????0 | Keep current TX power |
| Lose | ??????1 | Increase TX power |
| ??????0 | Lose | Keep current TX power |
| ??????1 | Lose | Increase TX power |
| Lose | Lose | Increase TX power |
Here have two kinds of continuous groupings that received before any action of adjusting power level of being adopted by subscriber station 301 at least, the power level of subscriber station is not adjusted when receiving initial packet.In a kind of situation, the transmission power level of subscriber station is by " soft restriction ", and wherein when on the highest or lowest transmit power level, one increases or reduces and asks not influence transmission power level.
To provide more detailed description to some hardware aspect of control section shown in Figure 15 1501 below.In a preferred embodiment, control section 1501 is particularly controlled ASIC1502, comprises having by the given function of the information among the following table 8-1 of being presented on and the register of access mode.
Table 8-1
| The address | The register title | Content of registers | Access mode |
| 0E01AH | The time slot mapping pointer | The time slot mapping pointer | Write |
| 0E019H | Linearizer 1 and 2 | Linearizer control and data | Read/write |
| 0E018H | Test model | The MS loopback | Write |
| 0E017H | Normal state | Relatively finish, relative error, the RX frame is finished, SIM TX error, pattern changes, and button is pushed/is discharged | Read |
| 0E016H | Interruption controls | Interrupt @ and finish relatively, interrupt @ and finish RX, interrupt the @RC upset | Write |
| 0E015H | Relatively input | The order comparing data, mask | Write |
| 0E014H | Relatively output | Order number of times relatively | Write |
| 0E013H | DSP data/control byte | DSP data/control byte | Write |
| 0E012H | The DSP source | The dsp code data that are used to send | Read |
| 0E011H | The receiver source | Data from the OTA reception | Read |
| 0E010H | Send target | Transceiver as target | Write |
| 0E00FH | Sleep control | μ C power descends, and μ C is standby, the DSP sleep, | Write |
| The codec sleep, wireless ASIC sleep, linearizer ASIC sleep, μ C is effective | |||
| 0E00EH | Reset | Wireless ASIC, DSP, RC counter, OTA LCA | Writing/Reading |
| 0E00DH | Accepting state | Frame error, head error, frequency error, transmitter fault | Read |
| 0E00CH | RSSI byte 1 and 2 | RSSI data first and second bytes | Read |
| 0E00BH | Sync byte 1 and 2 | DSP sync byte 1 and 2 | Write |
| 0E00AH | Key | Internal cryptographic | Read |
| 0E009H | Do not use |
| 0E008H | SIM sends counting | SIM sends byte count | Write |
| 0E007H | SIM control | The SIM counter-rotating, parity modes E/O, it is high/low to stop clock, TX/RX MSB first, activate clock, activate VCC, reset level | Write |
| 0E006H | SIM sends | SIM sends data/order | Write |
| 0E006H | SIM receives | SIM receives data/order | Read |
| 0E005H | Linearizer control | Take, automatic mode starts, receiving mode | Read/write |
| 0E004H | Do not use | ||
| 0E003H | ??KEYRESP | Keyboard is pushed ID (row 8-1) | Read |
| 0E003H | ??KEYPOLL | Keyboard commands | Write |
| (row 4-1) activates | |||
| 0E002H | Radio configuration/time slot mapping data | The target of radio configuration/time slot mapping data | Write |
| 0E001H | The radio configuration sign indicating number | The radio configuration sign indicating number is provided with | Write |
| 0E000H | General register | The SIM that resets, the RX that resets, TX activates, and annunciator activates, and DSP activates | Write |
| 0E000H | General register | Hands-free, the configuration pin | Read |
In a preferred embodiment, time slot mapping pointer register (0E01AH) provides a destination address that is used for to wireless interface circuit sending time slots mapping (enum) data.When microcontroller 1505 will be indicated next time slot by radio transmitting, microcontroller 1505 write the time slot mapping pointer register to a new numerical value.Then by wireless interface circuit (comprise, for example, RIF ASIC 1514) sense data, to determine next time slot of operation.The time slot mapping pointer register is defined as follows:
Address: 0E01AH
MSB?????????????????????????????????????????????????????????LSB
| ????7 | ????6 | ??5 | ??4 | ??3 | ??2 | ??1 | ??0 |
| Do not have | Do not have | MAP5 | ?MAP4 | ?MAP3 | ?MAP2 | ?MAP1 | ?MAP0 |
Bit 5-0 MAPx-time slot pointer mapping value
' value '-time slot pointer mapping value.This will be the hexadecimal value of the number of indication time slot carry.
' 00H '-invalid (initial condition)
Bit 7-6 does not use
Linearizer register (0E019H) serves as the control port of turnover linearizer ASIC 1513.When microcontroller 1505 was expected to linearizer ASIC 1513 transmitting control commands or data, it write the linearizer register with a byte.When response, the linearizer interface circuit among the OTALCA 1502 sends command to linearizer ASIC 1513.If the order of sending is read command, then reads canned data in the linearizer register, but have only bit 5-0 to be considered to effective.This register definitions is as follows:
Address: 0E019H
MSB?????????????????????????????????????????????????????LSB
| ??7 | ??6 | ??5 | ??4 | ??3 | ??2 | ??1 | ??0 |
| ?CMD7 | ?CMB6 | ?CMD5 | ?CMD4 | ?CMD3 | ?CMD2 | ?CMD1 | ?CMD0 |
Linearizer ASIC is advanced/gone out to bit 7-0 CMDx-order or data
' value '-command value
' 00H '-invalid (initial condition)
The various test models that test register (0E018H) definition OTA LCA can be inserted by controller.This register definitions is as follows:
Address: 0E018H
MSB??????????????????????????????????????????????LSB
| ????7 | ???6 | ???5 | ???4 | ???3 | ???2 | ???1 | ???0 |
| ????MS ?LOOPBACK | Do not have | Do not have | Do not have | Do not have | Do not have | Do not have | Do not have |
Bit 6-0 does not use
This bit of bit 7 MSLOOPBACK-activates or the operation of deexcitation MS loopback.
' 1 '-mobile phone is placed in loopback.
' 0 '-no loopback (initial condition)
Normal state register (0E017H) comprises some bit special state information that can cause the incident of microcontroller 1505 interruptions.When microprocessor received that a normal state interrupts, it responded with the reason of determining this interruption by reading the normal state register.After microprocessor was read the normal state register, OTA LCA 1502 removed this status bits, always indicates the real causes of an interruption with the data of guaranteeing to exist in the register.It is ' 0 ' that initial condition is set to all bits.This register is determined as follows:
Address: 0E017H
MSB???????????????????????????????????????????????????????????LSB
| ??7 | ??6 | ??5 | ?4 | ??3 | ???2 | ???1 | ????0 |
| ?KEY ?PRS- ?RLS | ?MODE ?CHG | SIMTX ERROR | Do not have | ??RX ?ERROR | RXCMPLT | ?COMPAR ?EERROR | ?CMPCMPLT |
Bit 0 CMPCMPLT-relatively finishes-indicates comparative sequences and finishes (relatively counter=0).
' 1 '-relatively finish
' 0 '-invalid
All bytes that bit 1 COMPARE ERROR-indication comparative sequences does not match and was compared.
' 1 '-comparison error
' 0 '-invalid
The Data Receiving that bit 2 RXCMPLT-finish receiving-indicate in the receiving unit of time slot is finished.
' 1 '-finish receiving
' 0 '-invalid
' 1 '-reception error
' 0 '-invalid
' 1 '-SIM transmits error
' 0 '-invalid
' 1 '-detect change
' 0 '-invalid
' 1 '-keyboard is pushed or is discharged
' 0 '-invalid
Interrupt control register (0E016H) determines when and whether OTA LCA1502 will produce interruption to microcontroller 1505 according to specified requirements.Initial condition is set to all bits and is " 0 ".This register is determined as follows:
Address: 0E016H
MSB??????????????????????????????????????????????????????????????LSB
| ??7 | ??6 | ??5 | ??4 | ??3 | ???2 | ????1 | ????0 |
| Do not have | Do not have | Do not have | Do not have | Do not have | INTRRCRL | INTRXFRM | ?INTCMPC |
Bit 0 INTCMPC-is about the interruption relatively finished-interrupt and should send when comparative sequences (error or error free) finishes to normal state of OTA LCA indication.
When finishing, ' 1 '-comparative sequences interrupts
When finishing, ' 0 '-comparative sequences do not interrupt
When finishing, bit 1 INTRXFRM-RX frame interrupts-interrupt and when received frame (good or bad reception) finishes, to send to normal state of OTA LCA indication.
When finishing, ' 1 ' received frame interrupts
' 0 ' received frame does not interrupt when finishing
Interrupt during the upset of bit 2 INTRRCRL-RC circuit-overturn to the long timer counter of μ C indication RC.Can be used for the long duration counter and allow the controller long duration to be waken up periodically.
When finishing, interrupts ' 1 '-time
' 0 '-time does not interrupt when finishing
Bit 7-3 does not use
Order comparison command template of input register (0E015H) and mask are to carrying out a compare operation.This register is provided for the destination address of write command template and mask to comparison circuit.Microcontroller 1505 response PEC interrupt, and at first write data byte, and basis PEC interruption next time writes this address with the mask of these data of user then.The comparison circuit of OTA LCA1502 is suitably stored these data.The register definitions of order input register is as described below:
Address: 0E015H
MSB???????????????????????????????????????????????????????????????????LSB
| ???7 | ???6 | ???5 | ???4 | ???3 | ???2 | ???1 | ???0 |
| ?DATA7 | ?DATA6 | ?DATA5 | ?DATA4 | ?DATA3 | ?DATA2 | ?DATA1 | ?DATA0 |
The data or the mask value of a single compare operation of bit 7-0 DATAx-.
' value '-data/mask value, note: ' 0 ' will cause respective data bit by mask.
' 00H '-invalid (initial condition)
Compare counter register (0E014H) is defined in a plurality of reception bytes that compare during command template/mask comparative sequences.Microcontroller 1505 is write the information (not using from the byte number that compares buffer) of the reception byte number that control compares to compare counter register, thereby starts a comparative sequences that is used for next received frame.This register definitions is as follows:
Address: 0E014H
MSB??????????????????????????????????????????????????????????LSB
| ????7 | ????6 | ????5 | ??4 | ??3 | ??2 | ??1 | ??0 |
| Do not have | Do not have | Do not have | ?CNT4 | ?CNT3 | ?CNT2 | ?CNT1 | ?CNT0 |
Bit 4-0 CNTx-relatively count value-each count value corresponding to command template and mask from the comparison buffer of SRAM.
' value '-count value (can from for example changing in 03 to the 1C hexadecimal scope)
' 00H '-invalid (initial condition)
Bit 7-5 does not use
DSP data/control byte register (0E013H) is used to the operation about DSP/ sound synthesizer 1510.When OTA LCA 1502 received a frame synchronization, the data that are encoded were sent to the DSP/ sound synthesizer 1510 that is used to decode.These data are made up of carrier data and DSP control information usually.In order to carry out the transmission of data, OTA LCA1502 utilizes PEC to ask the information of each byte ground retrieve stored.In when response, data and control byte that microcontroller 1505 will be used to send to DSP/ sound synthesizer 1510 write DSP data/control byte register.This register definitions is as follows:
Address: 0E013H
MSB???????????????????????????????????????????????????????????????????LSB
Bit 7-0 DATAx-is used for the control information of DSP/ sound synthesizer
| ???7 | ???6 | ???5 | ???4 | ???3 | ???2 | ???1 | ???0 |
| ?DATA7 | ?DATA6 | ?DATA5 | ?DATA4 | ?DATA3 | ?DATA2 | ?DATA1 | ?DATA0 |
' value '-control or data value
' 00H '-invalid (initial condition)
DSP source register (0E012H) provides dsp code data and state byte is moved to SRAM transmission buffer 1707 (referring to Figure 17) mechanism.After 1510 pairs of digital coding that are used to send of DSP/ sound synthesizer, this coded data is sent to OTA LCA1502, produce a PEC request then coded data is put into SRAM transmission buffer 1707, when microcontroller 1505 is inserted the DSP source register to information, OTA LCA 1502 is placed on data on the system bus 1530, and it is write SRAM 1524.This register definitions is as follows:
Address: 0E012H
MSB????????????????????????????????????????????????????????????????????LSB
| ???7 | ???6 | ???5 | ???4 | ???3 | ???2 | ???1 | ???0 |
| ?DATA7 | ?DATA6 | ?DATA5 | ?DATA4 | ?DATA3 | ?DATA2 | ?DATA1 | ?DATA0 |
Bit 7-0 DATAx-DSP coded data
' value '-dsp code data value
' 00H '-invalid (initial condition)
Reception sources register (0E011H) is provided for the address and the data of read operation, and the data that receive with 104 the link through the base station are associated.When data when radio transceiver 305 arrives, OTA LCA 1502 produces the PEC request, makes data deposit SRAM reception buffer 1706 in.For each read operation of microcontroller 1505 access reception sources registers, OTA LCA 1502 inserts SRAM reception buffer 1706 and responds by receiving data recently.This register definitions is as follows:
Address: 0E011H
MSB???????????????????????????????????????????????LSB
| ???7 | ???6 | ???5 | ???4 | ???3 | ???2 | ???1 | ???0 |
| ?DATA7 | ?DATA6 | ?DATA5 | ?DATA4 | ?DATA3 | ?DATA2 | ?DATA1 | ?DATA0 |
Bit 7-0 DATAx-receives aerial (OTA) data
' value '-data value.To there be header information, D-channel or B channel data.
' 00H '-invalid (initial condition)
Send destination register (0E010H) a PEC destination address is provided, it transmits with the data of the communication link of base station 104 and is associated.When OTA LCA 1502 requests sent the data of base station 104 to, microcontroller 1505 response PEC requests write transmitting data register with these data.This register definitions is as follows:
Address: 0E010H
MSB????????????????????????????????????????????????????????????????????LSB
| ???7 | ???6 | ???5 | ???4 | ???3 | ???2 | ???1 | ???0 |
| ?DATA7 | ?DATA6 | ?DATA5 | ?DATA4 | ?DATA3 | ?DATA2 | ?DATA1 | ?DATA0 |
The data that bit 7-0 DATAx-is to be sent.
' value '-data value.To be head, D channel and B channel data.
' 00H '-invalid (initial condition)
The sleep control setting of sleep control register (0EOOFH) definition OTA LCA 1502 pairs of microcontrollers 1505 and other hardware or ancillary equipment.When OTA LCA 1502 made microcontroller 1505 withdraw from standby and power to reduce pattern, OTA LCA 1502 removed two controller power-saving bits of (that is, resetting) sleep control registers.If two patterns all are effectively, then preferentially adopt the maximum power save mode.Microcontroller 1505 is responsible for turn-offing as required CODEC 1511, DSP/ sound synthesizer 1510, linearizer ASIC 1513 and digital radio ASIC (DRA).This register definitions is as follows: the address: 0E00FH MSB LSB
| ?7 | ??6 | ????5 | ??4 | ???3 | ??2 | ???1 | ???0 |
| Do not have | ALIVE | LINEARIZER ?ASIC?SLP | ?RADIO ?ASIC ?SLP | ?CODEC ?SLEEP | ?DSP SLEEP | ??μC ?STNDBY | ??μC ?PWRDWN |
The 80C165 controller describes in detail:
Ingoing power is reduced pattern with bit 0 μ C PWRDWN-indicating controller and OTA LCA 1502 reduces to 0Hz (by the microcontroller setting, being removed by OTALCA) with controller clock.
' 1 '-power reduces pattern
' 0 '-normal running (initial condition)
' 1 '-standby mode
' 0 '-normal running (initial condition) ancillary equipment power-saving register:
' 1 '-digital signal processor sleep pattern.
' 0 '-normal running (initial condition)
' 1 '-codec sleep pattern.
' 0 '-normal running (initial condition)
' 1 '-digital radio ASIC sleep pattern
' 0 '-normal running (initial condition)
' 1 '-linearizer ASIC sleep pattern
' 0 '-normal running (initial condition)
' 1 '-μ C has finished initialization (OTA LCA will reset).
' 0 '-normal running (initial condition)
Reseting register (0E00EH) is a read-write register, is provided for the control that resets of several circuit blocks and ancillary equipment for microcontroller 1505.In other appropriate module, provide some to reset.Owing to also implement this operation sequence, so OTALCA1502 provides the period of a reset operation for power rises.This register definitions is as follows:
Address: 0E00EH
MSB???????????????????????????????????????????????????????????????LSB
| ????7 | ???6 | ???5 | ???4 | ???3 | ???2 | ???1 | ???0 |
| Do not have | RIFASI -CRST | ?OTARST | ?RCCN- ?TRST | ?DSPRST | Do not have | Do not have | Do not have |
Bit 2-0 does not use
The bit 3 DSPRST-DSP OTA LCA 1502 DSP/ sound synthesizer that resets that resets-order.
' 1 '-(initial condition-have OTA LCA to remove) resets
' 0 '-do not reset
The bit 4 RCCNTRAT-order OTA LCA 1502 RC counter that resets.
' 1 '-(initial condition-removed by OTALCA) resets
' 0 '-do not reset
The bit 5 OTARST-OTA OTA LCA 1502 that resets-reset
' 1 '-(initial condition-removed by μ C) resets
' 0 ' does not reset
The bit 6 RIFASICRST-RIF ASIC OTA LCA 1502 digital radio ASIC (DRA) that resets that resets-order.
' 1 '-(initial condition-removed by OTA LCA) resets
' 0 '-do not reset
Error condition type when accepting state register (0E00DH) is indicated from the data error that radio transceiver 305 receives.Can be through 1505 mistakes of a normal state interrupt notification microcontroller, and when response, can select to read the accepting state register, to determine the character of this mistake.This register definitions is as follows:
Address: 0E00DH
MSB??????????????????????????????????????????????????????????????ISB
| ??7 | ??6 | ??5 | ??4 | ???3 | ????2 | ???1 | ???0 |
| Do not have | Do not have | Do not have | Do not have | TRNSERR | ?FREQERR | ?HDRERR | ?FRMERR |
When bit 0 FRMERR-frame error-will occur in is not confirmed the CRC of whole received frame.
' 1 '-mistake
' 0 '-zero defect (initial condition)
When bit 1 HDRERR-head mistake-will occur in is not confirmed the CRC that receives head.
' 1 '-mistake
' 0 ' zero defect (initial condition)
' 0 ' zero defect (initial condition)
The failure of bit 3 TRNSERR-indicator-transmitters.
' 1 ' mistake
' 0 ' zero defect (initial condition)
Bit 7-4 does not use
Address: 0E00CH
MSB????????????????????????????????????????????????????????????????????LSB
Bit 7-0 RSSIx-RSSI byte ' value '-RSSI value.Has the peaked hexadecimal value of 3F.' 00H '-invalid (initial condition)
| ???7 | ???6 | ???5 | ???4 | ???3 | ???2 | ???1 | ???0 |
| ?RSSI7 | ?RSSI6 | ?RSSI5 | ?RSSI4 | ?RSSI3 | ?RSSI2 | ?RSSI1 | ?RSSI0 |
Address: 0E00BH
MSB???????????????????????????????????????????????????????????????????LSB
| ???7 | ???6 | ???5 | ???4 | ???3 | ???2 | ???1 | ???0 |
| ?SYNC7 | ?SYNC6 | ?SYNC5 | ?SYNC4 | ?SYNC3 | ?SYNC2 | ?SYNC1 | ?SYNC0 |
Bit 7-0 SYNCx-depends on the sync byte 1 or 2 that writes.
' value '-sync byte.
' 0 '-invalid (initial condition)
SIM sends the reciprocation of counter register (0E008H) control and SIM port one 520.Microcontroller 1505 is write to SIM transmission counter register has to send SIM card to through SIM port one 520 for how many bytes.After successfully sending, SIM sends the value of storing in the counter register and is successively decreased at every turn, until final arrival zero.When this happens, SIM port one 520 transforms to receiving mode.This register definitions is as follows:
Address: 0E008H
MSB??????????????????????????????????????????????????LSB
| ??7 | ??6 | ??5 | ??4 | ??3 | ??2 | ??1 | ??0 |
| ?CNT7 | ?CNT6 | ?CNT5 | ?CNT4 | ?CNT3 | ?CNT2 | ?CNT1 | ?CNT0 |
Bit 7-0 CNTx-SIM sends byte count.
' value '-byte count value.
' 00H '-do not have to send and operate-invalid (initial condition)
SIM technology register (0E007H) provides the device of the control SIM port one 520 that adapts with the ISO/IEC7816-3 standard.Microcontroller 1505 provides startup setting and the number of times that is provided with when being made.When microcontroller 1505 initial resets were operated, some of the information that SIM card is returned was provided for the value of the control setting of SIM port one 520.These settings are written into the SIM control register, with the communication of control through SIM port one 520.This register definitions is as follows:
Address: 0E007H
MSB??????????????????????????????????????????????????????????????????LSB
| ???7 | ???6 | ???5 | ???4 | ???3 | ???2 | ???1 | ???0 |
| ?RESET ?LEVEL | ?ENABLE ??VCC | ?ENABLE ?CLOCK | MSBFRST | Do not have | ?CLKSHL | ?PE/O | ?SIMINV |
Bit 0 SIMINV-SIM reverse data-this bit should be with this data back before the SIM indication is sending.In addition, it orders SIM oppositely to give the data of PEC for reading order.OTA LCA SIM port will be carried out the reverse operating of data.
' 1 '-reverse data
' 0 '-data are reverse (initial condition) not
The parity check of ' 1 '-incident
' 0 '-odd check-(initial condition)
' 1 '-clock stops to a high position
' 0 ' clock stops to low level (initial condition)
' 1 '-least significant bit (LSB) is preferential
' 0 '-highest significant position (MSB) preferential (initial condition)
' 1 '-clock-provide clock is provided.
' 0 '-not provides clock (initial condition)-clock to be output as ' 0 ' to SIM card
' 1 '-activate VCC-to provide power supply to VCC
' 0 '-not to provide power supply (initial condition)-VCC level to the VCC of SIM card pin be ' 0 '
' 1 '-add to the high-value of reset signal
The low-value (initial condition) of reset signal is given in ' 0 '-tax
SIM transmitter register (0E006H) provides by microcontroller 1505 response and is used for a PEC request of SIM data and a data purpose writing.When SIM port one 520 when SIM card sends data.The request that OTA LCA 1502 produces a microprocessor 1502 by peripheral event controller, obtains sending to the more multidata of SIM card.This PEC request will send the counter register count value until SIM and arrive zero continuously, or the generation that resets.This register definitions is as follows:
Address: 0E006H
MSB???????????????????????????????????????????????????????????????????LSB
| ???7 | ???6 | ???5 | ???4 | ???3 | ???2 | ???1 | ???0 |
| ?DATA7 | ?DATA6 | ?DATA5 | ?DATA4 | ?DATA3 | ?DATA2 | ?DATA1 | ?DATA0 |
Bit 7-0 DATAx-will send to the SIM port data of SIM card.
' value '-data value.The details of this data value is referring to ISO/IEC7813-3.
' 00H '-invalid (initial condition)
SIM receiving register (0E006H) provides the data source address of being read by microcontroller 1505 response PEC requests.Data/control information is read through SIM port one 520, together places SRAM 1524 through a PEC request with the data that microcontroller 1505 moves then.This register definitions is as follows:
Address: 0E006H
MSB???????????????????????????????????????????????????????????????????LSB
| ???7 | ???6 | ???5 | ???4 | ???3 | ???2 | ???1 | ???0 |
| ?DATA7 | ?DATA6 | ?DATA5 | ?DATA4 | ?DATA3 | ?DATA2 | ?DATA1 | ?DAIA0 |
The data value that bit 7-0 DATAx-is read by controller.
' value '-data value.The details of this data value is referring to ISO/IEC7813-3.
' 00H '-invalid (initial condition)
Linearizer control register (0E005H) is provided for the controlling organization of linearizer ASIC 1513.Microcontroller 1505 is write the linearizer control register, sets with the control that expection is set.Whether microcontroller 1505 can also read from this register, occupied to determine linearizer ASIC 1513, or determines the state that control is set.This register definitions is as follows:
Address: 0E005H
MSB???????????????????????????????????????????????????????????LSB
| ????7 | ????6 | ??5 | ???4 | ???3 | ???2 | ???1 | ???0 |
| ?AUTOMODE | ?RECMODE | BUSY | Do not have | Do not have | Do not have | Do not have | Do not have |
Bit 0-4 does not use.
The state of bit 5 BUSY-indication linearizer.This bit is read-only.
' 1 '-indication linearizer interface is busy with sending to linearizer ASIC 1513
' 0 '-vacant (initial condition)
' 1 '-receiving mode starts
' 0 '-receiving mode invalid (initial condition)
' 1 '-automatic mode starts
' 0 '-automatic mode invalid (initial condition)
Keyresp register (0E003H) is the read-only memory that the current button of pushing of indication user is expert at.This register definitions is as follows:
Address: 0E003H
MSB?????????????????????????????????????????????????????LSB
| ???7 | ??6 | ??5 | ??4 | ??3 | ??2 | ??1 | ??0 |
| ?ROW8 | ?ROW7 | ?ROW6 | ?ROW5 | ?ROW4 | ?ROW3 | ?ROW3 | ?ROW1 |
Whether bit 7-0 ROWx-indicates the button in this row to be pressed
' 1 '-no button be pressed (initial condition)
Button is pressed in ' 0 '-this row
Button poll register (0E003H) is to allow microcontroller 1505 numerical value to be write the read-only register of keyboard rectangular array.Thereby microcontroller 1505 can detect the current button of pushing of user.Push identifier for button, microcontroller 1505 imposes on row with one ' 0 ' at every turn.The numerical value of row in the microcontroller 1505 key response registers.All multiple rows are necessary for the value that will be written to keyboard and activate.This register definitions is as follows:
Address: 0E003H MSB LSB
| ??7 | ??6 | ??5 | ??4 | ????3 | ??2 | ??1 | ??0 |
| ?COL4 | ?COL3 | COL2 | ?COL1 | ?COL_EN | Do not have | Do not have | Do not have |
Bit 2-0 does not use
' 1 '-use the value of the COLx of keyboard
' 0 '-disable register value is to keyboard (initial condition)
Bit 7-4 COLx-writes one 0 and will activate any bit position of respective column in the keyboard matrix.
' 1 '-invalid-no specimen (initial condition)
' 0 '-sample row
Radio configuration/time slot mapping data register (0E002H) provides a destination register for the radio configuration data, and these radio configuration data transmit from fast storage by the PEC operation.This register definitions is as follows:
Address: 0E002H
MSB?????????????????????????????????????????????????????LSB
Bit 7-0 D7-D0-radio configuration or time slot mapping data byte ' value '-data value ' 00H '-invalid (initial condition)
| ???7 | ???6 | ???5 | ???4 | ???3 | ???2 | ???1 | ???0 |
| ??D7 | ??D6 | ??D5 | ??D4 | ??D3 | ??D2 | ??D1 | ??D0 |
Radio configuration sign indicating number register (0E001H) contains the order to radio interface ply-yarn drill assembly that reconfigures radio transceiver 305.When data were obtained by RIF CLA, OTA LCA 1502 sent the PEC request that other data is sent to RIF LCA.This register definitions is as follows:
Address: 0E001H
MSB??????????????????????????????????????????????????????????LSB
The sign indicating number of bit 4-0 RFD-radio data sign indicating number ' value '-be used for rf data is provided with ' 00000 '-normal running (initial condition) bit 7-5 and does not use
| ????7 | ????6 | ????5 | ??4 | ??3 | ??2 | ??1 | ??0 |
| Do not have | Do not have | Do not have | RFD4 | ?RFD3 | ?RFD2 | ?RFD1 | ?RED0 |
General register (0E000H) is the write-only register that various controlled function are provided to several zones of OTA LCA 1502.This register definitions is as follows:
Address: 0E000H
MSB????????????????????????????????????????????????????????????????LSB
| ???7 | ????6 | ???5 | ??4 | ???3 | ???2 | ??1 | ??0 |
| ??DSP ?ENABLE | ?RINGER ??CTL1 | ?RINGER ??CTL0 | ??TX ENABLE | ?RSTRX | ?RSTSIM | Do not have | Do not have |
Bit 1-0 does not use at present
' 1 '-the SIM state machine resets
' 0 '-(initial condition) do not reset
The bit 3 RSTRX-OTA LCA accepting state machine that resets.When the accepting state machine has resetted, OTA LCA 1502 will remove this bit.
' 1 '-reset
' 0 '-(initial condition) do not reset
' 1 '-start and transmit
' 0 '-forbid (initial condition)
Bit 6-5 RINGER CTLx-connects ringer, produces a tone.This ringer is forbidden by software.
' 11 '-tone 3 (medium) starts (if feasible)
' 10 '-tone 2 (soft) starts
' 01 '-tone 1 (sound) starts
' 00 '-ringer is forbidden (initial condition)
' 1 '-DSP starts
' 0 '-DSP forbids (initial condition)
General register (0E000H) is a read-only register, is at any time read by microcontroller 1505, to determine current state and operator scheme.Usually, when OTALCA 1502 interrupts microcontroller 1505 and pointing-type change, read this general register.This register definitions is as follows:
Address: 0E000H
MSB???????????????????????????????????????????????????????????LSB
| ???7 | ???6 | ???5 | ???4 | ???3 | ????2 | ????1 | ????0 |
| Do not have | Do not have | Do not have | Do not have | Do not have | ?CONFIG ????2 | ?CONFIG ????1 | Hands-free |
Bit 0 is hands-free
' 1 '-hands-free invalid
' 0 '-connection hand free device
Bit 2-1 CONFIGx-disposes x
' value '-value pointing-type
Bit 7-3 does not use
Although some principle of operating has been described in conjunction with software implementation example and hardware embodiment at this, but it will be appreciated by one of skill in the art that can according to software or hardware or it be in conjunction with implementing various features and function, this depends on various compromise and other factors, such as, speed, volume, cost, simplification and efficient.Should be understood that the opinion that also depends on those skilled in the art with details is chosen in this enforcement, and do not deviate from inventive features described herein.
Principle of the present invention is applicable to mobile and fixed system, and the embodiment disclosed herein can be used in a mobile communication environment and a wireless local loop system.The present invention can also in conjunction with according to or in addition U.S. Patent application 09/159,714 and/or 09/160,010 disclosed feature and technology implement, each of these two U.S. Patent applications is as quoting as the reference that proves absolutely at this.
In a preferred embodiment, base station 104 and subscriber station 102 (or 301) use spread spectrum communication to communicate.Each above-mentioned embodiment can be configured to use spread spectrum communication to operate.Suitable spread spectrum sends and reception technique is for example disclosing in the United States Patent (USP) 5,016,255,5,022,047 or 5,659,547, and its each patent has transferred assignee of the present invention, and quotes as the reference that proves absolutely.Can the be designated different many spreading codes in different unit 103 (referring to Fig. 1) (or spreading code not on the same group, take this each code and be assigned to each subscriber station 102 temporarily), thus obtain the benefit of CDMA technology.Except using CDMA to distinguish the transmission of different units 103, can also according to specify the CDMA sign indicating number identical or a different repeat pattern different frequency is assigned to different units 103.
Although at this preferred embodiments of the present invention have been described, many variations can be retained in the principle and scope of the present invention.After checking specification and accompanying drawing, those skilled in the art will know this variation.Therefore, the present invention only is limited in the spirit and scope of incidental arbitrary claim.
Claims (34)
1. station that can communicate according to the time slot of time frame, described station comprises the radio of a transmission and received signal, a control system comprises:
A memory;
One group of time slot object that is stored in the described memory, each described time slot object comprises the tabulation of one or more time slots of regulation communication channel; And
A time slot manager, described time slot manager allow to set up or delete described time slot object.
2. control system according to claim 1 also comprises a driver that docks the upper-layer protocol parts.
3. control system according to claim 2, wherein said time slot manager and described driver communicate by the input and output message queueing.
4. control system according to claim 2, wherein driver is to ranking to the information of described time slot manager, so that response from the request of upper-layer protocol parts, increases, revises or the deletion time slot object.
5. control system according to claim 1, each in one or more time slots of wherein listing in the time slot object comprise, the subsequent timeslot that the indication of subsequent timeslot pointer is used to communicate by letter.
6. control system according to claim 1, wherein each described time slot object comprises radio configuration information.
7. control system according to claim 1, wherein the communication channel of being stipulated by one or more time slots of time slot object can be a regular traffic channel or a signaling channel.
8. control system according to claim 1 further comprises one group of interrupt service routine, is used for transmitting data with the response interrupt requests between source data storage location and target data memory location.
9. control system according to claim 8, wherein each interrupt routine transmits single byte to respond a corresponding interruption in the described interruption between source data storage location and target storage position.
10. control system according to claim 1, wherein said time slot object is handled continuously according to the order of being determined by the corresponding time slot position of the time slot of described time slot object.
11. control system according to claim 10, one of them time slot object is handled in the following manner: (a) according to the radio configuration information of storing in described time slot object configuration radio, and (b) send or reception information in listed at least one time slot in described time slot object.
12. control system according to claim 11, one of them time slot object is further handled by identifying a subsequent timeslot that is used to handle, and is subsequent timeslot repeating step (a) and (b).
13. an equipment comprises:
A radio transceiver;
A microprocessor;
A peripheral event controller that connects described microprocessor, described peripheral event controller receives one group of interrupt signal;
One group of source data storage location;
One group of target storage position; And
One connects described radio transceiver and the interface that is connected described peripheral event controller, thereby described microprocessor responds will be sent to described target data memory location from the data of described source data storage location from the interruption that described interface produces.
14. equipment according to claim 13, wherein said microprocessor transmit each interruption that a byte of data produces from described interface with response.
15. equipment according to claim 13 also comprises a memory of storing the program command of described microprocessor, described program command comprises a plurality of interrupt service routines.
16. equipment according to claim 15, each of wherein said interrupt service routine is corresponding to an interruption of described peripheral event controller.
17. equipment according to claim 16, each of wherein said interrupt service routine make described microprocessor transmit its corresponding interruption of response in the data between a source data position register and a target data location register.
18. equipment according to claim 13 also comprises a memory of storing a plurality of time slot object, each described time slot object comprises the tabulation of one or more time slots of stipulating a communication channel.
19. equipment according to claim 18, described time slot object is set up, revises or deleted to wherein said microprocessor according to one group of program command.
20. in a station that can communicate according to the time slot of time frame, a kind of method may further comprise the steps:
Produce one or more time slot object, each time slot object comprises a tabulation of one or more time slots of a communication channel of joint provisions;
According to a sequence of determining by the order of the time slot of listing in the time slot object, handle described one or more time slot object;
Radio transceiver of configuration on this station is so that send or receive in the listed time slot of time slot object.
21. method according to claim 20, each of wherein said one or more time slot object comprise a time slot profile.
22. method according to claim 21, wherein one or more time slots of time slot profile sign time slot object are sending time slots or receiving slot.
23. method according to claim 22, wherein the time slot profile comprises radio configuration information.
24. method according to claim 21, wherein the time slot profile comprises a message type identifier, is used to indicate the type of the message that will send or receive through the communication channel by one or more time slot defineds of time slot object.
25. method according to claim 24, the type of the message that wherein said message type identifier indication will send or receive is speech message or signaling message.
26. method according to claim 20, each of wherein said one or more time slot object comprise a plurality of time slot marks, the time slot that its each time slot mark sign is used to communicate by letter.
27. method according to claim 26, wherein each time slot mark comprises a subsequent timeslot pointer, is used to identify a subsequent timeslot that is used to communicate by letter, and described subsequent timeslot is listed in the time slot object.
28. method according to claim 20, wherein the described step of a radio transceiver of configuration may further comprise the steps on the station that sends or receive in the listed time slot of time slot object:
Be configured in the transmission of communicating by letter with first Target Station in the listed time slot of first time slot object or the radio transceiver of reception; And
Be configured in the transmission of communicating by letter with second Target Station in the listed time slot of second time slot object or the radio transceiver of reception.
29. in a station that can communicate according to the time slot of a time frame, a kind of control method for communicating may further comprise the steps:
One group of direct access storage channel is set between source data storage location and target data memory location, and described direct access storage channel is by microprocessor management;
Produce interruption periodically to microprocessor; And
Respond described interruption, between a source data storage location and a target data memory location, transmit data through described direct access storage channel.
30. method according to claim 29, wherein the step that transmits data through described direct access storage channel between a source data storage location and target data memory location comprises: for each interruption, and a byte of transmission data between a source data storage location and a target data memory location.
31. in a station that can communicate according to the time slot of a time frame, described station comprises a radio transceiver, a kind of communication means may further comprise the steps:
Produce first time slot object, described first time slot object identifies the time slot of the first communication channel of one or more regulation first Target Stations;
Produce second time slot object, described second time slot object identifies the time slot of the second communication channel of one or more regulation second Target Stations;
Radio transceiver is set, in one or more time slots of described first time slot object sign, sends or receive through described first communication channel about first Target Station;
Radio transceiver is set, in one or more time slots of described second time slot object sign, sends or receive through described second communication channel about second Target Station.
32. method according to claim 31, each of wherein said first time slot object and described second time slot object comprises radio configuration information.
33. method according to claim 31, each of wherein said first time slot object and described second time slot object identify the classification of the message that will pass through described first communication channel and transmission of described second communication channel or reception respectively.
34. method according to claim 33, wherein the described classification of the message that will send or receive comprises a speech message class classification and a signaling message class classification.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15973498A | 1998-09-24 | 1998-09-24 | |
| US09/159,734 | 1998-09-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1346557A true CN1346557A (en) | 2002-04-24 |
Family
ID=22573786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 99813631 Pending CN1346557A (en) | 1998-09-24 | 1999-09-08 | Management of time slot operations for wireless communication |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP1116352A4 (en) |
| CN (1) | CN1346557A (en) |
| AU (1) | AU6385299A (en) |
| SE (1) | SE0101058L (en) |
| WO (1) | WO2000018052A1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101887259A (en) * | 2010-06-29 | 2010-11-17 | 重庆大唐科技股份有限公司 | Coal-fired weighing networked intelligent system |
| CN101194477B (en) * | 2005-06-09 | 2012-10-31 | Nxp股份有限公司 | communication system node and storage method for data related with control and buffer |
| CN101442712B (en) * | 2003-11-07 | 2013-07-17 | 株式会社日立制作所 | Radio communicating system, base station, radio terminal and radio communication method |
| CN106126326A (en) * | 2016-06-23 | 2016-11-16 | 东软集团股份有限公司 | Timing task management method and apparatus |
| CN110363980A (en) * | 2019-07-25 | 2019-10-22 | 四川长虹电器股份有限公司 | LoRa acquisition device and its acquisition method based on TDMA and Contiki |
| CN110703008A (en) * | 2019-09-20 | 2020-01-17 | 中国电力科学研究院有限公司 | Station domain processing method and device for broadband measurement data |
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| US6735180B1 (en) | 2000-06-30 | 2004-05-11 | Nokia Mobile Phones, Ltd. | Method of sending feedback information in a fast automatic repeat request forming part of an overall wireless communication system |
| EP1421726A4 (en) * | 2001-07-02 | 2006-08-09 | Gilat Satellite Networks Ltd | Method, device, and system for managing communication transmissions |
| IN2014MN02189A (en) * | 2012-04-22 | 2015-09-11 | Elta Systems Ltd | |
| US9232522B2 (en) | 2013-07-19 | 2016-01-05 | Motorola Solutions, Inc. | Full duplex direct mode individual and group calling using adjacent time slots in a TDMA system |
| US9231693B2 (en) | 2013-07-19 | 2016-01-05 | Motorola Solutions, Inc. | Full duplex individual call via linked single frequency repeaters |
| TWI680651B (en) * | 2018-01-03 | 2019-12-21 | 立積電子股份有限公司 | Radio-frequency signal processing apparatus |
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| CA1280216C (en) * | 1986-08-05 | 1991-02-12 | At&T Global Information Solutions Company | Time slot protocol in the transmission of data in a data processing network |
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-
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- 1999-09-08 EP EP99951410A patent/EP1116352A4/en not_active Withdrawn
- 1999-09-08 AU AU63852/99A patent/AU6385299A/en not_active Abandoned
- 1999-09-08 CN CN 99813631 patent/CN1346557A/en active Pending
- 1999-09-08 WO PCT/US1999/020587 patent/WO2000018052A1/en not_active Application Discontinuation
-
2001
- 2001-03-26 SE SE0101058A patent/SE0101058L/en not_active Application Discontinuation
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101442712B (en) * | 2003-11-07 | 2013-07-17 | 株式会社日立制作所 | Radio communicating system, base station, radio terminal and radio communication method |
| CN101194477B (en) * | 2005-06-09 | 2012-10-31 | Nxp股份有限公司 | communication system node and storage method for data related with control and buffer |
| US8660131B2 (en) | 2005-06-09 | 2014-02-25 | Nxp B.V. | Storage unit for communication system node, method for data storage and communication system node |
| CN101887259A (en) * | 2010-06-29 | 2010-11-17 | 重庆大唐科技股份有限公司 | Coal-fired weighing networked intelligent system |
| CN106126326A (en) * | 2016-06-23 | 2016-11-16 | 东软集团股份有限公司 | Timing task management method and apparatus |
| CN110363980A (en) * | 2019-07-25 | 2019-10-22 | 四川长虹电器股份有限公司 | LoRa acquisition device and its acquisition method based on TDMA and Contiki |
| CN110703008A (en) * | 2019-09-20 | 2020-01-17 | 中国电力科学研究院有限公司 | Station domain processing method and device for broadband measurement data |
Also Published As
| Publication number | Publication date |
|---|---|
| AU6385299A (en) | 2000-04-10 |
| WO2000018052A1 (en) | 2000-03-30 |
| EP1116352A1 (en) | 2001-07-18 |
| WO2000018052A9 (en) | 2001-03-08 |
| SE0101058L (en) | 2001-05-21 |
| EP1116352A4 (en) | 2003-09-17 |
| SE0101058D0 (en) | 2001-03-26 |
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