CN1322410C - Data transmission system capable of carrying out multitask access on ATA bus - Google Patents
Data transmission system capable of carrying out multitask access on ATA bus Download PDFInfo
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- CN1322410C CN1322410C CNB2004100420610A CN200410042061A CN1322410C CN 1322410 C CN1322410 C CN 1322410C CN B2004100420610 A CNB2004100420610 A CN B2004100420610A CN 200410042061 A CN200410042061 A CN 200410042061A CN 1322410 C CN1322410 C CN 1322410C
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Abstract
The present invention relates to a data transmitting system which comprises a host machine controller provided with an end interface of an ATA bus host machine, a switcher, and a first data storing device, a second data storing device which are provided with end interfaces of an ATA bus device. When the command priority of the host machine controller to the second data storing device higher than that of the first data storing device, the host controller starts to send a first command to the first data storing device and then can control the switcher through a channel selecting signal to switch the selecting signals of a group of chips to the selecting signals of the other group of chips when the host controller does not send out chip selecting signals and the data storing device is not in a direct memory transmitting mode, and then the host controller can send a second command to the second data storing device without interrupting and changing the command executing state of the first data storing device before the execution of the first command is not finished.
Description
Technical field
The present invention relates to a kind of data transmission system, particularly relate to, be used for carrying out the data transmission system of order (commands) and the transmission of data (data) based on utilizing ata bus (advancedtechnology attachment bus, ATA bus).
Background technology
Ata bus is a data transmission standard that widely uses.For example, in personal computer (personalcomputer) system, ata bus promptly is used between main frame and Winchester disk drive or main frame and the CD-ROM drive, with the transmission data.About ata bus, existing disclosed description, its mode of action is known by industry.
See also Fig. 1, Fig. 1 is the synoptic diagram of given data transmission system 10.Data transmission system 10 comprises an ata bus signal transmssion line 12, a main frame 14, a Winchester disk drive 16 and a CD-ROM drive 18.
Ata bus signal transmssion line 12 can be the transmission line that comprises 40 barss or 80 barss.As shown in Figure 1, main frame 14, Winchester disk drive 16 and CD-ROM drive 18 are by ata bus host side interface 15, and each other ata bus device end interface 17 and 19, via 12 series connection of ata bus signal transmssion line.When console controller only had single ata bus host side interface, these devices only can connect with series system.
See also Fig. 2, Fig. 2 is the synoptic diagram of given data transmission system 20.In the data transmission system 20, main frame 14, Winchester disk drive 16 and CD-ROM drive 18 connect with parallel way, have in fact used two groups of ata bus signal transmssion lines 12 and 13.Compared to the data transmission system 10 of Fig. 1, the data transmission system 20 of Fig. 2 needs need set up another group ata bus host side interface 21 because of having set up ata bus signal transmssion line 13 on main frame 14.This kind utilizes parallel way when main frame needs control simultaneously or two data storage devices of access, more often is used.
According to the ata bus instructions, in the data transmission system 10 of Fig. 1, when (command) issued an order in main frame 14 beginning for CD-ROM drive 18 after, to finish at CD-ROM drive 18 before the execution of this order, main frame 14 can not be issued an order or carries out the transmission of data (data) Winchester disk drive 16.That is to say, under main frame and situation that two storage devices are connected, when main frame 14 begins after wherein a storage device is issued an order, finish at this storage device before the execution of this order, main frame 14 can not carry out order or carry out the transmission of data (data) being connected in another online storage device of same ata bus signal transmission.
See also Fig. 3, and in conjunction with Fig. 1.Fig. 3 is the Winchester disk drive 16 and the synoptic diagram of CD-ROM drive 18 according to sequential operation of Fig. 1.Among Fig. 3, axis T is a time shaft; The different operating that on behalf of Winchester disk drive 16, axis HDD carry out according to time sequencing; The different operating that on behalf of CD-ROM drive 18, axis DVD carry out according to time sequencing.Please refer to axis DVD, main frame 14 is assigned an order by ata bus host side interface 15, ata bus transmission line 12 and ata bus device end interface 19 to CD-ROM drive 18, and produces one period when order apart from (CMD) 22.The preparation of CD-ROM drive 18 before according to this command execution data transmission bide one's time apart from (WAIT) 24 and produce one section grade.And CD-ROM drive 18 begins data transmission to main frame 14 according to this order, or begins to receive data from main frame 14, thus when producing one section transmission apart from (XFER) 26.And from 14 pairs of CD-ROM drives 18 of main frame assign one the order, to the transmission finish sometimes the distance 22,24,26, CD-ROM drive 18 is all in running order.
In like manner, please refer to axis HDD, in the time of can producing corresponding order about the various operations of Winchester disk drive 16 apart from 28, etc. bide one's time apart from 30 and during transmission apart from 32.And in the time in 28,30,32, Winchester disk drive 16 is all in running order.
Yet, the grade of axis DVD as shown in Figure 3 bide one's time apart from 24 and axis HDD etc. bide one's time in 30, main frame is neither issued an order to CD-ROM drive 18 and Winchester disk drive 16, CD-ROM drive 18 and Winchester disk drive 16 are not carried out order or transmission data yet.That is to say, bide one's time among 24 and 30 waiting, can be considered the idle state of ata bus host side interface 15, in fact then is a kind of waste of transfer resource.
According to the regulation of ata bus instructions, when CD-ROM drive 18 was in running order, main frame 14 can not be issued an order to control or data transmission to another device hard disk machine 16 that is on the same ata bus transmission line 12.But the asynchronism(-nization) that different types of data memory device is spent when operating.As shown in Figure 3, the time that is spent during CD-ROM drive 18 operation is much larger than Winchester disk drive 16, and the medium that CD-ROM drive 18 is read is replaceable type, and its grade was bide one's time apart from 24 times that spent easily to be increased because of the difference that reads medium.The difference of required spended time, remove the fact that highlights transmission resource waste, also cause console controller hard disk 16 to be controlled or during data access at needs, the time delay that increase can not be expected, and its maximum-delay can reach the time apart from 22,24, and 26 summation.As shown in Figure 3, the grade of CD-ROM drive 18 is bide one's time apart from 24, when being enough to make Winchester disk drive 16 to finish order apart from 28, etc. bide one's time apart from 30 and during transmission apart from 32.Yet, because the agreement of ata bus standard, thus the given data transmission system leave each hardware etc. bide one's time apart from the waste that causes transfer resource.
Problem in the face of transmission resource waste, formulated the data memory device specification of so-called order overlapping function (commandoverlapped feature), but be on the market, employing has the data memory device of order overlapping function and revises existing design because of need, and expensive problem is arranged, so still belong to only a few.In addition, a data transmission system may comprise a plurality of data memory devices, if avoid the waste of transfer resource and make each data memory device all have order overlapping function, cost then increases along with the increase of the data memory device number that connects.And this order overlapping function need increase the time of unit state conversion, even if should can be left in the basket switching time, will control or during access hard disk machine 16 when main frame 14, still may have CD-ROM drive 18 the time apart from 22 or the time apart from 26 delay, and can't reach real-time.
If the data transmission system of application drawing 2,, be connected to Winchester disk drive 16 and CD-ROM drive 18 because of console controller is by two ata bus host side control interfaces 15 and 21 independently.When 14 pairs of CD-ROM drives 18 of main frame are controlled or data access and when delay is arranged, still can be directly by another ata bus host side control interface 21 independently, Winchester disk drive 16 is controlled or data access, and need not be arranged extra time delay.Though so can solve 14 pairs in the main frame problem that order postpones of meeting sb. at the airport firmly, but the order of 14 pairs of Winchester disk drive 16 of main frame and CD-ROM drive 18 has been distributed to two independently ata bus host side control interfaces 15 and 21, concerning individual other ata bus host side interface, its utilization rate is lower than the ata bus host side interface 15 in the data transmission system of Fig. 2.Concerning main frame 14, because of need increase by one group of additionally ata bus host side interface 21 independently, except that need are revised the design of existing main frame 14, when if main frame 14 is a triangular web chip, because of need increase by one group of complete ata bus host side interface, and need increase the output of chip pin position, and increase encapsulation and cost of processing.
Therefore, develop a kind of can be when console controller only has a single ata bus host side interface, two or more have the device of ata bus device end interface in connection, when the device that is connected need not have order overlapping function, can on ata bus, carry out the data transmission system of multitask access (multitask), avoiding the waste of ata bus host side interface transfer resource, and guarantee to be an important problem to the real-time of some device control and data access wherein.
Summary of the invention
Fundamental purpose of the present invention provides a kind of waste of avoiding ata bus (advanced technologyattachment bus) transfer resource, and guarantees the data transmission system of the real-time of some data memory device control and data access wherein.
Another fundamental purpose of the present invention need not used the data memory device with order overlapping function for providing a kind of, can carry out the data transmission system of multitask access (multitask) on ata bus.
According to one embodiment of the invention, the invention provides a kind of data transmission system, comprise a console controller with single ata bus host side interface, have ata bus device end interface first and 1 second data memory device, connect the ata bus connecting line of this device and single switch (single switcher).
This ata bus host side interface can be gone into (programmed input/output via the different program-controlled output of transmission speed, PIO) pattern, or a direct memory access (direct memoryaccess, DMA) pattern is carried out the transmission of order (commands) and data (data).This ata bus host side interface also comprises one group of chip select signal (a set of chip select signals) output.
This first and this second data memory device be connected with this console controller via this ata bus.Wherein first data memory device is to go into pattern with this program-controlled output to transmit.
This switch can be divided into the corresponding chip select signal of at least two groups with this group chip select signal switching from this console controller, to transfer to first and second data memory device via corresponding signalling channel (signal channel) respectively.This switch only allows wherein at every turn, and a signalling channel keeps unimpeded.
After this console controller begins for next first order of this first data memory device, when console controller does not send chip select signal, and the ata bus device end interface of first data memory device is not when being in this direct memory access pattern, this switch one channel selecting signal (channel selection signal) that can transmit according to this console controller then, this group chip select signal is switched to other signalling channel, so that this console controller is not before the execution of this first order is finished as yet, needn't interrupt the execution of this first order, or change the executing state of first data memory device, and can be directly for next second order of this second data memory device.
If there is the 3rd data memory device to exist, and this console controller is controlled this device or the priority level of data access is identical with first data memory device, that is work as main frame at control or access first data memory device, do not need to control simultaneously or during access the 3rd data memory device, it is online then the 3rd data memory device and first data memory device can be connected in same ata bus signal transmission.
Compared to known technology, data transmission system of the present invention need not used the data memory device with order overlapping function, promptly can only have on the console controller of single ata bus host side interface, two or more data memory devices be carried out the data transmission system of multitask access (multitask) one.And not only meet the consideration of cost factor according to data transmission system of the present invention, and can be by the effect of performance multitask access promoting the usefulness of data transmission, and guarantee real-time to the order of high priority device.
Can be about the advantages and spirit of the present invention by being further understood below in conjunction with the detailed description of accompanying drawing to invention.
Description of drawings
Fig. 1 is the synoptic diagram of given data transmission system 10.
Fig. 2 is the synoptic diagram of given data transmission system 20.
Fig. 3 is the Winchester disk drive 16 and the synoptic diagram of CD-ROM drive 18 according to sequential operation of Fig. 1.
Fig. 4 can carry out the synoptic diagram of the data transmission system 40 of multitask access on ata bus for the present invention.
Fig. 5 is first and second data memory device 46,48 synoptic diagram according to sequential operation of Fig. 4.
Fig. 6 is the various standard signals of ata bus.
Fig. 7 is the various standard definition of command area block register.
Fig. 8 is the various standard definition of control zone block controller.
Fig. 9 is the synoptic diagram of another embodiment of the present invention data transmission system 41.
The drawing reference numeral explanation
10,20 given data transmission systems
12,13,44a, 44b ata bus signal transmssion line
14,51,53 main frames, 16 Winchester disk drive
18 CD-ROM drives
17,19 ata bus device end interfaces
15,21 ata bus host side interfaces
In 22,28 whens order, are apart from 24, the 30 grades distance of biding one's time
42 console controllers, 46 first data memory devices
48 second data memory devices, 50 switchs
52a, 52b chip select signal 58 first signalling channels
59 signalling channels, 60 secondary signal passages
61,79 incomplete ata bus 62 channel selecting signals
T65 device ready time point 70 first interrupt request singals
Ready signal is gone in 74 outputs of 72 second interrupt request singals
76 first outputs are gone into ready signal 78 second outputs and are gone into ready signal
Embodiment
See also Fig. 4, Fig. 4 can carry out the multitask access for the present invention on ata bus (advanced technology attachmentbus) data transmission system 40 synoptic diagram.Data transmission system 40 comprises console controller (host controller) 42, two ata bus signal transmssion line 44a and the 44b with ata bus host side interface 49, has first data memory device 46 of ata bus device end interface, and second data memory device 48, and a single switch 50 (single switcher).In the present embodiment, the number of data memory device is two.Also can be according under aforesaid condition, connect onlinely at same ata bus signal, connect two data memory device simultaneously, or increase the signalling channel of switch, allow whole data transmission system connect three or above data memory device.
The function of console controller 42 is with the console controller 14 of Fig. 1, having single ata bus host side interface places among the main frame 51, can be used to the different program-controlled output of transmission speed and go into pattern (programmed input/output mode, PIO mode) or a direct memory access pattern (directmemory access mode, DMA mode), and can issue an order to data storage device 46,48, to control or data access.If the needs in the side circuit design are arranged, console controller 42 can be integrated in the single chip with switch 52, and channel selecting signal 62 can be produced automatically by a logic, or produces via the output signal of a software-controllable system, with control switch 50.
Ata bus signal transmssion line 44a and 44b can be used to carry out program-controlled output and go into pattern (programmed input/output mode, PIO mode) order (commands) is transmitted with data (data), or carries out the data transmission of direct memory access pattern (direct memory access mode).And the signal that ata bus signal transmssion line 44a and 44b are transmitted respectively comprises one group of chip select signal 58 and 60.
First data memory device 46 and second data memory device 48 are connected with main frame 51 via ata bus signal transmssion line 44a and 44b.Wherein, the control of one of them device in 42 pairs of these two data storage devices 46,48 of console controller and data access priority level be than another height, and the lower data memory device of another data access priority level must be gone into pattern with this program-controlled output and transmitted.In the present embodiment, first data memory device 46 is a CD-ROM drive, and second data memory device 48 is a Winchester disk drive.With regard to General System was used, the exectorial speed of Winchester disk drive was far faster than the exectorial speed of CD-ROM drive, and main frame to the control of Winchester disk drive and privilege of access grade than the CD-ROM drive height.Therefore in the present embodiment, first data memory device 46 is gone into pattern with this program-controlled output and is transmitted, and second data memory device 48 then can use this program-controlled output to go into pattern, or this direct memory access pattern (DMA mode).And the priority level of the control of 42 pairs second data memory devices 48 of console controller and data access is higher than first data memory device 46.
As shown in Figure 4, in main frame 51 inside, the ata bus host side interface 49 of console controller 42 is a complete ata bus host side interface, and the output of this interface is gone into signal and can be divided into chip select signal 52, and an incomplete ata bus host side interface signal 61.After chip select signal 52a after signal 61 and the switching or the chip select signal 52b combination, can be considered as a complete ata bus host side interface signal respectively, ata bus signal transmssion line 44a and 44b be can pass through, first data memory device 46 and second data memory device 48 transferred to.
In data transmission system 40, after console controller 42 beginnings are for 46 next first order of first data memory device, console controller 42 can not send this group chip select signal 52, and first data memory device 46 is not when being in this direct memory access pattern, switch 50 channel selecting signal 62 (channel selection signal) that can transmit according to console controller 42 then, chip select signal 52 is switched to second group of chip select signal 52b by first group of chip select signal 52a, so that console controller 42 is not before the execution of this first order is finished as yet, needn't interrupt the execution of this first order, or change the command execution state of this device, and can be for next second order of this second data memory device.Channel selecting signal 62 does not belong to one of standard signal of ata bus.
See also Fig. 5, and the known technology of comparison diagram 2.Fig. 5 is first and second data memory device 46,48 synoptic diagram according to sequential operation of Fig. 4.Among Fig. 5, axis T is a time shaft; The different operating that on behalf of first data memory device 46, axis DVD carry out according to time sequencing; The different operating that on behalf of second data memory device 48, axis HDD carry out according to time sequencing.The time represent console controller 42 second data memory device 48 to be controlled or data transmission respectively apart from A, B, C, D, E, F, G, H in the different periods, also respectively comprised one section order (CMD), waited for (WAIT), and distance when transmitting (XFER).
According to the present invention, console controller 42 can utilize first data memory device, 46 grades to bide one's time during 24, second data memory device 48 is controlled or data transmission, with strive for as Fig. 5 the time apart from the timely transfer resource during the E of C.
In addition, the data transmission system 40 of Fig. 4 further can be when the order of first data memory device 46 apart from 22 and during transmission apart from 26 during, preferentially second data memory device 48 is selected, in real time it is controlled or data transmission.Its method is optionally sent channel selecting signal 62 by console controller 42 then as previously mentioned, to select corresponding secondary signal passage 60.As shown in Figure 5, main frame can suspend the order of first data memory device or data transmission, preferential second data memory device 48 of selecting, it is controlled or data transmission, as the time apart from B in time apart from G, continue again afterwards first data memory device 46 is carried out uncompleted control of institute or data transmission.With this embodiment, just can when need control or access second data memory device, console controller 42 carry out this operation immediately, and not be subjected to the command execution state of first data memory device or the influence of time length.
In addition, the time in 24, when console controller 42 is waiting for that first storage device is ready, console controller 42 can send channel selecting signal 62 to switch 50 by continuing, so that switch 50 constantly switches between two signalling channels, make console controller 42 learn whether first data memory device 46 whether after ready (device ready), begins to carry out data transmission to first data memory device with decision.As shown in Figure 5, by continuing to send channel selecting signal 62, console controller 42 can learn that first data memory device 46 is ready after a device ready time point T65, and prepares to carry out the transmission of data for first data memory device 46.If first data memory device 46 is not ready as yet, but console controller switchback second data memory device carries out Next Command to it, to strive for the more data transfer resource, as the time apart from D in time apart from F.
As for striving for the more data transfer resource, main frame also can not be in the following time of state of direct internal memory transmission at second data memory device, in the time during wait (WAIT) in G apart from during, after switching back the data transmission that first data memory device carries out a period of time, switchback second data memory device carries out data transmission again.
If desire realizes making console controller before the execution of this first order is not finished as yet, needn't interrupt the execution of this first order, and can be for the purpose of next second order of this second data memory device, the given data transmission system needs first data memory device to possess order overlapping function (a commandoverlapped feature).
Order overlapping function (a command overlapped feature) is meant when a certain described data memory device needs more time when finishing the execution of order, this order overlapping function makes this data memory device can carry out a bus to disengage (bus release) operation, and makes other data memory device be connected in this ata bus to be used by console controller 42.But in order and data transmission procedure, and can not be interrupted and switch to other data memory device.In the data transmission system 40 of the present invention, first data memory device 46 and second data memory device 48, need not possess this order overlapping function, and by above-mentioned set-up mode of the present invention, data transmission system 40 can be in the arbitrary stage in the implementation of first order, for second order under second data memory device.
See also Fig. 6, Fig. 6 is the various standard signals of ata bus.Among Fig. 6 four row (row) are represented various standard signals according to the direction that signal transmits respectively.The various various signals that are sent to data memory device by console controller 42 of the first row record of Fig. 6.In the data transmission system 40 of Fig. 4, chip select signal 52 comprises a CS0 signal and a CS1 signal of ata bus standard.Whether CS0 signal and CS1 signal are one group and are sent to the wherein signal of a data memory device end by console controller 42 ends, in order to define this data memory device should be by receiving the signal that is transmitted on its ata bus device end interface.
See also Fig. 7, Fig. 8 and Fig. 4, Fig. 7 is that various standard definition, Fig. 8 of command area block register defines for the various standards of control zone block controller.Data transmission system 40 shown in Figure 4, described data memory device 46,48 all include a plurality of outputs and go into register (I/O registers), as Fig. 7 and Fig. 8, will order or data are written into described output and go in the register for console controller 42.Console controller 42 writes described output by ata bus with various signals goes among the register, with selecting apparatus 0 or install 1, and the order of device after selected assigned, the storage of data with read.
As shown in Figure 6, ata bus also comprises a direct memory request signal (DMARQ signal), an interrupt request singal (INTRQ signal) and exports ready signal (IORDY signal).Directly memory request response signal (DMACK signal) is the signal that is sent to the data memory device end by console controller 42 ends.DMARQ signal, INTRQ signal and IORDY signal are the signals that is sent to console controller 42 ends by the data memory device end.
In this data transmission system, only the data memory device that right of priority is high can use the DMA pattern, so device signal output DMARQ there is no collision problem.The INTRQ signal then can be gone into register by output and be controlled and only allow the device of a priority level use simultaneously.If console controller can provide an extra INTRQ signal input, then two priority levels of height all can use the output of INTRQ signal simultaneously.The use of IORDY signal is then different because of the device of low priority.If this device does not send the IORDY signal when not receiving the chip select signal that main frame sends, the IORDY of then high and low priority level device exports and then can not conflict mutually.If not, then console controller can use one need not use the program-controlled output of IORDY to go into pattern (PIO mode) than low speed to this device, to avoid the IORDY output conflict of high and low priority level device.If main frame or switch can provide the switching channel of one group of extra IORDY signal, then all devices all can go under the pattern to use in all program-controlled output.
See also Fig. 9, Fig. 9 is the synoptic diagram of another embodiment of the present invention data transmission system 41.Compared to the data transmission system 40 of Fig. 4, the data transmission system 41 of Fig. 9 has further utilized the interrupt request singal (INTRQ signal) of the listed standard ata bus of Fig. 6 and output to go into ready signal (IORDYsignal).
In data transmission system shown in Figure 9 41, console controller 42 provides the input of two device interrupt request singals, one first interrupt request singal 70 and one second interrupt request singal 72.First interrupt request singal 70 is sent to console controller 42 from first data memory device 46.Second interrupt request singal 72 is sent to console controller 42 from second data memory device 78.Console controller 42 increases the benefit of second interrupt request singal input, be that console controller 42 does not need as previously mentioned, before waiting for that first data memory device is ready, continue between first data memory device and second data memory device, to switch, to strive for more transfer resource by switch 50.So only need to learn first data storing dress data ready by the input of device interrupt request singal, thereby can reduce the device blocked operation of console controller, and increase the control of second data memory device or the operation of data access, further promote the effective utilization of ata bus resource.If console controller 42 does not provide the input of two device interrupt request singals, also can provide input of two device interrupt request singals and the output of a device interrupt request singal by switch 50.When switch 50 receives that channel selecting signal switches chip select signal, also switch corresponding device interrupt request singal simultaneously and input to its interrupt request singal output.Can allow 42 other pick-up units of console controller whether send interrupt request singal though this makes mode in fact, console controller 42 still must continue to switch in different interchannels, just can obtain this state.
In data transmission system shown in Figure 9 41, switch 50 also can provide two outputs to go into the ready signal input, and ready signal 76 is gone in one first output and ready signal 78 is gone in one second output.First output is gone into ready signal 76 and is sent to switch 50 from first data memory device 46.Second output is gone into ready signal 78 and is sent to switch 50 from second data memory device 48.As previously mentioned, after switch 50 increases the switching of exporting ready signal, even if a certain device is not receiving that chip select signal also can export under the situation of going into ready signal, also can allow two devices go under the pattern to use in all program-controlled outputs simultaneously, with the compatibility issue of avoiding various devices to use.
And the incomplete ata bus 79 of main frame 53 inside (the second uncomplete ATA bus) for do not include chip select signal (CS0, CS1), output goes into ready signal (IORDY), and the ata bus of interrupt request singal (INTRQ).
Data transmission system 40 compared to Fig. 4, the data transmission system 41 of Fig. 9 for adapt to first interrupt request singal 70, second interrupt request singal 72, ready signal 76 is gone in first output and ready signal 78 is gone in second output, needing increases the input of second interrupt request singal in console controller, or in the signalling channel that switch 50 is switched, increase output go into ready signal switching.But this two extra signal or device that increases, and nonessential, also do not need to use simultaneously.Only need according to system the bus service efficiency, or the characteristic of institute of system coupling arrangement is with compatible, or actual system need give use as one thinks fit.
Compared to known technology, data transmission system of the present invention need not used the data memory device with order overlapping function, also need not increase by second group of independently ata bus interface host side interface, can on ata bus, carry out multitask access (multitask), therefore can avoid the waste of ata bus transfer resource, and shorten the command execution time delay of higher priority level device.According to the present invention, data transmission system not only meets the consideration of cost factor, and can be by the effect of bringing into play the multitask access to promote the usefulness and the real-time of data transmission.
By the above detailed description of preferred embodiments, be to wish to know more to describe feature of the present invention and spirit, and be not to come category of the present invention is limited with above-mentioned disclosed preferred embodiment.On the contrary, its objective is that hope can contain in being arranged in of various changes and the tool equality claim category of the present invention.Therefore, the category of claim of the present invention should be done the broadest explanation according to above-mentioned explanation, contains the arrangement of all possible change and tool equality to cause it.
Claims (8)
1. data transmission system comprises:
One console controller, this main frame control device comprises an ata bus host side interface, and a channel selecting signal; This ata bus host side interface can be gone into pattern via the different program-controlled output of transmission speed at least, or a direct memory access pattern is used for carrying out the transmission of order or data, and this ata bus interface comprises one group of chip select signal output at least;
One single switch, this switch can switch the chip select signal that is divided at least two groups with this group chip select signal from this console controller, and the channel selecting signal that this switch can transmit according to this console controller only allows wherein the chip select signal output of one group of chip select signal and console controller keep unimpeded;
At least two data memory devices with ata bus device end interface, can be via this ata bus and this switch, be connected with this console controller, in this data memory device, have the right of priority height of the right of priority of a data storage device at least than other data memory device, and the data memory device of different priority levels is connected respectively to the difference group chip select signal output of this switch, but not the data memory device of highest priority grade is gone into pattern with this program-controlled output and carried out data transmission; And
Wherein, when this console controller during at access or the lower data memory device of control right of priority, console controller can be under the state that does not change the lower data memory device of this right of priority, control this switch, do not send chip select signal at console controller, and the lower data memory device of this right of priority is non-when being in this direct memory access pattern, switch to the chip select signal of the data memory device that connects higher priority level, the data memory device of higher priority level is controlled or data access.
2. data transmission system as claimed in claim 1, wherein the output of the device interrupt request singal of the data memory device of different priority levels can be connected to the interrupt request singal input of the ata bus interface of this console controller, and in these data memory devices, down, a data storage device operative installations interrupt request singal is only arranged at one time.
3. data transmission system as claimed in claim 1, wherein this switch has the input of two device interrupt request singals at least, and device look-at-me output, be connected to the interrupt request singal input of the ata bus interface of this console controller, wherein this switch can be according to this channel selecting signal, only allow one of them device interrupt request singal import, keep unimpeded with the output of device interrupt request singal, and the device interrupt request singal of the data memory device of different priority levels is connected to device interrupt request singal inputs different on this switch.
4. data transmission system as claimed in claim 1, wherein this console controller has two interrupt request singal inputs at least, and the interrupt request singal of the data memory device of different priority levels is connected to interrupt request singal inputs different on this console controller.
5. data transmission system as claimed in claim 1, wherein this switch has at least two outputs to go into the ready signal input, and ready signal output is gone in an output, the ready signal input is gone in the output that is connected to the ata bus interface of this console controller, wherein this switch can be according to this channel selecting signal, only allow one of them device output go into the ready signal input, go into ready signal output with output and keep unimpeded, and the output of the data memory device of different priority levels is gone into ready signal output and is connected to output different on this switch and goes into the ready signal input.
6. data transmission system as claimed in claim 1, wherein this console controller has at least two outputs to go into ready signal input, and the output of the data memory device of different priority levels is gone into ready signal output and is connected to output different on this console controller and goes into the ready signal input.
7. data transmission system as claimed in claim 1, wherein the data memory device of a low priority grade is being controlled or during data access when console controller, send this channel selecting signal at console controller, switch to the chip select signal of the data memory device that connects high priority level, the data memory device that is connected the high priority level on this group chip select signal is controlled or data access, and during the data memory device of waiting for this high priority level, when if the data memory device of this high priority level is not in direct internal memory transmission state, console controller can send this channel selecting signal again, switch to the passage of the data memory device that connects former low priority grade, proceed access or control to this device, data memory device up to this high priority level is in direct internal memory transmission state, send this channel selecting signal again to this switch, switch to the chip select signal of the data memory device that connects this high priority level of not finishing control or data access, continuation is carried out this control or data access program to the data storage device of this high priority level.
8. data transmission system as claimed in claim 1, wherein this console controller and this switch are integrated in the single chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100420610A CN1322410C (en) | 2004-04-29 | 2004-04-29 | Data transmission system capable of carrying out multitask access on ATA bus |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100420610A CN1322410C (en) | 2004-04-29 | 2004-04-29 | Data transmission system capable of carrying out multitask access on ATA bus |
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| CN1690945A CN1690945A (en) | 2005-11-02 |
| CN1322410C true CN1322410C (en) | 2007-06-20 |
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| CNB2004100420610A Expired - Fee Related CN1322410C (en) | 2004-04-29 | 2004-04-29 | Data transmission system capable of carrying out multitask access on ATA bus |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100447714C (en) * | 2005-11-04 | 2008-12-31 | 英业达股份有限公司 | Online switching interfaces of peripheral devices in multitask mode computer |
| US8527667B2 (en) | 2009-09-24 | 2013-09-03 | Maishi Electronic (Shanghai) Ltd | Apparatuses and methods for transferring data |
| CN102222054A (en) * | 2010-04-19 | 2011-10-19 | 凹凸电子（武汉）有限公司 | Data transmission device, method and controller |
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