CN1316387C - Series interface bus communications controller - Google Patents
Series interface bus communications controller Download PDFInfo
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- CN1316387C CN1316387C CNB021408513A CN02140851A CN1316387C CN 1316387 C CN1316387 C CN 1316387C CN B021408513 A CNB021408513 A CN B021408513A CN 02140851 A CN02140851 A CN 02140851A CN 1316387 C CN1316387 C CN 1316387C
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Abstract
The present invention relates to a series interface bus communication controller which comprises an interface part, a bus part and a communication logic control part, wherein the interface part comprises an interface end series asynchronous receiving and transmitting unit and a data buffering processing unit 1; the bus part comprises a bus end series asynchronous receiving and transmitting unit and a data buffering processing unit 2; the communication logic control part comprises a communication control unit, an error count, an error processing circuit and a carrier interception multi-address access conflict monitoring circuit. On the premise of satisfying a communication requirement for household control systems, the present invention fully uses the idle resource of the existing control object, reduces the manufacturing cost of the bus communication controller, and largely reduces the total cost of the household control systems. The present invention has the characteristics of simple structure, low manufacturing cost, low application cost and good application effect, and can be widely applied to the household control systems and similar control systems.
Description
Technical field
The present invention relates to a kind of bus communication control device, the universal serial bus mode control device of usefulness of communicating by letter between particularly a kind of single-chip microcomputer and single-chip microcomputer or single-chip microcomputer and the personal computer.
Background technology
At present, existing single-chip microcomputer and single-chip microcomputer, or the multiple access communication of single-chip microcomputer and PC personal computer generally is to utilize parallel interface to carry out serial bus communication.Used bus communication controller (claiming the bus communication control chip again) in communication substantially all is by the design of synchronous communication working method, is used for industry more.It is fast that this parallel interface bus communication controler has data rate, and antijamming capability is strong, and fault tolerance is strong, and the reliability height can be than the characteristics of working under the rugged surroundings.But the cost of manufacture of this bus communication controller is higher.In present home control system, controlling object is various electrical appliances (as TV, refrigerator, micro-wave oven etc.) that single-chip microcomputer is housed or by the electrical appliance (as by the electric light under the Single-chip Controlling, electric furnace, socket etc.) of single-chip microcomputer Centralized Monitoring, system environments is better relatively, and is lower to the requirement of data transmission.In the control system of home control system or similar application environment, use this parallel interface bus communication controler, obviously on function, have redundancy and cost higher.In the existing in addition home control system, the parallel port of the single-chip microcomputer on each controlling object all requires occupied because of internal control basically, therefore adopt this parallel interface bus communication controler, also to transform under many situations existing controlling object, this transformation had both increased the cost of home control system, made troubles for again controlling object manufacturer.Adopt parallel interface bus communication controler line more besides, complicated again.
Summary of the invention
The objective of the invention is to, a kind of communication controller of serial interface bus is provided.It is to use serial line interface to carry out bus communication.It both can significantly reduce the cost of manufacture of bus communication controller and the total cost of home control system; Can satisfy the communicating requirement of home control system again, adapt to existing controlling object, and the resource of existing controlling object is more made full use of.
The present invention is achieved in that a kind of communication controller of serial interface bus, and its formation comprises the interface section, bus portion and communication logic control section; It is characterized in that: the formation of interface section comprises interface end asynchronous serial Transmit-Receive Unit that joins with Asynchronous Serial Interface and the data buffering processing unit 1 that joins with this unit; The formation of bus portion comprises bus end asynchronous serial Transmit-Receive Unit that joins with the asynchronous serial bus interface and the data buffering processing unit 2 that joins with this unit, but data buffering processing unit 2 also joins and bi-directional transfer of data with data buffering processing unit 1; The communication logic control section comprises, the carrier sense multiple access conflict monitoring circuit that joins with the asynchronous serial bus interface, the error count and the fault processing circuit that join with carrier sense multiple access conflict monitoring circuit, other respectively constitutes the communication control unit that the unit joins with error count and fault processing circuit and serial interface bus controller.
In the above-mentioned communication controller of serial interface bus, the formation of described interface end asynchronous serial Transmit-Receive Unit comprises, the interface end asynchronous serial transceiver that joins with Asynchronous Serial Interface, the string that joins with this transceiver in the lump change-over circuit and and a string change-over circuit; The formation of described data buffering processing unit 1 comprises that interface reception data buffer and interface send the data buffer; The formation of described bus end asynchronous serial Transmit-Receive Unit comprises, with the bus end asynchronous serial transceiver that the asynchronous serial bus interface joins, join with this transceiver and a string change-over circuit and the change-over circuit in the lump of going here and there; The formation of described data buffering processing unit 2 comprises that bus sends data buffer and bus reception data buffer: described communication control unit comprises, the transmit control register heap, add up and checking circuit, the cyclic redundancy code generation circuit, reception control register heap adds up and generative circuit the address check circuit, the CRC circuit, the time-out check circuit.
In the aforesaid communication controller of serial interface bus, described interface reception data buffer comprises data buffer 1, interface buffer control circuit 1; Interface sends the data buffer and comprises data buffer 2, connects 13 buffer zone control circuits 2; Bus sends the data buffer and comprises data buffer 3, bus buffer district control circuit 1; The bus reception data buffer comprises data buffer 4, bus buffer district control circuit 2; Receive that the control register heap comprises frame tagged word register file 2, connects 13 transmit control registers heap, bus receives control register heap, answering circuit 2 and answering circuit 4; The transmit control register heap comprises that frame tagged word register file 1, interface receive control register heap, bus transmit control register heap, answering circuit 1 and answering circuit 3; Interface end asynchronous serial transceiver comprises that interface asynchronism transceiver, frame format packeting circuit 1, frame format unpack circuit 1; Bus end asynchronous serial transceiver comprises that bus asynchronism transceiver, frame format packeting circuit 2, frame format unpack circuit 2.
Compared with the prior art, the present invention provides a kind of bus communication controller that adopts serial line interface to carry out bus communication according to the communication characteristics of home control system.The present invention has made full use of the slack resources of existing controlling object under the prerequisite that satisfies the home control system communicating requirement, need not transform existing controlling object, and wiring is simple.Not only reduce the cost of manufacture of bus communication controller, and reduced the total cost of home control system significantly.The present invention has simple in structure, and cost of manufacture is low, and application cost is low, the integrated application good effectiveness.Can be widely used in the control system LAN (Local Area Network) and device of home control system and similar application environment.
Description of drawings
Accompanying drawing 1 is the circuit structure block diagram 1 of serial interface 1:3 bus communication controller;
Accompanying drawing 2 is circuit structure block diagrams 2 of communication controller of serial interface bus;
Accompanying drawing 3 is circuit structure block diagrams 3 of communication controller of serial interface bus.
Embodiment
Embodiment: the formation of communication controller of serial interface bus comprises the interface section, bus portion and communication logic control section.As shown in Figure 1, the formation of the interface section data buffering processing unit 1 that comprises interface end asynchronous serial Transmit-Receive Unit and join with it; The data buffering processing unit 2 that the formation of bus portion comprises bus end asynchronous serial Transmit-Receive Unit and joins with it; The communication logic control section comprises communication control unit, error count and fault processing circuit, carrier sense multiple access conflict monitoring circuit.Again as shown in Figure 2, the formation of described interface end asynchronous serial Transmit-Receive Unit can comprise interface end asynchronous serial transceiver, the string that joins with transceiver in the lump change-over circuit and and a string change-over circuit; The formation of described data buffering processing unit 1 can comprise that interface reception data buffer and interface send the data buffer; The formation of described bus end asynchronous serial Transmit-Receive Unit can comprise bus end asynchronous serial transceiver, the also a string change-over circuit that joins with it and the change-over circuit in the lump of going here and there; The formation of described data buffering processing unit 2 can comprise that bus sends data buffer and bus reception data buffer; Described communication control unit comprises that the transmit control register heap adds up and checking circuit, and the cyclic redundancy code generation circuit receives the control register heap, adds up and generative circuit address check circuit, CRC circuit, time-out check circuit.Again as shown in Figure 3, described interface reception data buffer can comprise data buffer 1, interface buffer control circuit 1: interface sends the data buffer can comprise data buffer 2, interface buffer control circuit 2; Bus sends the data buffer can comprise data buffer 3, bus buffer district control circuit 1: the bus reception data buffer can comprise data buffer 4, bus buffer district control circuit 2; Receive the control register heap and can comprise that frame tagged word register file 2, interface transmit control register heap, bus receive control register heap, answering circuit 2 and answering circuit 4; The transmit control register heap can comprise that frame tagged word register file 1, interface receive control register heap, bus transmit control register heap, answering circuit 1 and answering circuit 3; Interface end asynchronous serial transceiver can comprise that interface asynchronism transceiver, frame format packeting circuit 1, frame format unpack circuit 1; Bus end asynchronous serial transceiver can comprise that bus asynchronism transceiver, frame format packeting circuit 2, frame format unpack circuit 2.Whole communication controller of serial interface bus can be made into an integrated circuit (IC) chip.Can realize error count and fault processing function with the fatal error testing circuit shown in the accompanying drawing 3 during concrete the making, and a string change-over circuit and go here and there in the lump that change-over circuit can unpack in the circuit in frame format packeting circuit and frame format in merger.
Because in the existing home control system, not idle not the using of full duplex serial communication interface that a programmable UART of having (asynchronism transceiver) function is all arranged in the single-chip microcomputer of each controlling object, therefore with communication controller of serial interface bus therewith communication interface join, both need not transform existing controlling object, utilized the idle resource of controlling object again, and adopted the serial interface communication mode, line has only several, and adopt the parallel interface communication mode, then need tens.
The principle of work of communication controller of serial interface bus: the mode that equipment adopts universal asynchronous serial communication sends to the Asynchronous Serial Interface IRX of communication controller of serial interface bus and contains initial symbol, data length, control command word, destination address, data block, verification and and the frame sequence of end mark.Through communication controller of serial interface bus internal interface end asynchronous serial transceiver, be reduced into 8 bit stream, become parallel data and deposit the interface reception data buffer in by going here and there in the lump change-over circuit.Simultaneously, send and add up and checking circuit, determine whether the transmission data are correct, send the transmit control register heap the result.The transmit control register heap extracts control command word, destination address and transmission data from the interface reception data buffer, and deposit bus in and send the data buffer, add local address, by the cyclic redundancy code generation circuit check code is deposited in check field simultaneously, and organize the bus transfer frame.(the bus transfer frame is the frame sequence with initial symbol, destination address, local address, control command word, length, data block, check field and end mark.) according to different control word decisions data to be sent to bus be to adopt the broadcast mode or the mode of intelligence transmission for transmit control register heap, start to send.The signal that collision detection provides according to carrier sense multiple access when being the bus free time, allows to send, and then starts to send.Bus sends the data buffer and send also a string change-over circuit to form serial sequence data.Send bus transfer frame through asynchronous serial bus interface BTX to communication bus by bus end asynchronous serial transceiver at last.Adopting the mode of " listening while saying " to determine whether to send successfully in the process of transmitting, specifically is that BRX by the asynchronous serial bus interface receives more whether the bit sequence of the bit sequence that sends to bus and transmission is input to the carrier sense multiple access collision detection circuit consistent.If consistent, then continue to send; If inconsistent then notify transmit control register heap and error count fault processing circuit immediately, stop transmission.If error count is overflowed, then carry out fault processing, stop to send, producing mismark etc.
On the contrary, if communication bus is sent a transmission frame sequence, at first be input to bus end asynchronous serial transceiver through asynchronous serial bus interface BRX, be reduced to 8 bit stream, send serial-parallel conversion circuit, CRC circuit, time-out check circuit n string then to deposit the bus reception data buffer in after the conversion in the lump; The cyclic redundancy check circuit obtains sending reception control register heap behind the result, determines whether transmission frame is effective: the signal whether the time-out check circuit then provides frame sequence to finish, and whole receiving circuit can accurately be resetted, enter new wait accepting state.The address check circuit then extracts DAF destination address field and local address relatively from the bus reception data buffer, determine to mail to local transmission frame.Destination address, control command word and data block deposit interface transmission data buffer in the control register heap copy bus reception data buffer by receiving.Simultaneously by add up and generative circuit obtain verification and, also deposit interface in and send the data buffer.Receive the control register heap and start the interface transmission, interface sends the data buffer data and forms 8 bit streams through parallel-to-serial converter, sends into interface end asynchronous serial transceiver and mails to equipment through Asynchronous Serial Interface ITX.
Frame tagged word register file 1 is the result who unpacks according to frame, stores the tagged word of representative frame into the relevant register heap, as command word, frame length, source address, destination address, local update address, local update control register etc.Interface transmit control register heap is when control interface transmission interface buffer zone control circuit 2 starts work; Judge that interface sends condition, start to send; Control adds up and generates (adding up and generation module); Control interface frame format packing (frame format packing 1).It is that the verification received frame is corrected errors that bus receives the control register heap, judges frame head, postamble, judges Cyclic Redundancy Code (CRC module), judge information bit length, judge receive time-out (time-out check module), by source address, destination address, the judgment frame sending direction; The audit interface state judges whether to move frame information to interface; When control bus reception data buffer control module 2 starts work.The result that frame tagged word register file module 2 unpacks according to frame stores the tagged word of representative frame into the relevant register heap, as command word, frame length, source address, destination address, local update address, local update control register etc.It is that the verification received frame is corrected errors that interface receives the control register heap, judge frame head, postamble, judge and to add up and (add up and check module), judgment frame length, judge receive time-out (time-out check module): the supervision bus state, judge whether to the bus translation frame information: when control interface buffer zone control circuit 1 starts work.Bus transmit control register heap is when control bus buffer zone control module 1 starts work: judge that bus sends condition, start to send; The Control Circulation redundanat code generates (Cyclic Redundancy Code generation module); Control bus frame format packing (frame format packetization module).The data buffer comprises the interface reception data buffer, interface sends data buffer, bus reception data buffer, bus transmission data buffer 4 block RAMs, and every block size is 8*32bit.The buffer zone control circuit is used to produce read-write control signal, the read/write address of data buffer (RAM) and empties the buffer zone signal.The frame structure parse module is the characteristics according to dissimilar frame structures, and frame data are unpacked.The frame structure packetization module is the characteristics according to dissimilar frame structures, and frame data are packed.Asynchronism transceiver (UART) module is to receive and the standard of transmission start-stop type charcter topology start bit, 8 bit data positions and a position of rest.Sample frequency is ten sixths of interface baud rate.If the charcter topology mistake, interface end abandons automatically; The fatal error of then carrying out bus end detects (fatal error detection module) and replys judge module: the acknowledgement frame that receives is handled accordingly; Check results to non-acknowledgement frame is replied processing accordingly; Chip is provided with frame is replied and warm reset (having only interface that this function is arranged); Start transmission transmission acknowledgement frame (having only bus that this function is arranged) according to bus acknowledge situation control interface.Carrier sense, collision detection module are used for the real-time listening bus, and address priority is judged in collision detection.The fatal error testing circuit is the charcter topology when set form when containing one or more non-tagmeme, then detects a form error, produces bus error (fatal error) when being accumulated to 128 form errors.And control interface transmit control register heap starts interface transmission transmission fatal error frame.
Claims (3)
1, a kind of communication controller of serial interface bus, its formation comprises the interface section, bus portion and communication logic control section; It is characterized in that: the formation of interface section comprises interface end asynchronous serial Transmit-Receive Unit that joins with Asynchronous Serial Interface and the data buffering processing unit 1 that joins with this unit; The formation of bus portion comprises bus end asynchronous serial Transmit-Receive Unit that joins with the asynchronous serial bus interface and the data buffering processing unit 2 that joins with this unit, but data buffering processing unit 2 also joins and bi-directional transfer of data with data buffering processing unit 1; The communication logic control section comprises, the carrier sense multiple access conflict monitoring circuit that joins with the asynchronous serial bus interface, the error count and the fault processing circuit that join with carrier sense multiple access conflict monitoring circuit, other respectively constitutes the communication control unit that the unit joins with error count and fault processing circuit and serial interface bus controller.
2, communication controller of serial interface bus according to claim 1, it is characterized in that: the formation of described interface end asynchronous serial Transmit-Receive Unit comprises, the interface end asynchronous serial transceiver that joins with Asynchronous Serial Interface, the string that joins with this transceiver in the lump change-over circuit and and a string change-over circuit; The formation of described data buffering processing unit 1 comprises that interface reception data buffer and interface send the data buffer; The formation of described bus end asynchronous serial Transmit-Receive Unit comprises, with the bus end asynchronous serial transceiver that the asynchronous serial bus interface joins, join with this transceiver and a string change-over circuit and the change-over circuit in the lump of going here and there; The formation of described data buffering processing unit 2 comprises that bus sends data buffer and bus reception data buffer: described communication control unit comprises, the transmit control register heap, add up and checking circuit, the cyclic redundancy code generation circuit, reception control register heap adds up and generative circuit the address check circuit, the CRC circuit, the time-out check circuit.
3, communication controller of serial interface bus according to claim 2 is characterized in that: described interface reception data buffer comprises data buffer 1, interface buffer control circuit 1; Interface sends the data buffer and comprises data buffer 2, connects 13 buffer zone control circuits 2; Bus sends the data buffer and comprises data buffer 3, bus buffer district control circuit 1; The bus reception data buffer comprises data buffer 4, bus buffer district control circuit 2; Receive that the control register heap comprises frame tagged word register file 2, connects 13 transmit control registers heap, bus receives control register heap, answering circuit 2 and answering circuit 4; The transmit control register heap comprises that frame tagged word register file 1, interface receive control register heap, bus transmit control register heap, answering circuit 1 and answering circuit 3; Interface end asynchronous serial transceiver comprises that interface asynchronism transceiver, frame format packeting circuit 1, frame format unpack circuit 1; Bus end asynchronous serial transceiver comprises that bus asynchronism transceiver, frame format packeting circuit 2, frame format unpack circuit 2.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB021408513A CN1316387C (en) | 2002-02-20 | 2002-07-05 | Series interface bus communications controller |
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| CN02113384.0 | 2002-02-20 | ||
| CN02113384 | 2002-02-20 | ||
| CNB021408513A CN1316387C (en) | 2002-02-20 | 2002-07-05 | Series interface bus communications controller |
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| CN1316387C true CN1316387C (en) | 2007-05-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101465839B (en) * | 2008-10-24 | 2012-07-04 | 北京蛙视通信技术有限责任公司 | Transmission control method and apparatus for serial data |
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| JP4173122B2 (en) * | 2004-09-03 | 2008-10-29 | 沖電気工業株式会社 | Communication control device, communication control method, node, and communication system |
| CN100461141C (en) * | 2005-03-22 | 2009-02-11 | 威盛电子股份有限公司 | Method for monitoring system bus and relative device |
| CN101620558B (en) * | 2008-07-01 | 2011-08-03 | 环旭电子股份有限公司 | General debugging-assistant device |
| CN108446243B (en) * | 2018-03-20 | 2021-11-26 | 上海奉天电子股份有限公司 | Bidirectional communication method and system based on serial peripheral interface |
| CN109284248A (en) * | 2018-08-23 | 2019-01-29 | 深圳柴火创客教育服务有限公司 | UART bus communication method, equipment and its functional module using UART bus communication |
| DE102019211980A1 (en) * | 2019-08-09 | 2021-02-11 | Robert Bosch Gmbh | Conflict detector for a subscriber station of a serial bus system and method for communication in a serial bus system |
| CN112468379B (en) * | 2020-11-03 | 2022-06-28 | 中国航空工业集团公司西安航空计算技术研究所 | Communication bus with node equal authority |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101465839B (en) * | 2008-10-24 | 2012-07-04 | 北京蛙视通信技术有限责任公司 | Transmission control method and apparatus for serial data |
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