CN1304922C - Circuit interface for high-speed CCD camera - Google Patents

Abstract

The present invention discloses a circuit interface used for a high speed charge coupling camera, which belongs to the field of data transmission devices. A USB2.0 is adopted as a data interface between a high speed camera and a computer, the USB2.0 is connected with a programmable logic device (CPLD) acting as a control sensor, and a bus of the USB2.0 is connected with a bus of the data address of a single-chip computer. In addition, an IO port of the CPLD is connected with a DMA port of the USB2.0, so the high speed transmission between the CPLD and the USB2.0 is realized. An FIFO is additionally expanded beyond an interface chip of the USB2.0, so acquisition cards of the system are left out. In this way, the cost is saved, and the system reliability is improved. Furthermore, the goal of avoiding USB2.0 from interrupting now and then in the transmission procedures resulting in data loss is achieved.

Description

The circuit interface that is used for high-speed CCD camera

Technical field

The invention belongs to the data transmission device field, particularly a kind of circuit interface that is used for high-speed CCD camera.

Technical background

CCD (charge-coupled image sensor) is a kind of electrooptical device, uses the integrated circuit technology manufacturing, mainly is made up of photosensitive unit, input structure, export structure.At present, CCD is widely used in equipment such as the digital camera, robotic vision system, video game machine, scanner, facsimile recorder in the security system, and can be used as the alternative method of film camera in uranology, spectroscopy and the crystallography research.Simultaneously CCD is also constantly opening up new application at traffic identification, TV and computer peripheral equipment, toy, wired and aspects such as RF video conference and Internet access device.

High-speed CCD is a class comparatively special in the various CCD products, and its frame per second can reach hundreds of even thousands of frame per second, is the strong instrument of research high speed processes.High-speed CCD camera is the product that development of semiconductor arrives certain phase, is emerging in recent years a kind of technology.The high-speed CCD chip is the core component of high speed camera, has only the fewer companies of a few countries to produce at present.By the characteristics of CCD as can be known, the CCD application system is if operate as normal, must be by means of the optical system of necessity, suitable peripheral drive circuit and some peripherals such as signal processing circuit and interface circuit, and interface circuit is a wherein very important part, and the image that interface circuit is taken high speed camera is exported to Computer Storage and handled.Can think that data interface circuit is the bridge between high speed camera and the computing machine.Data transfer rate is very high because high speed camera has, and general design is difficult to meet the demands, and the data-interface of high speed camera and PC normally adopts the special image capture card to connect and compose by the pci bus of PC at present.

Summary of the invention

The purpose of this invention is to provide a kind of circuit interface that is used for high-speed charge coupled camera.The data-interface of described high speed camera and PC is to adopt USB2.0 to constitute, it is characterized in that: described high-speed charge coupled camera adopts USB 2.0 interface chip ISP1581 as data-interface, and ISP1581 links to each other with the programmable logic device (CPLD) of making the control sensor; The initial configuration of ISP1581 adopts single chip computer AT 89S52 to realize, the data address bus of AT89S52 is linked to each other with the bus of ISP1581, and the IO mouth of CPLD linked to each other with the DMA mouth of ISP1581, CPLD is the DMA main frame, ISP1581 is the DMA slave, realizes the high speed DMA transmission between CPLD and the ISP1581.

Also and meet push-up storage FIFO, avoid losing of data with this, and when computing machine can't in time be taken data away, data are cushioned between described CPLD and the ISP1581.

The model of described CPLD is: M4A5-128/64.

The invention has the beneficial effects as follows and adopt USB2.0, thereby in system, saved capture card, promptly saved the reliability that cost has improved system again, realize high-speed transfer by CPLD as the interface between high speed camera and the computing machine.In addition, the present invention outside USB 2.0 interface chips additional extension FIFO, can reach like this and avoid in USB 2.0 transmission courses interrupting once in a while the loss of data that causes.

Description of drawings

Fig. 1 is USB 2.0 interface circuit connection layout.

Fig. 2 is USB 2.0 interface spread F IFO circuit diagrams.

The FIFO width mode of extension figure of Fig. 3 for adopting in USB 2.0 circuit.

Fig. 4 is the DMA sequential chart of ISP1581.

Embodiment

The invention provides a kind of circuit interface that is used for high-speed charge coupled camera, the data-interface of general high speed camera and PC is to adopt the special image capture card to connect and compose by the pci bus of PC.In USB shown in Figure 1 2.0 interface circuit connection layout, USB 2.0 interfaces adopt chip I SP1581 as data-interface, and ISP1581 links to each other with the programmable logic device (CPLD) of making the control sensor; The initial configuration of ISP1581 adopts single chip computer AT 89S52 to realize, the data address bus of AT89S52 is linked to each other with the bus of ISP1581, and the IO mouth of CPLD linked to each other with the DMA mouth of ISP1581, CPLD is the DMA main frame, ISP1581 is the DMA slave, realizes the high speed DMA transmission between CPLD and the ISP1581.ISP1581 has two sets of data interface: MCU (single-chip microcomputer) interfaces, high speed DMA (direct memory access) interface.The MCU interface is used to dispose the ISP1581 internal register, and initialization USB 2.0 communications are the communication than jogging speed; Start DMA interface and be used for high speed data transfer, control by CPLD; The model of CPLD is: M4A5-128/64.

In USB 2.0 interface spread F IFO circuit diagrams shown in Figure 2, between CPLD and ISP1581, also and meet push-up storage FIFO, avoid losing of data with this, and when computing machine can't in time be taken data away, data are cushioned.The digital picture that the high-speed CCD chip is photographed is sent to computing machine, and the data rate of the image sequence that photographs is 120Mbps, and because digital image stream itself requires the data transmission continous-stable.This just requires interface circuit to have the transmission speed greater than 120Mbps of continous-stable.Though USB 2.0 has the bandwidth of 480Mbps in theory.But because problem such as protocol overhead, its speed can not reach theoretical value far away, and because problem such as computer system is busy, and the DREQ of ISP1581 will step-down, of short duration interruption DMA transmission.This short interruption does not influence for non real-time transmission application, but will cause loss of data for real-time application.Therefore the extra push-up storage FIFO that adds in circuit transmits the unstable obliterated data problem that is caused thereby solved USB 2.0.FIFO model as buffering is IDT7206, is asynchronous operation type FIFO, i.e. the read-write of FIFO can be carried out simultaneously, does not need to consider the synchronous of read and write.The width of IDT7206 is 9bits, and the degree of depth is 16K.Because the DMA between CPLD and ISP1581 is 16bits, therefore need expand the width of FIFO, make it width and expand to 18bits, the actual 16bits that uses wherein, 2bits abandons in addition.In the width expander graphs of FIFO shown in Figure 3, the control of FIFO there are four road most important signal: WR, RD, FF, FE.WR is the FIFO write signal, and on the rising edge of WR, DATA IN bus data can be written into FIFO, and FIFO internal data pointer adds one automatically simultaneously.RD is the FIFO read signal, and on the rising edge of RD, the interior data of FIFO can be latched to DATA OUT bus and get on, and FIFO internal data pointer subtracts one automatically simultaneously.The read-write operation of FIFO can carry out simultaneously, and can not cause the confusion of the data pointer of FIFO inside.FF is the abbreviation of Full Flag, if the FIFO internal data has reached the limit of FIFO memory space, the FF signal can be put low level by FIFO, if continue to the FIFO write data this moment, data can not enter FIFO, and data can be lost automatically.EF is the abbreviation of empty sign, if the FIFO internal data all is read out, data pointer points to zero, and the EF signal can be put low level by FIFO, if continue from the FIFO read data this moment, the data on the FIFO output data bus are wrong.The interface line of ISP1581 and MCU has: 8 bit address data multiplex bus AD[0:7], address latch signal ALE, read enable signal RD, write enable signal WR, add the look-at-me INTn that an ISP1581 notice MCU removes read data.

In the DMA of ISP1581 shown in Figure 4 sequential.Single-chip microcomputer does not participate in high-speed transfer, and high-speed transfer realizes by the DMA (direct memory access) between CPLD#2 and ISP1581.CPLD#2 is the direct memory access main frame in the high-speed transfer process, and ISP1581 is DMA SLAVE.Transmission course is initiated by the ISP1581 as DMA SLAVE, and the DMA process is controlled by DMA MASTER.During the transmission beginning, at first send the DMA request by ISP1581, ISP1581 pulls into high level with DREQ and represents to have the DMA request, at this time needing CPLD#2 to provide DMA replys, if CPLD#2 has been ready to transmission, then CPLD#2 drags down answer signal DACK, afterwards by CPLD#2 control DIOR (reading)/DIOW (writing) and DATA[15:0] carry out the DMA read-write operation.

Claims (3)

1. circuit interface that is used for high-speed charge coupled camera, the data-interface of described high speed camera and PC is to adopt USB2.0 to constitute, it is characterized in that: described high-speed charge coupled camera adopts USB 2.0 interface chip ISP1581 as data-interface, and ISP1581 links to each other with the programmable logic device (CPLD) of making the control sensor; The initial configuration of ISP1581 adopts single chip computer AT 89852 to realize, the data address bus of AT89852 is linked to each other with the bus of ISP1581, and the IO mouth of CPLD linked to each other with the DMA mouth of ISP1581, CPLD is the DMA main frame, ISP1581 is the DMA slave, realizes the high speed DMA transmission between CPLD and the ISP1581.

2. according to the described circuit interface that is used for high-speed charge coupled camera of claim 1, it is characterized in that: go back and connect push-up storage FIFO between described CPLD and the ISP1581, avoid losing of data with this, and when computing machine can't in time be taken data away, data are cushioned.

3. according to the described circuit interface that is used for high-speed charge coupled camera of claim 1, it is characterized in that: the model of described CPLD is: M4A5-128/64.

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